Hi Daniel,
On Fri, May 15, 2015 at 10:17:33PM +0800, Daniel Kurtz wrote:
Hi Sascha,
On Tue, May 12, 2015 at 3:23 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
This adds support for some miscellaneous bits of the infracfg controller.
The mtk_infracfg_set/clear_bus_protection functions are
Noralf Trønnes nor...@tronnes.org writes:
Den 13.05.2015 21:00, skrev Eric Anholt:
This gives us a function for making mailbox property channel requests
of the firmware, which is most notable in that it will let us get and
set clock rates.
Signed-off-by: Eric Anholt e...@anholt.net
---
Juno contains a GICv2m extension for handling PCIe MSI messages.
Add a node declaring the first frame of the extension.
Signed-off-by: Liviu Dudau liviu.du...@arm.com
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 35 --
1 file changed, 21 insertions(+), 14
This driver will provide support for calls into the firmware that will
be used by other drivers like cpufreq and vc4.
---
v2: Improve commit message, point to mailbox.txt for how mboxes work.
v3: Use Lee's suggestion for mailbox phandle docs, fix spelling of
raspberry.
This board is based on Juno r0 with updated Cortex A5x revisions
and board errata fixes. It also contains coherent ThinLinks ports
on the expansion slot that allow for an AXI master on the daughter
card to participate in a coherency domain.
Support for SoC PCIe host bridge will be added as a
Hi Tony,
On May 18, 2015, at 20:03 , Tony Lindgren t...@atomide.com wrote:
* Robert Nelson robertcnel...@gmail.com [150518 09:51]:
On Mon, May 18, 2015 at 11:29 AM, Tony Lindgren t...@atomide.com wrote:
* Robert Nelson robertcnel...@gmail.com [150518 09:15]:
On Mon, May 18, 2015 at 10:21
This gives us a function for making mailbox property channel requests
of the firmware, which is most notable in that it will let us get and
set clock rates.
Signed-off-by: Eric Anholt e...@anholt.net
---
v2: Drop power-domains stuff for now since we don't have the driver
core support to make
* Robert Nelson robertcnel...@gmail.com [150518 09:15]:
On Mon, May 18, 2015 at 10:21 AM, Tony Lindgren t...@atomide.com wrote:
All the rev information is in the board's eeprom:
hexdump -e '8/1 %c' /sys/bus/i2c/devices/0-0050/eeprom -s 12 -n 4
Rev A5B
0A5B
Rev C
000C
Just another
+ linux-spi
On Mon, May 18, 2015 at 11:45:01AM +0100, Mark Rutland wrote:
On Fri, May 15, 2015 at 08:55:41PM +0100, Brian Norris wrote:
It really helps if I test patches...
On Thu, May 14, 2015 at 10:32:53AM -0700, Brian Norris wrote:
[...]
@@ -305,7 +305,7 @@ static const struct
Hi,
On Tue, May 05, 2015 at 10:42:36PM +0200, Arnd Bergmann wrote:
On Tuesday 05 May 2015 20:57:52 Aaro Koskinen wrote:
On Tue, May 05, 2015 at 12:02:04PM +0200, Arnd Bergmann wrote:
What does that main node actually do?
The common setup is that you have regular ehci/ohci/uhci
Here's a series to add a real clock provider on Raspberry Pi.
Previously, we've been using a mix of fixed clocks from clk-bcm2835.c
(though some of them failed to get used by their intended consumers),
and fixed-clock nodes in the DT.
This driver gives us the ability to enable/disable our clocks,
Signed-off-by: Eric Anholt e...@anholt.net
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi
b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index ace33f6..ac5f84c 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++
Nothing uses it, and I can't find any evidence that anything ever has.
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/clk/clk-bcm2835.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c
index 6b950ca..dd295e4 100644
---
We were previously using a fixed clock declared in the 2835 DT, but
it's actually the core clock, and it might not be the same if you had
adjusted it using the firmware's config.txt.
Signed-off-by: Eric Anholt e...@anholt.net
---
This is the only patch in the series I haven't really tested,
Unfortunately, the clock manager's registers are not accessible by the
ARM, so we have to request that the firmware modify our clocks for us.
This driver only registers the clocks at the point they are requested
by a client driver. This is partially to support returning
-EPROBE_DEFER when the
The hardware clocks are not controllable by the ARM, so we have to
make requests to the firmware to do so from the VPU side. This will
let us replace fixed clocks in our DT with actual clock control (and
correct frequency information).
Signed-off-by: Eric Anholt e...@anholt.net
---
This appears to have been copy-and-paste from another serial driver's
DT. The driver has never used this value -- instead, the pl011 driver
is getting the fixed 20201000.uart clock from clk-bcm2835.c.
Signed-off-by: Eric Anholt e...@anholt.net
---
arch/arm/boot/dts/bcm2835.dtsi | 1 -
1 file
This gets us a correct apb_pclk, which previously was accidentally
using the 20201000.uart clock from clk-bcm2835.c, due to the
fallback clk_get_sys() path.
Signed-off-by: Eric Anholt e...@anholt.net
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 7 +++
arch/arm/boot/dts/bcm2835.dtsi | 2 +-
2
Add DT binding documentation for lpc1850-ccu clk driver.
Signed-off-by: Joachim Eastwood manab...@gmail.com
---
.../devicetree/bindings/clock/lpc1850-ccu.txt | 146 +
1 file changed, 146 insertions(+)
create mode 100644
Add driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU
provides fine grained gating of most clocks present in the SoC.
Signed-off-by: Joachim Eastwood manab...@gmail.com
---
drivers/clk/nxp/Makefile| 1 +
drivers/clk/nxp/clk-lpc18xx-ccu.c | 305
Hi Enrico,
On 18/05/15 13:27, Enrico Weigelt, metux IT consult wrote:
Am 16.05.2015 um 00:35 schrieb Philippe Reynes:
The mxc RTC needs two clocks, one for the input
reference, and one for the IP. But this driver
was only using one clock (for the reference).
This patch add the second clock
On 05/18/2015 02:05 PM, Aaro Koskinen wrote:
Hi,
On Mon, Mar 16, 2015 at 06:06:00PM +0300, Aleksey Makarov wrote:
The OCTEON MMC controller is currently found on cn61XX and cnf71XX
devices. Device parameters are configured from device tree data.
eMMC, MMC and SD devices are supported.
On 18/05/2015 at 14:30:50 -0500, Zhi Li wrote :
On Mon, May 18, 2015 at 3:45 AM, Philipp Zabel p.za...@pengutronix.de wrote:
Hi Frank,
Am Freitag, den 15.05.2015, 21:36 +0800 schrieb frank...@freescale.com:
From: Frank Li frank...@freescale.com
snvs is MFP device. Change dts to use
This patch adds a MAINTAINERS entry for APM X-Gene SoC EDAC driver.
Signed-off-by: Loc Ho l...@apm.com
---
MAINTAINERS |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 00a586b..0134fee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@
On Mon, May 18, 2015 at 08:04:14PM +0900, Yoshihiro Shimoda wrote:
Since the HSUSB controllers of R-Car Gen2 are the same specification
(they have 16 pipes and usb-dmac), this patch changes USBHS_TYPE_R8A7790
and USBHS_TYPE_R8A7791 to USBHS_TYPE_RCAR_GEN2.
Signed-off-by: Yoshihiro Shimoda
Hi Geert,
On Mon, May 18, 2015 at 08:51:46PM +0200, Geert Uytterhoeven wrote:
On Mon, May 18, 2015 at 8:34 PM, Brian Norris
computersforpe...@gmail.com wrote:
On Mon, May 18, 2015 at 11:45:01AM +0100, Mark Rutland wrote:
On Fri, May 15, 2015 at 08:55:41PM +0100, Brian Norris wrote:
It
This patch set is based on Felipe's usb.git / testing/next branch.
(commit id = 1c14905ef951fb968c8da90e4e64be02c309a2ae)
This patch set adds support for R-Car E2. This patch set also changes
the SoC types from #define values to enum values.
Yoshihiro Shimoda (2):
usb: renesas_usbhs: Change
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