Hello Heiko,
On 06/02/2015 11:15 PM, Heiko Stübner wrote:
> Am Dienstag, 2. Juni 2015, 10:11:03 schrieb Javier Martinez Canillas:
>> Hello,
>>
>> Newer Chromebooks have more than one Embedded Controller (EC) in the
>> system. These additional ECs are connected through I2C with a host EC
>> which
Hi Rob,
On Wed, Jun 3, 2015 at 12:46 AM, Rob Herring wrote:
> With the addition of overlays, it is now plausible to use DT on any arch
> and without an arch using it at boot time. It is also desirable to
> expand the compile coverage of the DT code. Make CONFIG_OF user
> selectable by converting
Ping!
> -Original Message-
> From: Kedareswara rao Appana [mailto:appana.durga@xilinx.com]
> Sent: Thursday, May 21, 2015 10:40 PM
> To: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
> ijc+devicet...@hellion.org.uk; Michal Simek; ga...@codeaurora.org;
> app...@xilinx.c
Signed-off-by: Shengzhou Liu
---
v2: rebase
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 8033919..4d0929f 100644
--- a
On Monday 11 May 2015 08:15 PM, Kishon Vijay Abraham I wrote:
On Tuesday 05 May 2015 11:43 PM, Ezequiel Garcia wrote:
Hi Kishon,
This series adds support for the USB2.0 PHY present on the IMG Pistachio SoC.
Based on mips-for-linux-next and tested on the IMG Pistachio BuB. If possible,
I
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y
With the latest dtc import include fixups, it is no longer necessary to
add explicit include paths to use libfdt. Remove these across the
kernel.
Signed-off-by: Rob Herring
Cc: Ralf Baechle
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Grant Likely
Cc: linux-m...@lin
On 02-06-15, 11:31, Stephen Boyd wrote:
> Also, is there already code written to handle these new
> bindings in the OPP library? If not, it would be good to write
> some to flush out any problems that may be lurking in actual
> implementation.
I had written code earlier for V2 or something, but th
On Tue, Jun 2, 2015 at 2:05 AM, Linus Walleij wrote:
> On Wed, May 27, 2015 at 5:26 AM, Gregory Fong wrote:
>> I've now actually attempted to use the gpiolib irqchip code. This
>> driver can't directly use gpiochip_irqchip_add() because of the
>> multiple gpiochip : one irqchip map. At first, I
Hello Mark, Rob and other ARM64 DT maintainers,
Could you help to ack this patch?
Thanks for your time.
Bintian
On 2015/5/30 9:51, Bintian Wang wrote:
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.
Hi Jon,
On Wed, Jun 3, 2015 at 10:40 AM, jonsm...@gmail.com wrote:
> On Tue, Jun 2, 2015 at 8:35 PM, Julian Calaby wrote:
>> Hi Jon,
>>
>> On Wed, Jun 3, 2015 at 6:20 AM, jonsm...@gmail.com
>> wrote:
>>> Resend with plain text for image links
>>>
>>> I have one of these GA10H-A33 and tore
On Tue, Jun 2, 2015 at 8:35 PM, Julian Calaby wrote:
> Hi Jon,
>
> On Wed, Jun 3, 2015 at 6:20 AM, jonsm...@gmail.com wrote:
>> Resend with plain text for image links
>>
>> I have one of these GA10H-A33 and tore it apart. They used an uncommon
>> wifi/BT chip - RDA5990P. Took mine apart since
Hi Jon,
On Wed, Jun 3, 2015 at 6:20 AM, jonsm...@gmail.com wrote:
> Resend with plain text for image links
>
> I have one of these GA10H-A33 and tore it apart. They used an uncommon
> wifi/BT chip - RDA5990P. Took mine apart since the wifi didn't work worth
> two cents.
> http://www.rdaic.com
With the addition of overlays, it is now plausible to use DT on any arch
and without an arch using it at boot time. It is also desirable to
expand the compile coverage of the DT code. Make CONFIG_OF user
selectable by converting the menu to menuconfig.
Signed-off-by: Rob Herring
Cc: Geert Uytterh
In preparation to allow users to enable DeviceTree without arch or
machine selecting it, we need to fix build errors on MIPS. When
CONFIG_OF is enabled, device_tree_init cannot be resolved. This is
trivially fixed by using CONFIG_USE_OF instead of CONFIG_OF for prom.h.
Signed-off-by: Rob Herring
There are a couple of reasons we'd like to have CONFIG_OF be user
visible and enabled. The first is DT overlays can be used on
architectures regardless of whether they use DT for booting. One example
is running DT unittests on x86. The second is simply to expand the
compile coverage of the DT c
In order to get iio-hwmon support, the lradc must be declared as an
iio provider. So fix this issue by adding the #io-channel-cells property.
Signed-off-by: Stefan Wahren
Fixes: bd798f9c7b30 ("ARM: dts: mxs: Add iio-hwmon to mx23 soc")
---
arch/arm/boot/dts/imx23.dtsi |1 +
1 file changed, 1
On Tue, Jun 02, 2015 at 08:32:59PM +0200, Hans de Goede wrote:
> Hi,
>
> On 06/02/2015 05:58 PM, Maxime Ripard wrote:
> >On Mon, Jun 01, 2015 at 05:02:59PM +0200, Hans de Goede wrote:
> >>The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been
> >>using
> >>the same dts for both
On Tue, Jun 02, 2015 at 10:08:01PM +0200, Hans de Goede wrote:
> Hi Maxime,
>
> I forgot to test and update the tabletkeys setting, even though that was
> the whole reason for not sending this file before.
>
> This v2 has a fixed tabletkeys section.
Applied, thanks!
Maxime
--
Maxime Ripard, F
Am Dienstag, 2. Juni 2015, 10:11:03 schrieb Javier Martinez Canillas:
> Hello,
>
> Newer Chromebooks have more than one Embedded Controller (EC) in the
> system. These additional ECs are connected through I2C with a host EC
> which is the one that is connected to the Application Processor (AP)
> t
Ethernet AVB includes an Gigabit Ethernet controller (E-MAC) that is basically
compatible with SuperH Gigabit Ethernet E-MAC. Ethernet AVB has a dedicated
direct memory access controller (AVB-DMAC) that is a new design compared to the
SuperH E-DMAC. The AVB-DMAC is compliant with 3 standards for
Resend with plain text for image links
I have one of these GA10H-A33 and tore it apart. They used an uncommon
wifi/BT chip - RDA5990P. Took mine apart since the wifi didn't work worth
two cents.
http://www.rdaic.com/sites/default/files/public/RDA5990P_datasheet_V1.4.pdf
Is that unpopulated pa
Find the configured DMA controller by asking for a DMA channel in the
probe phase and releasing it right after. The controller device can be
found via the dma_chan struct and the controller is recognized from
the compatible property of its device node. The patch assumes EDMA if
there is no device n
Hi Maxime,
I forgot to test and update the tabletkeys setting, even though that was
the whole reason for not sending this file before.
This v2 has a fixed tabletkeys section.
Regards,
Hans
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to major
The ga10h is an 10" tablet with an A33 or A23 soc, 1G RAM, 8G or 16G nand,
sdio wifi, 2 micro usb ports, 1 otg and 1 host and 1 micro sd slot.
This commit adds a dts file for the v1.1 pcb with an a33 soc.
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/Makefile | 1 +
arch/
On 06/02/15 19:16, Misael Lopez Cruz wrote:
Jyri,
On 06/02/2015 08:49 AM, Jyri Sarha wrote:
Find the configured DMA controller by asking for a DMA channel in the
probe phase and releasing it right after. The controller device can be
found via the dma_chan struct and the controller is recognized
* Felipe Balbi [150602 12:26]:
> On Wed, May 06, 2015 at 12:25:33PM -0500, Dave Gerlach wrote:
> > Add node for TI AM4372 EMIF.
> >
> > Signed-off-by: Dave Gerlach
>
> Tony, this patch fixes the regression I just reported at [1], care to
> pick this one up ?
OK thanks yes tag this for v4.2 fix
On Fri, May 22, 2015 at 04:54:17PM +0100, Srinivas Kandagatla wrote:
> From: Arnd Bergmann
>
> This patch is a fixup to correct dependencies in patch 9bae4880acee
> ("ASoC: qcom: move ipq806x specific bits out of lpass driver.")
>
> Originally this change-set was suggested by Arnd on mailing lis
On Fri, May 22, 2015 at 04:54:07PM +0100, Srinivas Kandagatla wrote:
> + if (cpu_dai->id == MI2S_QUATERNARY) {
> + /* Configure the Quat MI2S to TLMM */
> + writel(readl(pdata->mic_iomux) |
> + MIC_CTRL_QUA_WS_SLAVE_SEL_10 |
> + M
The ga10h is an 10" tablet with an A33 or A23 soc, 1G RAM, 8G or 16G nand,
sdio wifi, 2 micro usb ports, 1 otg and 1 host and 1 micro sd slot.
This commit adds a dts file for the v1.1 pcb with an a33 soc.
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/Makefile | 1 +
arch/
Hello.
On 06/02/2015 07:49 PM, Cyrille Pitchen wrote:
This patches documents the new bindings for the Flexcom clock, which will
be introduced by Atmel sama5d2x chips.
Signed-off-by: Cyrille Pitchen
---
.../devicetree/bindings/clock/at91-clock.txt | 20
1 file
On 06/02/2015 01:35 PM, Alan Tull wrote:
> Support suspend to ram on socfpga.
> * allocate space in ocram using sram driver.
> * Add a function in ocram to place DDR in self-refresh
> and suspend.
> * Prevent suspend if EDAC is enabled.
> * Add a device tree binding document for the Alt
Hi Anda,
On Fri, May 29, 2015 at 05:25:42PM +0300, Anda-Maria Nicolae wrote:
> The next 3 patches do the following:
> - first patch adds Richtek Technology Corporation in the vendor-prefixes list
> - second patch adds device tree binding example for Richtek RT9455 battery
> charger
> - third patc
This patch adds syscon poweroff device node to support poweroff feature
on APM X-Gene Mustang platform
Signed-off-by: Tai Nguyen
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/b
This patch adds syscon reboot device node to support reboot feature on APM
X-Gene platform
Signed-off-by: Feng Kan
Signed-off-by: Tai Nguyen
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b
On Wed, May 06, 2015 at 12:25:33PM -0500, Dave Gerlach wrote:
> Add node for TI AM4372 EMIF.
>
> Signed-off-by: Dave Gerlach
Tony, this patch fixes the regression I just reported at [1], care to
pick this one up ?
Tested-by: Felipe Balbi
Acked-by: Felipe Balbi
[1] http://marc.info/?l=linux-o
This patch set adds syscon reboot/poweroff device nodes to support reboot and
poweroff features on X-Gene platform.
Tai Nguyen (2):
power: reset: Add syscon reboot device node for APM X-Gene platform
power: reset: Add syscon poweroff device node for APM X-Gene Mustang platform
arch/arm64/bo
On Tue, Jun 02, 2015 at 11:31:20AM -0700, Stephen Boyd wrote:
> On 05/28, Viresh Kumar wrote:
> > + opp-supply = <&cpu_supply0>;
> opp-supply isn't mentioned anywhere. Is that intentional? Is it
> supposed to be cpu-supply still? It isn't clear to me from the
I'm also a bit wor
On Mon, Jun 01, 2015 at 04:09:35PM -0600, Loc Ho wrote:
> The new x-gene EDAC driver incorrectly tried to figure out the version of
> one of its IP blocks by looking at the version of the CPU core, which is
> only vagely related.
>
> This removes the incorrect code and instead uses the version of
Signed-off-by: Peter Seiderer
Tested-by: Eric Nelson
---
v1:
- do the same for the sabrelite board as suggested/tested
by Eric Nelson
---
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-s
Regulator stuff copied from imx6qdl-tx6.dtsi, pin configuration
taken from Boundary Devices linux kernel tree ([1] and [2]).
[1]
https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_3.10.17_1.0.2_ga/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
[2]
https://github.com/boundarydevices/linux
Add code that requests that the sdr controller go into
self-refresh mode. This code is run from ocram.
Suspend-to-RAM and EDAC support are mutually exclusive on
SOCFPGA. If the EDAC is enabled, it will prevent the
platform from going into suspend.
Example of how to request to suspend to ram:
$
Support suspend to ram on socfpga.
* allocate space in ocram using sram driver.
* Add a function in ocram to place DDR in self-refresh
and suspend.
* Prevent suspend if EDAC is enabled.
* Add a device tree binding document for the Altera
SOCFPGA SDRAM controller that is used to put
Add binding doc for Altera SOCFPGA SDRAM controller.
Signed-off-by: Alan Tull
---
v4: Add bindings doc
v5: No change for v5
v6: No change for v6
---
.../arm/altera/socfpga-sdram-controller.txt| 12
1 file changed, 12 insertions(+)
create mode 100644
Documentation/devicet
On Wed, 6 May 2015, Dave Gerlach wrote:
> Without a hwmod for am43xx emif use counting for emif clockdomain does
> not happen correctly so it may be shut off by pm code unintentionally.
>
> Signed-off-by: Dave Gerlach
Thanks, sent upstream for v4.2.
- Paul
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To unsubscribe from this list: se
On Tue, 26 May 2015, Pali Rohár wrote:
> Hi Paul,
>
> this patch is also for omap2... Can you review it too?
>
> On Saturday 28 February 2015 17:24:36 Pavel Machek wrote:
> > On Thu 2015-02-26 14:49:52, Pali Rohár wrote:
> > > Register crypto hwmod links only if they are not disabled in DT.
> >
Hi,
On 06/02/2015 05:58 PM, Maxime Ripard wrote:
On Mon, Jun 01, 2015 at 05:02:59PM +0200, Hans de Goede wrote:
The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been using
the same dts for both models. Unfortunately this does not work for the otg
controller, on the M9 this is
On 05/28, Viresh Kumar wrote:
> Current OPP (Operating performance point) device tree bindings have been
> insufficient due to the inflexible nature of the original bindings. Over
> time, we have realized that Operating Performance Point definitions and
> usage is varied depending on the SoC and a
On Tue, Jun 2, 2015 at 6:45 AM, Linus Walleij wrote:
> On Fri, May 29, 2015 at 4:14 AM, Gregory Fong wrote:
>
>> Several drivers (e.g. gpio-keys) allow for GPIOs to be configured as
>> wakeup sources, and this GPIO controller supports that through a
>> separate interrupt path.
>>
>> The de-facto
On Fri, May 29, 2015 at 5:43 PM, Brian Norris
wrote:
> On Thu, May 28, 2015 at 07:14:08PM -0700, Gregory Fong wrote:
>> Several drivers (e.g. gpio-keys) allow for GPIOs to be configured as
>> wakeup sources, and this GPIO controller supports that through a
>> separate interrupt path.
>>
>> The de-
On 06/02/2015 11:55 AM, Fu Wei wrote:
+static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
+{
+ struct sbsa_gwdt *gwdt = (struct sbsa_gwdt *)dev_id;
+ struct watchdog_device *wdd = &gwdt->wdd;
+
+ if (wdd->pretimeout)
+ /* The pretimeout is valid, go pan
On 02/06/2015 at 19:04:35 +0200, Boris Brezillon wrote :
> Hi Cyrille,
>
> On Tue, 2 Jun 2015 18:57:19 +0200
> Cyrille Pitchen wrote:
>
> > This driver supports the new Atmel Flexcom. The Flexcom is a wrapper which
> > integrates one SPI controller, one I2C controller and one USART. Only one
> >
On 06/02/2015 09:55 AM, Fu Wei wrote:
Hi Timur,
Thanks , feedback inline
On 2 June 2015 at 23:32, Timur Tabi wrote:
On 06/01/2015 11:05 PM, fu@linaro.org wrote:
+/*
+ * help functions for accessing 32bit registers of SBSA Generic Watchdog
+ */
+static void sbsa_gwdt_cf_write(unsigned in
Hi Cyrille,
On Tue, 2 Jun 2015 18:57:19 +0200
Cyrille Pitchen wrote:
> This driver supports the new Atmel Flexcom. The Flexcom is a wrapper which
> integrates one SPI controller, one I2C controller and one USART. Only one
> function can be enabled at a time. This driver selects the function once
Le 02/06/2015 18:49, Cyrille Pitchen a écrit :
> Signed-off-by: Cyrille Pitchen
>
> This driver supports the new Atmel Flexcom. The Flexcom is a wrapper which
> integrates one SPI controller, one I2C controller and one USART. Only one
> function can be enabled at a time. This driver selects the f
This driver supports the new Atmel Flexcom. The Flexcom is a wrapper which
integrates one SPI controller, one I2C controller and one USART. Only one
function can be enabled at a time. This driver selects the function once for
all, when the Flexcom is probed, according to the value of the new
"atmel
ChangeLog
v2:
- fix commit message
v1:
This series of patches introduces a new driver for the Atmel Flexcom.
Cyrille Pitchen (2):
clk: at91: add a new compatible string for Flexcom in the DT
documentation
clk: at91: add Flexcom clock
.../devicetree/bindings/clock/at91-clock.txt |
This patches documents the new bindings for the Flexcom clock, which will
be introduced by Atmel sama5d2x chips.
Signed-off-by: Cyrille Pitchen
---
.../devicetree/bindings/clock/at91-clock.txt | 20
1 file changed, 20 insertions(+)
diff --git a/Documentation/devicet
Hi Timur,
Thanks , feedback inline
On 2 June 2015 at 23:32, Timur Tabi wrote:
> On 06/01/2015 11:05 PM, fu@linaro.org wrote:
>
>> +/*
>> + * help functions for accessing 32bit registers of SBSA Generic Watchdog
>> + */
>> +static void sbsa_gwdt_cf_write(unsigned int reg, u32 val,
>> +
Signed-off-by: Cyrille Pitchen
This driver supports the new Atmel Flexcom. The Flexcom is a wrapper which
integrates one SPI controller, one I2C controller and one USART. Only one
function can be enabled at a time. This driver selects the function once for
all, when the Flexcom is probed, accordi
ChangeLog
v1:
This series of patches introduces a new driver for the Atmel Flexcom.
Cyrille Pitchen (2):
clk: at91: add a new compatible string for Flexcom in the DT
documentation
clk: at91: add Flexcom clock
.../devicetree/bindings/clock/at91-clock.txt | 20 +++
arch/arm/mach-at
This patches documents the new bindings for the Flexcom clock, which will
be introduced by Atmel sama5d2x chips.
Signed-off-by: Cyrille Pitchen
---
.../devicetree/bindings/clock/at91-clock.txt | 20
1 file changed, 20 insertions(+)
diff --git a/Documentation/devicet
On Tue, Jun 02, 2015 at 11:05:21AM +0200, Linus Walleij wrote:
> ... and have the
> IRQ handler return IRQ_NONE if the IRQ comes from this
> bank, or IRQ_HANDLED if it has handled an IRQ from its own
> space.
I'm not sure that's worded correctly or not, but... fwiw, all IRQ handlers
_should_ be re
Jyri,
On 06/02/2015 08:49 AM, Jyri Sarha wrote:
Find the configured DMA controller by asking for a DMA channel in the
probe phase and releasing it right after. The controller device can be
found via the dma_chan struct and the controller is recognized from
the compatible property of its device n
On 06/01/2015 09:05 PM, fu@linaro.org wrote:
From: Fu Wei
Also update Documentation/watchdog/watchdog-kernel-api.txt to
introduce:
(1)the new elements in the watchdog_device and watchdog_ops struct;
(2)the new API "watchdog_init_timeouts"
Reasons:
(1)kernel already has two watchdog drivers
On Mon, Jun 01, 2015 at 05:02:59PM +0200, Hans de Goede wrote:
> The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been using
> the same dts for both models. Unfortunately this does not work for the otg
> controller, on the M9 this is routed to a micro-usb connector on the outside
> I was thinking the same so I have tried to cherry-pick the patch on a 3.10.79
> and it didn't cause any conflicts so I thought it could be sent to stable as
> is.
OK, so reducing context seems to help. Thanks for checking!
signature.asc
Description: Digital signature
On Wed, Jun 03, 2015 at 12:36:28AM +0900, Wolfram Sang wrote:
>
> > If you send a new version, could you add stable in Cc to patch 3/6:
>
> No need to send a new version just because of an additional ack. I can
> apply that. However...
>
> > Cc: sta...@vger.kernel.org #3.10 and later
> > If not,
On 02-06-15 09:50, Paul Bolle wrote:
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(&i2c->dev, "%s(%u) %#x %#x\n", __func__,
On 06/02/2015 05:28 AM, Linus Walleij wrote:
On Tue, May 26, 2015 at 9:41 PM, Stephen Warren wrote:
On 05/25/2015 08:53 AM, Tomeu Vizoso wrote:
Specify how the GPIOs map to the pins in T124, so the dependency is
explicit.
Signed-off-by: Tomeu Vizoso
---
arch/arm/boot/dts/tegra124.dtsi |
On 06/02/2015 08:32 AM, Timur Tabi wrote:
On 06/01/2015 11:05 PM, fu@linaro.org wrote:
+/*
+ * help functions for accessing 32bit registers of SBSA Generic Watchdog
+ */
+static void sbsa_gwdt_cf_write(unsigned int reg, u32 val,
+ struct watchdog_device *wdd)
+{
+struc
> If you send a new version, could you add stable in Cc to patch 3/6:
No need to send a new version just because of an additional ack. I can
apply that. However...
> Cc: sta...@vger.kernel.org #3.10 and later
> If not, Wolfram could you do it please?
The problem with 3/6 is that it seems to dep
On Tue, Jun 2, 2015 at 7:20 AM, Ilya Faenson wrote:
> Hi Rob,
>
> Appreciate your insights.
>
> -Original Message-
> From: Rob Herring [mailto:robherri...@gmail.com]
> Sent: Monday, June 01, 2015 8:19 PM
> To: Ilya Faenson
> Cc: Marcel Holtmann; linux-blueto...@vger.kernel.org;
> devicetr
Hi, Jacek!
On Tue, Jun 02, 2015 at 11:13:54AM +0200, Jacek Anaszewski wrote:
> Hi Sakari,
>
> On 06/01/2015 10:59 PM, Sakari Ailus wrote:
> >Hi Jacek,
> >
> >On Mon, May 25, 2015 at 05:13:57PM +0200, Jacek Anaszewski wrote:
> >>This patch adds helper functions for registering/unregistering
> >>LE
On 06/01/2015 11:05 PM, fu@linaro.org wrote:
+/*
+ * help functions for accessing 32bit registers of SBSA Generic Watchdog
+ */
+static void sbsa_gwdt_cf_write(unsigned int reg, u32 val,
+ struct watchdog_device *wdd)
+{
+ struct sbsa_gwdt *gwdt = to_sbsa_g
Hi Cyrille,
For the whole serie:
Acked-by: Ludovic Desroches
If you send a new version, could you add stable in Cc to patch 3/6:
Cc: sta...@vger.kernel.org #3.10 and later
If not, Wolfram could you do it please?
Thanks
Ludovic
On Tue, Jun 02, 2015 at 03:18:30PM +0200, Cyrille Pitchen wrote:
>
Hi,
On Mon, Jun 01, 2015 at 11:28:23AM +0200, Hans de Goede wrote:
> On 01-06-15 11:22, Maxime Ripard wrote:
> >On Sun, May 31, 2015 at 06:10:25PM +0200, Hans de Goede wrote:
> >>+ /* We either want both gpio pins or neither (when in host mode) */
> >>+ if (!data->id_det_gpio != !data->vbus_de
On Sun, May 31, 2015 at 06:10:26PM +0200, Hans de Goede wrote:
> This is based on initial code to get the Allwinner sunxi musb controller
> supported by Chen-Yu Tsai and Roman Byshko.
>
> This adds support for the Allwinner sunxi musb controller in both host only
> and otg mode. Peripheral only mo
Hi,
On Tue, Jun 02, 2015 at 09:14:05AM +0200, Hans de Goede wrote:
> >>>Here is an updated version of the remaining (not yet merged in Felipe's
> >>>tree)
> >>>sunxi musb patches.
> >>>
> >>>The "phy-sun4i-usb: Add full support for usb0 phy / OTG" patch has been
> >>>updated with a small bug-fix a
Hello.
On 6/2/2015 4:18 PM, Cyrille Pitchen wrote:
The probe() function now prints the hardware version of the I2C
controller.
Signed-off-by: Cyrille Pitchen
---
drivers/i2c/busses/i2c-at91.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/i2c/busses/i2c-at91.c b/driver
For now this improvement is only used with TX DMA transfers. The data
width must be set properly when configuring the DMA controller. Also
the FIFO configuration must be set to match the DMA transfer data
width:
TXRDYM (Transmitter Ready Mode) and RXRDYM (Receiver Ready Mode) must
be set into the F
Depending on the hardware, TX and RX FIFOs may be available. The RX
FIFO can avoid receive overruns, especially when DMA transfers are
not used to read data from the Receive Holding Register. For heavy
system load, The CPU is likely not be able to fetch data fast enough
from the RHR.
In addition,
This patch updates macro definitions in atmel_serial.h to fit the
80 column rule.
Please note that some deprecated comments such as "[AT91SAM9261 only]"
are removed as the corresponding bits also exist in some later chips.
The patch also fix macro definitions in atmel_serial.c to replace
(port,v)
add 3 new properties:
- "atmel,fifo-size": to enable FIFO support
- "atmel,rts-low-threshold" and "atmel,rts-high-threshold": to control
the hardware handshake flow control.
Signed-off-by: Cyrille Pitchen
---
Documentation/devicetree/bindings/serial/atmel-usart.txt | 15 +++
1 file
ChangeLog
v1:
This series of patches add support to FIFOs which will be introduced with Atmel
sama5d2x SoC.
FIFOs allow to reduce the number of I/O access. Indeed depending on the data
size and the USART mode, FIFOs work in either single or multiple data. For
multiple data, up to 4 data can be wr
Find the configured DMA controller by asking for a DMA channel in the
probe phase and releasing it right after. The controller device can be
found via the dma_chan struct and the controller is recognized from
the compatible property of its device node. The patch assumes EDMA if
there is no device n
On Fri, May 29, 2015 at 4:14 AM, Gregory Fong wrote:
> Several drivers (e.g. gpio-keys) allow for GPIOs to be configured as
> wakeup sources, and this GPIO controller supports that through a
> separate interrupt path.
>
> The de-facto standard DT property "wakeup-source" is checked, since
> that
On Fri, May 29, 2015 at 4:14 AM, Gregory Fong wrote:
> Out of the brcmstb SoCs that I know, BCM3390 has the largest numbers
> of GPIOs, with its
> - 320 "peripheral" GPIOs
> - 5*32 = 160 UPG GPIOs (counting unused lines, which do get counted)
> - 2*32 = 64 UPG AON GPIOs (counting unused lines)
>
On Fri, May 29, 2015 at 4:14 AM, Gregory Fong wrote:
> Select ARCH_WANT_OPTIONAL_GPIOLIB from BRCMSTB to allow GPIOLIB and
> GPIO_BRCMSTB to be enabled.
>
> Signed-off-by: Gregory Fong
Acked-by: Linus Walleij
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe de
On Fri, May 29, 2015 at 4:14 AM, Gregory Fong wrote:
> This adds support for the GPIO IP "UPG GIO" used on Broadcom STB SoCs
> (BCM7XXX and some others). Uses basic_mmio_gpio to instantiate a
> gpio_chip for each bank. The driver assumes that it handles the base
> set of GPIOs on the system and
On Tue, Jun 02, 2015 at 02:33:33PM +0530, Rameshwar Prasad Sahu wrote:
> This patch fixes sparse warnings like incorrect type in assignment
> (different base types), cast to restricted __le64.
>
I am appliying this but ideally you should have split thsi into seprate
patches for each fix
--
~Vino
On Fri, May 29, 2015 at 4:14 AM, Gregory Fong wrote:
> Create an irq_chip for each GIO block. Uses chained IRQ handling since
> known uses of this block have a BCM7120 L2 interrupt controller as a
> parent. Supports interrupts for all GPIOs.
>
> In the IRQ handler, we check for raised IRQs for
For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.
In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
the TXCOMP interrupt may be enabled
add a new value "atmel,at91sama5d2-i2c" for the "compatible" property.
add a new optional property "atmel,fifo-size" to enable FIFO support when
available.
add missing optional properties "dmas" and "dma-names".
Signed-off-by: Cyrille Pitchen
---
Documentation/devicetree/bindings/i2c/i2c-at91.tx
The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.
This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register wa
When FIFOs are available and enabled, the driver now configures the Atmel
eXtended DMA Controller to perform word accesses instead of byte accesses
when possible.
The actual access width depends on the size of the buffer to transmit.
To enable FIFO support the "atmel,fifo-size" property must be se
This patch just fixes typo before applying later patches which will use
register bits with index above 16.
Signed-off-by: Cyrille Pitchen
---
drivers/i2c/busses/i2c-at91.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/i2c/busses/i2c-a
The probe() function now prints the hardware version of the I2C
controller.
Signed-off-by: Cyrille Pitchen
---
drivers/i2c/busses/i2c-at91.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 67b4f15..340ce2e 100644
--- a/d
ChangeLog
v3:
- fix braces {} coding style issue
- split the alternative command patch into 2 patches: the first one fixes
a race condition whereas the second one is the actual alternative command
patch
v2:
- fix typo in comment for AT91_TWI_SVEN.
- document new device tree bindings like "atm
On Fri, May 29, 2015 at 05:32:50PM +0300, Peter Ujfalusi wrote:
> On 05/29/2015 01:18 PM, Vinod Koul wrote:
> > On Fri, May 29, 2015 at 11:42:27AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, May 29, 2015 at 11:33 AM, Vinod Koul wrote:
> >>> On Tue, May 26, 2015 at 04:25:57PM +0300, Peter Ujfalus
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