adds bindings for CEVA AHCI SATA controller. optional property
broken-gen2 is useful incase of hardware speed limitation.
Signed-off-by: Suneel Garapati suneel.garap...@xilinx.com
---
Documentation/devicetree/bindings/ata/ahci-ceva.txt | 20
1 file changed, 20 insertions(+)
Adds support for Ceva sata host controller on Xilinx
Zynq UltraScale+ MPSoC.
Signed-off-by: Suneel Garapati suneel.garap...@xilinx.com
---
Changes v2
- Change module license string to GPL v2
---
drivers/ata/Kconfig | 9 ++
drivers/ata/Makefile| 1 +
drivers/ata/ahci_ceva.c | 225
Hi,
I'm working on a new board and one feature it as is a plug-in module
with an ADS7830 voltage monitor on it. This will be used during
manufacturing to sanity check that various voltage rails are within
expected ranges.
I have a dts entry for the device as below (with some omissions for the
Hi Chris,
On 06/04/2015 11:03 PM, Chris Packham wrote:
Hi,
I'm working on a new board and one feature it as is a plug-in module
with an ADS7830 voltage monitor on it. This will be used during
manufacturing to sanity check that various voltage rails are within
expected ranges.
I have a dts
Hello,
This patchset implements SoC bus support for Freescale Vybrid platform,
implementing the following
https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-devices-soc
and is the fifth revision. Tested on a Colibri VF61 module after
rebasing on shawn's for-next branch.
Arnd and Shawn I
On Fri, May 29, 2015 at 11:38:44AM -0500, Rob Herring wrote:
Combine the ChipIdea USB binding into a single document to reduce
duplication and fragmentation. This marks use of the old PHY bindings as
deprecated. Future compatible bindings should use generic PHY binding.
Signed-off-by: Rob
On 2015/6/4 21:23, James Morse wrote:
On 03/06/15 09:35, Zhou Wang wrote:
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
new file mode 100644
index 000..2a4d72e
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi.c
New file? Please update MAINTAINERS.
(Also add
Hi YH,
2015-06-05 8:15 GMT+02:00 YH Huang yh.hu...@mediatek.com:
On Mon, 2015-05-25 at 10:14 +0800, Yingjoe Chen wrote:
On Thu, 2015-05-21 at 21:29 +0800, YH Huang wrote:
This patch series add the use of display PWM driver and documentation
for Mediatek SoCs. The driver is used to support
On Thu, Jun 04, 2015 at 05:27:28PM -0500, Dinh Nguyen wrote:
This is my mistake. I applied Alan Tull's patch for suspend-to-ram which
also touches drivers/edac/altera_edac.c.
This adds a SoC driver to be used by the Freescale Vybrid SoC's.
We create the fsl directory for holding the different Freescale
designs. Driver utilises syscon to get the various register values
needed. After this sysfs exposes some SoC specific properties as
below:
cd /sys/devices/soc0
ls
Add a device tree node for the On-Chip One Time Programmable
Controller (OCOTP) and the On-Chip ROM.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/boot/dts/vfxxx.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/vfxxx.dtsi
On 04/06/15 23:07, Stephen Boyd wrote:
On 05/22, Daniel Thompson wrote:
+
+#include linux/clk.h
Are you using this include?
+#include linux/clkdev.h
Are you using this include?
Not very much?
Turns out I was relying on these to get kzalloc() defined but there are
better headers for me
On 06/05/2015 08:02 AM, Suneel Garapati wrote:
Adds support for Ceva sata host controller on Xilinx
Zynq UltraScale+ MPSoC.
Signed-off-by: Suneel Garapati suneel.garap...@xilinx.com
---
Changes v2
- Change module license string to GPL v2
---
drivers/ata/Kconfig | 9 ++
On Mon, 2015-05-25 at 10:14 +0800, Yingjoe Chen wrote:
On Thu, 2015-05-21 at 21:29 +0800, YH Huang wrote:
This patch series add the use of display PWM driver and documentation
for Mediatek SoCs. The driver is used to support the backlight of
the panel. This is based on v4.1-rc1.
YH Huang
On Fri, May 29, 2015 at 11:38:45AM -0500, Rob Herring wrote:
Currently, ci_default_pdata is common to all instances of the driver and
gets modified by the core driver code. This is bad if there are multiple
instances of the device with different settings such as the phy type. Fix
this by
On Fri, May 29, 2015 at 11:38:46AM -0500, Rob Herring wrote:
The Marvell 28nm HSIC PHY requires the port to be forced to HS mode after
the port power is applied. This is done using the test mode in the PORTSC
register.
As HSIC is always HS, this work-around should be safe to do with all HSIC
On 06/05/2015 08:02 AM, Suneel Garapati wrote:
adds bindings for CEVA AHCI SATA controller. optional property
broken-gen2 is useful incase of hardware speed limitation.
Signed-off-by: Suneel Garapati suneel.garap...@xilinx.com
---
Documentation/devicetree/bindings/ata/ahci-ceva.txt | 20
On Friday 05 June 2015 06:03:30 Chris Packham wrote:
Is there a better way of getting the devicetree machinery to avoid the
call to the driver probe function in the first place?
The newly added DT overlay support should do what you need, but it might
not be the easiest solution.
To
On 2015/6/4 21:19, James Morse wrote:
On 03/06/15 09:35, Zhou Wang wrote:
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init. Also set
On Thu, Jun 04, 2015 at 11:19:30PM +0100, Chalamarla, Tirumalesh wrote:
On Jun 1, 2015, at 3:22 AM, Mark Rutland mark.rutl...@arm.com wrote:
It's possible to specify that the paths exist. I expect that software
would select which to use at runtime.
My worry is how to define any
Adds support for CEVA SATA Host controller found on Xilinx Zynq
Ultrascale+ MPSoC.
Changes v2
- change module license to GPL v2
Suneel Garapati (2):
devicetree:bindings: add devicetree bindings for ceva ahci
drivers: ata: add support for Ceva sata host controller
Hi Chris,
On Fri, 5 Jun 2015 06:03:30 +, Chris Packham wrote:
I'm working on a new board and one feature it as is a plug-in module
with an ADS7830 voltage monitor on it. This will be used during
manufacturing to sanity check that various voltage rails are within
expected ranges.
I
On Fri, Jun 05, 2015 at 10:37:07AM +0300, Ivan T. Ivanov wrote:
On Fri, 2015-06-05 at 15:03 +0800, Peter Chen wrote:
On Tue, Jun 02, 2015 at 04:14:33PM +0300, Ivan T. Ivanov wrote:
On recent Qualcomm platforms VBUS and ID lines are not routed to
USB PHY LINK controller. Use extcon
On Thu, 04 Jun 2015, Javier Martinez Canillas wrote:
From: Gwendal Grignou gwen...@chromium.org
Chromebooks can have more than one Embedded Controller so the
cros_ec device id has to be incremented for each EC registered.
Add a new structure to represent multiple EC as different char
On Fri, 2015-06-05 at 10:39 +0200, Matthias Brugger wrote:
Hi YH,
2015-06-05 8:15 GMT+02:00 YH Huang yh.hu...@mediatek.com:
On Mon, 2015-05-25 at 10:14 +0800, Yingjoe Chen wrote:
On Thu, 2015-05-21 at 21:29 +0800, YH Huang wrote:
This patch series add the use of display PWM driver and
On Thu, 04 Jun 2015, Javier Martinez Canillas wrote:
From: Gwendal Grignou gwen...@chromium.org
Chromebooks can have more than one Embedded Controller so the
cros_ec device id has to be incremented for each EC registered.
Add a new structure to represent multiple EC as different char
I'm also very concerned that the interface exposed to userspace is
hideously low-level. Surely we'd expect kernel-side drivers to be doing
the bulk of direct communication to the OP-TEE instance? In the lack of
a provided rationale I don't see why the current messaging interface
Hello Lee,
On 06/05/2015 12:38 PM, Lee Jones wrote:
[...]
-err = mfd_add_devices(dev, 0, cros_devs,
- ARRAY_SIZE(cros_devs),
+err = mfd_add_devices(ec_dev-dev, PLATFORM_DEVID_AUTO, ec_cell, 1,
NULL, ec_dev-irq, NULL);
if
Hi Thierry
Am Freitag, 5. Juni 2015, 13:02:01 schrieb Thierry Reding:
On Mon, Mar 23, 2015 at 07:17:49PM +0100, Heiko Stuebner wrote:
Hi Philipp,
Am Donnerstag, 12. März 2015, 21:45:19 schrieb Heiko Stuebner:
At least the Rockchip variant of the dw_hdmi can have controllable power
On Mon, Mar 23, 2015 at 07:17:49PM +0100, Heiko Stuebner wrote:
Hi Philipp,
Am Donnerstag, 12. März 2015, 21:45:19 schrieb Heiko Stuebner:
At least the Rockchip variant of the dw_hdmi can have controllable power
supplies providing 1.0 and 1.8V. Therefore add the possibility for the
On Thu, Jun 04, 2015 at 09:28:44AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This series of patches adds support for the Arria10 EDAC. The
SDRAM controller and ECC registers are significantly different
from the CycloneV/ArriaV but common
Some device tree platforms have not defined correctly their memory
resources (i.e. Overlapping or duplication of resources).
To avoid this issue we have historically avoided to add their resources to
the resource tree. This leads to code duplication and oops when trying to
unload dynamically a
Some device tree platform do not define their resources properly. i.e.
overlapping or repeated resources.
This patch mark all device tree resources as shareable.
In the future this should only be set for the platforms that have
problems.
Signed-off-by: Ricardo Ribalda Delgado
On Thu, Jun 4, 2015 at 5:35 PM, Dinh Nguyen
dingu...@opensource.altera.com wrote:
Hi Alan,
On 06/02/2015 02:22 PM, Dinh Nguyen wrote:
On 06/02/2015 01:35 PM, Alan Tull wrote:
Support suspend to ram on socfpga.
* allocate space in ocram using sram driver.
* Add a function in ocram to
Hello,
Thanks for the patch, it's good to see another user of the generic
IO page-table code. However, I have quite a lot of comments on the code.
On Fri, May 15, 2015 at 10:43:26AM +0100, Yong Wu wrote:
This patch is for ARM Short Descriptor Format.It has 2-levels
pagetable and the allocator
On Thursday 04 June 2015 14:25:12 Y Vo wrote:
GIC is designed to support two of trigger mechanisms - active level
high or edge rising. But in the gpio_keys driver, it tries to use both
edge rising and edge falling trigger. This patch fixes the gpio_keys
driver to request only the edge rising
On Fri, May 15, 2015 at 10:43:28AM +0100, Yong Wu wrote:
This patch adds support for mediatek m4u (MultiMedia Memory Management Unit).
After looking at the page table code, I thought I'd come and check your
TLB invalidate code here.
+static void mtk_iommu_tlb_flush_all(void *cookie)
+{
+
On Friday 05 June 2015 10:32 AM, Vineet Gupta wrote:
On Thursday 14 May 2015 06:34 PM, Vineet Gupta wrote:
On Thursday 14 May 2015 06:23 PM, Arnd Bergmann wrote:
On Thursday 14 May 2015 15:48:42 Alexey Brodkin wrote:
chosen {
- bootargs = console=tty0
On Thursday, June 04, 2015 at 05:40:58 PM, Michal Suchanek wrote:
On 4 June 2015 at 17:28, Marek Vasut ma...@denx.de wrote:
On Thursday, June 04, 2015 at 06:54:00 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:40
On Thursday 14 May 2015 06:19 PM, Alexey Brodkin wrote:
AXS101 is a new generation of devlopment boards from Synopsys that houses
ASIC with ARC700 and lots of DesignWare peripherals:
* DW APB UART
* DW Mobile Storage (MMC/SD)
* DW I2C
* DW GMAC
More info about DesignWare ARC
On 6/5/15 6:02 AM, Borislav Petkov wrote:
On Thu, Jun 04, 2015 at 09:28:44AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This series of patches adds support for the Arria10 EDAC. The
SDRAM controller and ECC registers are significantly
On 29 May 2015 at 08:16, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
PSCI v1.0 augmented the power_state parameter format specification
(extended stateid) and introduced a way to probe it through the
PSCI_FEATURES interface.
This patch implements code that detects the power_state
On Fri, 5 Jun 2015, Dinh Nguyen wrote:
On Thu, Jun 4, 2015 at 5:35 PM, Dinh Nguyen
dingu...@opensource.altera.com wrote:
Hi Alan,
On 06/02/2015 02:22 PM, Dinh Nguyen wrote:
On 06/02/2015 01:35 PM, Alan Tull wrote:
Support suspend to ram on socfpga.
* allocate space in ocram using
Hi Boris,
On 6/5/15 4:17 AM, Borislav Petkov wrote:
On Thu, Jun 04, 2015 at 05:27:28PM -0500, Dinh Nguyen wrote:
This is my mistake. I applied Alan Tull's patch for suspend-to-ram which
also touches drivers/edac/altera_edac.c.
Hi,
The ti-dma-crossbar driver in it's current form can work when it is used with
sDMA (omap-dma). On DRA7x class of devices we have both sDMA and eDMA available.
The DT bindings for sDMA has been done in a way that DMA users need to specify
the required DMA request number + 1 when they request
On 06/05/2015 06:34 PM, Peter Ujfalusi wrote:
Hi,
The ti-dma-crossbar driver in it's current form can work when it is used with
sDMA (omap-dma). On DRA7x class of devices we have both sDMA and eDMA
available.
The DT bindings for sDMA has been done in a way that DMA users need to specify
On Fri, Jun 05, 2015 at 10:17:58AM -0700, Joe Perches wrote:
On Fri, 2015-06-05 at 09:49 -0700, Dmitry Torokhov wrote:
Hi Irina,
On Thu, May 28, 2015 at 03:47:37PM +0300, Irina Tirdea wrote:
Fix alignment to match open parenthesis detected by
running checkpatch.pl --strict.
From: Roman Byshko rbys...@gmail.com
Enable the otg/drc usb controller on the cubietruck.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git
Enable the otg controller on Ippo Q8H tablets, for now it is enabled
in host-only mode, because true OTG support requires support for
detecting and enabling Vbus through the axp221 pmic.
For this to work the Vbus on the port must be enabled by u-boot,
or a powered hub must be used.
Enable the otg/drc usb controller on the Ippo Q8H-A33 tablet, for now it
is enabled in host-only mode, because true OTG support requires support
for detecting and enabling Vbus through the axp221 pmic.
For this to work the Vbus on the port must be enabled by u-boot,
or a powered hub must be used.
The A33 SoC uses the same musb controller as found on the A31 and later,
but allwinner has removed the configdata register, this commit adds special
handling for this.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
.../devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt | 3 ++-
On some boards we cannot detect the presence of an external Vusb, because
e.g. the 5V of the otg connector is directly connected to the 5V of the board,
and thus is always high.
This commit adds support for using such boards by only looking at the
id-detection pin.
Signed-off-by: Hans de Goede
Hi Maxime,
Here is a patch-set with all the otg / sun8i-usb-host related dts patches
I've accumulated.
These are intended for 4.3, and go hand in hand with the outstanding
musb-sunxi / phy-sun4i-usb patches, which I expect to be merged as is
for 4.3 .
Regards,
Hans
--
To unsubscribe from this
Add a node for the otg/drc usb controller to sun5i-a1*.dtsi.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun5i.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 54b0978..53d3ead
Add a node for the otg/drc usb controller to sun4i-a10.dtsi.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index
The A31 SoC uses the same musb controller as found in earlier SoCs, but it
is hooked up slightly different. Its SRAM is private and no longer controlled
through the SRAM controller, and its reset is controlled via a separate
reset controller. This commit adds support for this setup.
We can cleanly handle this inside the sunxi glue, instead of adding special
casing to the core, but setting ep0 addr to 0 on a reset interrupt.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/usb/musb/musb_core.h| 1 -
drivers/usb/musb/musb_gadget.c | 6 --
Hi Felipe and Kishon,
This musb-sunxi / phy-sun4i-usb series adds supports for the otg and
host usb-phys found on newer sunxi SoCs and for the musb ip found on
newer sunxi SoCs. This series sits on top of the 2 still outstanding
musb-sunxi / phy-sun4i-usb patches.
These patches (and the 2 still
Whoops, nearly forgot the DT folks.
Sorry chaps.
* Add support for continuous-voltage mode
* Put more meat on the bones with regards to voltage-table mode
* Sort out formatting for ease of consumption
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Before this commit the code for determining the disconnect threshold was
checking for allwinner,sun4i-a10-usb-phy or allwinner,sun6i-a31-usb-phy
assuming that those where the exception and then newer SoCs would use a
disconnect threshold of 2 like sun7i does. But it turns out that newer
SoCs use a
The usb-phys on the sun8i-a33 SoC are mostly the same as sun8i-a23 but for
some reason (hw bug?) the phyctl register was moved to a different address
and is not initialized to 0 on reset.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 1
The usb-phys on the sun8i-a23 SoC have the same setup wrt clocks as on the
sun6i-a31 SoC, but there are only 2 instead of 3 like on the sun5i-a13 SoC.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 2 ++
drivers/phy/phy-sun4i-usb.c
-Original Message-
From: Dmitry Torokhov [mailto:dmitry.torok...@gmail.com]
Sent: 05 June, 2015 20:12
To: Tirdea, Irina
Cc: 'Antonio Ospite'; Bastien Nocera; linux-in...@vger.kernel.org;
devicetree@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: Re: [PATCH 2/9] input:
Hi Steve,
On Thu, Jun 04, 2015 at 12:02:32PM +0100, S Twiss wrote:
From: Steve Twiss stwiss.opensou...@diasemi.com
Add OnKey driver support for DA9063
Signed-off-by: Steve Twiss stwiss.opensou...@diasemi.com
---
The changes made in PATCH V3 have been taken from the DA9062 OnKey review
Enable the otg/drc usb controller on the A20-OLinuxIno-Lime.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 32 ++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
Enable the otg/drc usb controller on the Cubieboard. Note that the
5V of the otg is directly connected to the general 5V, so we only use
the id pin.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 19 +++
1 file changed, 19
Note these are added to the sun8i-a23.dtsi file rather then to the shared
sun8i-a23-a33.dtsi file as both the phy and the otg controller on the a33
are slightly different.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a23.dtsi | 32
From: Roman Byshko rbys...@gmail.com
Add a node for the otg/drc usb controller to sun7i-a20.dtsi
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
The Mele A1000G-quad has an usb to sata bridge connected to its otg
controller, this commit enables support for this. Since the otg is
hardwired to the sata bridge it gets enabled in host only mode.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Enable the OTG controller on the UTOO P66 tablet.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
From: Chen-Yu Tsai w...@csie.org
The Sina33 SDK board exposes the EHCI/OHCI USB host pair.
VBUS for this port is always on and non-controllable.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 13
Enable the otg/drc usb controller on the A20-OLinuxIno-Micro.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 32 +
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
Enable the otg/drc usb controller on the Chuwi V7 CW0825 tablet.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 34 +
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
Note these are added to the sun8i-a33.dtsi file rather then to the shared
sun8i-a23-a33.dtsi file as both the phy and the otg controller on the a33
are slightly different.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a33.dtsi | 32
Add a node for the otg/drc usb controller to sun6i-a31.dtsi.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index
Enable the otg/drc usb controller on the Bananapi.
This is based on the fex file settings which claim that vbus-det is
PH5, but this does not work and the schematic shows that it is actually
connected to gpio1 of the axp209, so we cannot add otg support for the
bananapi until we get support for
Enable the otg controller on GA10H-A33 tablets, for now it is enabled
in host-only mode, because true OTG support requires support for
detecting and enabling Vbus through the axp221 pmic.
For this to work the Vbus on the port must be enabled by u-boot,
or a powered hub must be used.
The GA10H tablets not only have an otg connector, but also a normal
usb host connector, enabled support for this.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts | 8
1 file changed, 8 insertions(+)
diff --git
Hi,
On 05-06-15 21:02, Hans de Goede wrote:
Enable the otg/drc usb controller on the Bananapi.
This is based on the fex file settings which claim that vbus-det is
PH5, but this does not work and the schematic shows that it is actually
connected to gpio1 of the axp209, so we cannot add otg
On Fri, Jun 05, 2015 at 04:36:24PM +, Tirdea, Irina wrote:
-Original Message-
From: Bastien Nocera [mailto:had...@hadess.net]
Sent: 04 June, 2015 15:51
To: Tirdea, Irina
Cc: Dmitry Torokhov; linux-in...@vger.kernel.org;
devicetree@vger.kernel.org;
-Original Message-
From: Bastien Nocera [mailto:had...@hadess.net]
Sent: 04 June, 2015 16:01
To: Tirdea, Irina
Cc: Dmitry Torokhov; linux-in...@vger.kernel.org; devicetree@vger.kernel.org;
linux-ker...@vger.kernel.org; Purdila, Octavian
Subject: Re: [PATCH 7/9] input: goodix: add
2015-06-05 5:53 GMT+09:00 yga...@codeaurora.org:
Hi Yaniv,
2015-06-03 18:37 GMT+09:00 Yaniv Gardi yga...@codeaurora.org:
@@ -321,7 +313,22 @@ static int ufshcd_pltfrm_probe(struct
platform_device *pdev)
goto out;
}
- hba-vops = get_variant_ops(pdev-dev);
+
-Original Message-
From: Dmitry Torokhov [mailto:dmitry.torok...@gmail.com]
Sent: 05 June, 2015 19:41
To: Tirdea, Irina
Cc: 'Antonio Ospite'; Bastien Nocera; linux-in...@vger.kernel.org;
devicetree@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: Re: [PATCH 2/9] input:
From: Misael Lopez Cruz misael.lo...@ti.com
eDMA crossbar works exactly the same way as sDMA, but sDMA
requires an offset of 1, while no offset is needed for eDMA.
Signed-off-by: Misael Lopez Cruz misael.lo...@ti.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
On Fri, 2015-06-05 at 06:37PM +0530, Ranjit Waghmode wrote:
Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
No changes in v2
---
.../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26
-Original Message-
From: linux-input-ow...@vger.kernel.org
[mailto:linux-input-ow...@vger.kernel.org] On Behalf Of Antonio Ospite
Sent: 03 June, 2015 23:50
To: Tirdea, Irina
Cc: Dmitry Torokhov; Bastien Nocera; linux-in...@vger.kernel.org;
devicetree@vger.kernel.org;
On Fri, Jun 05, 2015 at 04:36:24PM +, Tirdea, Irina wrote:
-Original Message-
From: Bastien Nocera [mailto:had...@hadess.net]
Sent: 04 June, 2015 15:55
To: Tirdea, Irina
Cc: Mark Rutland; Dmitry Torokhov; linux-in...@vger.kernel.org;
devicetree@vger.kernel.org;
On 06/01/2015 12:31 AM, Barry Song wrote:
2015-05-29 23:50 GMT+08:00 Bjorn Andersson bj...@kryo.se:
On Thu, May 28, 2015 at 2:30 PM, Suman Anna s-a...@ti.com wrote:
[..]
reg = 0x1324 0x0001;
An unrelated question here, why the reg is same for all the
On Fri, 2015-06-05 at 09:49 -0700, Dmitry Torokhov wrote:
Hi Irina,
On Thu, May 28, 2015 at 03:47:37PM +0300, Irina Tirdea wrote:
Fix alignment to match open parenthesis detected by
running checkpatch.pl --strict.
Mixed bag of changes here, but that's checkpatch for you.
Yup,
-Original Message-
From: Dmitry Torokhov [mailto:dmitry.torok...@gmail.com]
Sent: 05 June, 2015 19:42
To: Tirdea, Irina
Cc: 'Bastien Nocera'; linux-in...@vger.kernel.org;
devicetree@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: Re: [PATCH 4/9] input: goodix: add ACPI IDs
-Original Message-
From: Dmitry Torokhov [mailto:dmitry.torok...@gmail.com]
Sent: 05 June, 2015 19:49
To: Tirdea, Irina
Cc: Bastien Nocera; linux-in...@vger.kernel.org; devicetree@vger.kernel.org;
linux-ker...@vger.kernel.org
Subject: Re: [PATCH 1/9] input: goodix: fix alignment
Hi Irina,
On Thu, May 28, 2015 at 03:47:37PM +0300, Irina Tirdea wrote:
Fix alignment to match open parenthesis detected by
running checkpatch.pl --strict.
Mixed bag of changes here, but that's checkpatch for you.
Signed-off-by: Irina Tirdea irina.tir...@intel.com
---
On Fri, Jun 05, 2015 at 05:00:05PM +, Tirdea, Irina wrote:
-Original Message-
From: Dmitry Torokhov [mailto:dmitry.torok...@gmail.com]
Sent: 05 June, 2015 19:41
To: Tirdea, Irina
Cc: 'Antonio Ospite'; Bastien Nocera; linux-in...@vger.kernel.org;
-Original Message-
From: Bastien Nocera [mailto:had...@hadess.net]
Sent: 04 June, 2015 15:51
To: Tirdea, Irina
Cc: Dmitry Torokhov; linux-in...@vger.kernel.org; devicetree@vger.kernel.org;
linux-ker...@vger.kernel.org
Subject: Re: [PATCH 4/9] input: goodix: add ACPI IDs for GT911
On Fri, Jun 05, 2015 at 04:34:38PM +, Tirdea, Irina wrote:
-Original Message-
From: linux-input-ow...@vger.kernel.org
[mailto:linux-input-ow...@vger.kernel.org] On Behalf Of Antonio Ospite
Sent: 03 June, 2015 23:50
To: Tirdea, Irina
Cc: Dmitry Torokhov; Bastien Nocera;
On Fri, Jun 5, 2015 at 5:51 AM, Ricardo Ribalda Delgado
ricardo.riba...@gmail.com wrote:
Some device tree platform do not define their resources properly. i.e.
overlapping or repeated resources.
This patch mark all device tree resources as shareable.
In the future this should only be set for
-Original Message-
From: Bastien Nocera [mailto:had...@hadess.net]
Sent: 04 June, 2015 15:58
To: Tirdea, Irina
Cc: Mark Rutland; Dmitry Torokhov; linux-in...@vger.kernel.org;
devicetree@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: Re: [PATCH 8/9] input: goodix: add
From: Misael Lopez Cruz misael.lo...@ti.com
In preparation for supporting multiple DMA crossbar instances,
make the idr xbar instance specific.
Signed-off-by: Misael Lopez Cruz misael.lo...@ti.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
drivers/dma/ti-dma-crossbar.c | 9
Currently the driver can be used with sDMA only due to the fact that the
sDMA bindings are using real DMA_REQ + 1 indexing of the DMA requests.
This is not a case with the eDMA for example so the driver in current form
can not handle the case when it is used with eDMA.
Be precise with the
Hello Rob,
Thanks for your feedback!
On Fri, Jun 5, 2015 at 6:45 PM, Rob Herring robherri...@gmail.com wrote:
On Fri, Jun 5, 2015 at 5:51 AM, Ricardo Ribalda Delgado
ricardo.riba...@gmail.com wrote:
Some device tree platform do not define their resources properly. i.e.
overlapping or
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