On Fri, Jul 17, 2015 at 11:10:09AM +0200, Thierry Reding wrote:
On Thu, Jul 16, 2015 at 10:29:35PM +1000, David Gibson wrote:
On Thu, Jul 16, 2015 at 01:13:53PM +0200, Thierry Reding wrote:
On Wed, Jul 15, 2015 at 11:41:30PM +1000, David Gibson wrote:
On Wed, Jul 15, 2015 at 01:13:57PM
Hello
This is the driver for the Security System included in Allwinner SoC A20.
The Security System (SS for short) is a hardware cryptographic accelerator that
support AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on others Allwinner SoC:
- A10, A10s, A13, A31 and A33 manual give the
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2d3d55c..308da53 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -556,6 +556,12 @@ S: Maintained
F:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support:
- MD5 and SHA1 hash algorithms
- AES block cipher in CBC/ECB mode with 128/196/256bits keys.
- DES and 3DES block cipher in CBC/ECB mode
Signed-off-by:
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on many Allwinner SoC.
This patch enable the Security System on the Allwinner A20 SoC Device-tree.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
This patch adds documentation for Device-Tree bindings for the
Security System cryptographic accelerator driver.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
Documentation/devicetree/bindings/crypto/sun4i-ss.txt | 19 +++
1 file changed, 19 insertions(+)
create
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on many Allwinner SoC.
This patch enable the Security System on the Allwinner A10 SoC Device-tree.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
Hi Chanwoo,
Chanwoo Choi cw00.c...@samsung.com writes:
This patchset introduce the generic devfreq cooling device for generic thermal
framework. The devfreq devices are used ad cooling device to reduce the
overheating temperature. This patch is based on drivers/thermal/cpu_cooling.c.
The
On Fri, Jul 17, 2015 at 01:20:49PM +0300, Peter De Schrijver wrote:
On Fri, Jul 17, 2015 at 11:57:55AM +0200, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jul 13, 2015 at 01:39:40PM +0100, Jon Hunter wrote:
The Tegra memory controller implements a flush feature to flush
Dear ARM SoC Maintainers,
On 07/17/2015 01:45 PM, Benjamin Gaignard wrote:
STI drm drivers probe and bind using component framework was incorrect.
In addition to drivers fix DT update is needed to make all sub-components
become childs of sti-display-subsystem.
Signed-off-by: Benjamin Gaignard
ST's platforms currently support a maximum of 5 Mailboxes, one for
each of the supported co-processors situated on the platform. Each
Mailbox is divided up into 4 instances which consist of 32 channels.
Messages are passed between the application and co-processors using
shared memory areas. It
Am Montag, den 13.07.2015, 13:39 +0100 schrieb Jon Hunter:
From: Vince Hsu vin...@nvidia.com
Add of_reset_control_get_by_index() to allow the drivers to get reset
device without knowing its name.
Signed-off-by: Vince Hsu vin...@nvidia.com
[jonath...@nvidia.com: Updated stub function to
Hi Punit,
On 07/17/2015 07:53 PM, Punit Agrawal wrote:
Hi Chanwoo,
Chanwoo Choi cw00.c...@samsung.com writes:
This patchset introduce the generic devfreq cooling device for generic
thermal
framework. The devfreq devices are used ad cooling device to reduce the
overheating temperature.
Fix misunderstanding in how use component framework.
drm_platform_init() is now call only when all the
sub-components are register themselves instead of the
previous broken two stages mechanism.
Update bindings documentation.
Signed-off-by: Benjamin Gaignard benjamin.gaign...@linaro.org
---
STI drm drivers probe and bind using component framework was incorrect.
In addition to drivers fix DT update is needed to make all sub-components
become childs of sti-display-subsystem.
Signed-off-by: Benjamin Gaignard benjamin.gaign...@linaro.org
---
arch/arm/boot/dts/stih407.dtsi | 82
Hello.
On 7/16/2015 6:27 PM, Cyrille Pitchen wrote:
This patch documents the DT bindings for the driver of the Atmel QSPI
controller embedded inside sama5d2x SoCs.
Signed-off-by: Cyrille Pitchen cyrille.pitc...@atmel.com
---
.../devicetree/bindings/mtd/atmel-quadspi.txt | 29
This patch supplies the Mailbox Controller nodes. In order to
request channels, these nodes will be referenced by Mailbox
Client nodes.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
arch/arm/boot/dts/stih407-family.dtsi | 34 ++
1 file changed, 34
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
.../devicetree/bindings/mailbox/sti-mailbox.txt| 53 ++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
diff --git
ST's platforms currently support a maximum of 5 Mailboxes, one for
each of the supported co-processors situated on the platform. Each
Mailbox is divided up into 4 instances which consist of 32 channels.
Messages are passed between the application and co-processors using
shared memory areas.
Also
This patch supplies a Client node to enable the Mailbox testing
facility. It will be used to send and receive messages from any
given co-processor in order to test the STi Mailbox Controller
driver.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
arch/arm/boot/dts/stih407-family.dtsi | 6
This header is currently only used for defines pertaining to data
direction i.e. Rx, Tx or Loopback.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
include/dt-bindings/mailbox/mailbox.h | 14 ++
1 file changed, 14 insertions(+)
create mode 100644
This particular Client implementation uses shared memory in order
to pass messages between Mailbox users; however, it can be easily
hacked to support any type of Controller.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mailbox/Kconfig| 7 ++
drivers/mailbox/Makefile
On Wed, Jul 15, 2015 at 8:40 AM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
When the MPP is configured for analog output the output level is selected by
the AOUT_CTL register, this patch makes it possible to control this.
Signed-off-by: Bjorn Andersson
On Thu, Jun 18, 2015 at 8:47 AM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
The function of the MPP driver was inherited from the GPIO driver, but the
differences between the two hardware blocks makes both the driver and the
device tree binding to be awkward.
Instead of
On 07/16/2015 06:43 PM, santosh.shilim...@oracle.com wrote:
On 7/16/15 2:51 PM, Murali Karicheri wrote:
Currently PCIe DT bindings are broken. PCIe driver can't function
without having a SerDes driver that provide the phy configuration.
On K2E EVM, this causes problem since the EVM has Marvell
On 07/14/2015 12:10 PM, Philipp Zabel wrote:
Am Montag, den 13.07.2015, 13:07 +0200 schrieb Hans Verkuil:
On 07/10/2015 03:11 PM, Philipp Zabel wrote:
This is useful to subscribe to HDMI hotplug events via the
V4L2_CID_DV_RX_POWER_PRESENT control.
Signed-off-by: Philipp Zabel
The Maxim MAX77686 PMIC is a multi-function device with regulators,
clocks and a RTC. The DT bindings for the clocks are in a separate
file but the bindings for the regulators are inside the mfd part.
To make it consistent with the clocks portion of the binding and
because is more natural to look
The regulator-compatible property from the regulator DT binding was
deprecated. But the max77686 DT binding doc still suggest to use it
instead of the regulator node name's which is the correct approach.
Signed-off-by: Javier Martinez Canillas jav...@osg.samsung.com
Reviewed-by: Krzysztof
The MAX77802 is a chip that contains regulators, 2 32kHz clocks,
a RTC and an I2C interface to program the individual components.
The are already DT bindings for the regulators and clocks and
these reference to a bindings/mfd/max77802.txt file, that didn't
exist, for the details about the PMIC.
2015-07-17 15:46 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
Hello Krzysztof,
On 07/17/2015 08:42 AM, Krzysztof Kozlowski wrote:
2015-07-17 15:29 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
The Maxim MAX77686 PMIC is a multi-function device with regulators,
2015-07-17 15:59 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
Hello Krzysztof,
On 07/17/2015 08:49 AM, Krzysztof Kozlowski wrote:
2015-07-17 15:46 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
Hello Krzysztof,
On 07/17/2015 08:42 AM, Krzysztof Kozlowski wrote:
On Fri, Jul 17, 2015 at 09:54:48AM +0530, punnaiah choudary kalluri wrote:
your MUA is wrapping lines funny, please fix it
I have explored using the virt-dma to reduce the common list processing,
But
in this driver descriptor processing and cleaning is happening inside
the tasklet
On Fri, Jul 17, 2015 at 5:09 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Fri, Jul 17, 2015 at 04:57:11PM +0800, Chen-Yu Tsai wrote:
Hi Vishnu,
This patch did not make v4.2-rc1.
A33 support requires this patch. Otherwise the clock tree
is absent and nothing works.
It
On Fri, 2015-07-17 at 01:18 +0800, Daniel Kurtz wrote:
On Fri, Jul 17, 2015 at 12:44 AM, YH Huang yh.hu...@mediatek.com wrote:
On Thu, 2015-07-16 at 23:21 +0800, Daniel Kurtz wrote:
On Thu, Jul 16, 2015 at 3:17 PM, YH Huang yh.hu...@mediatek.com wrote:
On Thu, 2015-07-16 at 14:54 +0800,
2015-07-17 15:29 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
The MAX77802 is a chip that contains regulators, 2 32kHz clocks,
a RTC and an I2C interface to program the individual components.
The are already DT bindings for the regulators and clocks and
these reference to a
2015-07-17 15:29 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
The Maxim MAX77686 PMIC is a multi-function device with regulators,
clocks and a RTC. The DT bindings for the clocks are in a separate
file but the bindings for the regulators are inside the mfd part.
To make it
This patchset introduce the generic devfreq cooling device for generic
thermal
framework. The devfreq devices are used ad cooling device to reduce the
overheating temperature. This patch is based on drivers/thermal/cpu_cooling.c.
The devfreq cooling device can change the ragne of the
Hello Krzysztof,
On 07/17/2015 08:49 AM, Krzysztof Kozlowski wrote:
2015-07-17 15:46 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
Hello Krzysztof,
On 07/17/2015 08:42 AM, Krzysztof Kozlowski wrote:
2015-07-17 15:29 GMT+09:00 Javier Martinez Canillas
jav...@osg.samsung.com:
On Fri, Jul 17, 2015 at 2:35 PM, YH Huang yh.hu...@mediatek.com wrote:
On Fri, 2015-07-17 at 01:18 +0800, Daniel Kurtz wrote:
On Fri, Jul 17, 2015 at 12:44 AM, YH Huang yh.hu...@mediatek.com wrote:
On Thu, 2015-07-16 at 23:21 +0800, Daniel Kurtz wrote:
On Thu, Jul 16, 2015 at 3:17 PM, YH
Dear Myungjoo,
On 07/17/2015 03:40 PM, MyungJoo Ham wrote:
This patchset introduce the generic devfreq cooling device for generic
thermal
framework. The devfreq devices are used ad cooling device to reduce the
overheating temperature. This patch is based on
Hello Lee,
This series update the max77686 pmic drivers entry to also resolve the new
max77686 regulator DT binding doc and also adds an entry for the max77802.
The series depend on:
[PATCH v2 0/4] mfd: Improve DT binding docs for max77686 and max77802
https://lkml.org/lkml/2015/7/17/73
I added support for the max77802 drivers and have been maintaining them.
So add an entry for these drivers to make tools like get_maintainer.pl
to work and make people submitting patches add me to the CC list.
Signed-off-by: Javier Martinez Canillas jav...@osg.samsung.com
---
MAINTAINERS | 8
The Device Tree binding documentation for the Maxim max77686 regulators
has been moved from the Multi-Function Device DT binding section to its
own Documentation/devicetree/bindings/regulator/max77686.txt file.
Use a wilcard so both the mfd and regulator DT bindings are resolved.
Signed-off-by:
Hello Lee,
This series contains some improvements for the Device Tree bindings of
the Maxim MAX77686 and MAX77802 multi-function devices.
This is the second version of the series that addresses issues pointed
out by Krzysztof Kozlowski and Sergei Shtylyov.
Patch #1 changes the max77686 binding
The ePAR standard says that: the name of a node should be somewhat
generic, reflecting the function of the device and not its precise
programming model.
So, change the max77686 binding document example to use a generic
node name instead of using the chip's name.
Suggested-by: Sergei Shtylyov
On Mon, Jul 13, 2015 at 10:35:45AM -0700, Kyle Huey wrote:
This patch modifies the device tree for tegra124 based devices to enable
the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
DP-06905-001_v03p. This patch was tested on a Jetson TK1.
Updated for proper ordering and
On Fr, 2015-07-17 at 02:26 +, Gao Pandy wrote:
From: Jan Lübbe mailto:j...@pengutronix.de Sent: Thursday, July 16, 2015
8:58 PM
To: Gao Pan-B54642
Cc: Uwe Kleine-König; w...@the-dreams.de; linux-...@vger.kernel.org; Li
Frank-B20596; Duan Fugang-B38611
Subject: Re: [Patch v1] i2c:
Hello Krzysztof,
On 07/17/2015 08:42 AM, Krzysztof Kozlowski wrote:
2015-07-17 15:29 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
The Maxim MAX77686 PMIC is a multi-function device with regulators,
clocks and a RTC. The DT bindings for the clocks are in a separate
file but the
On 15/07/15 10:35, Mark Rutland wrote:
On Mon, Jul 13, 2015 at 06:35:45PM +0100, Kyle Huey wrote:
This patch modifies the device tree for tegra124 based devices to enable
the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA TRM
DP-06905-001_v03p. This patch was tested on a
Add basic DT binding for mmc35240
Add DT binding doc for mmc35240
Jandy Gou (2):
iio: magnetometer: mmc35240: Add DT binding
iio: magnetometer: mmc35240: Add DT binding doc
.../devicetree/bindings/iio/magnetometer/mmc35240.txt | 13 +
drivers/iio/magnetometer/mmc35240.c
Hi Vishnu,
This patch did not make v4.2-rc1.
A33 support requires this patch. Otherwise the clock tree
is absent and nothing works.
On Mon, May 11, 2015 at 4:53 PM, Vishnu Patekar
vishnupatekar0...@gmail.com wrote:
Hi,
On Sun, May 10, 2015 at 3:47 PM, Maxime Ripard
On do, 2015-07-16 at 17:27 +0200, Cyrille Pitchen wrote:
--- /dev/null
+++ b/drivers/mtd/spi-nor/atmel-quadspi.c
+static struct platform_driver atmel_qspi_driver = {
+ .driver = {
+ [...]
+ .bus= platform_bus_type,
+ [...]
+};
Hello.
On 7/17/2015 9:29 AM, Javier Martinez Canillas wrote:
The ePAR standard says that: the name of a node should be somewhat
ePAPR.
generic, reflecting the function of the device and not its precise
programming model.
So, change the max77686 binding document example to use a
On am437x-gp-evm, pixcir touchscreen can wake the system from low power
state by generating wake-up interrupt via pinctrl and IO daisy chain.
Add support for optional wakeup interrupt source by regsitering to
automated wake IRQ framework introduced by commit 4990d4fe327b (PM /
Wakeirq: Add
Pixcir_i2c_tsc driver can now wakeup the system from lower power state
via pinctrl and IO daisy chain using generic wakeirq framwework. Add
optional wakeup irq entry to allow pixcir_i2c_tsc to wake system from
low power state.
Signed-off-by: Vignesh R vigne...@ti.com
---
On am437x-gp-evm, pixcir_i2c_tsc can wake-up system from low power
state via pinctrl and IO daisy chain mechanism. This patch series add
support for such optional wake up interrupt to be handled via recently
introduced generic wake irq handling framework.
Tested on am437x-gp-evm, with some out
Hello Krzysztof,
On 07/17/2015 09:11 AM, Krzysztof Kozlowski wrote:
2015-07-17 15:59 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
Hello Krzysztof,
On 07/17/2015 08:49 AM, Krzysztof Kozlowski wrote:
2015-07-17 15:46 GMT+09:00 Javier Martinez Canillas
jav...@osg.samsung.com:
On Fri, 2015-07-17 at 14:59 +0800, Daniel Kurtz wrote:
On Fri, Jul 17, 2015 at 2:35 PM, YH Huang yh.hu...@mediatek.com wrote:
On Fri, 2015-07-17 at 01:18 +0800, Daniel Kurtz wrote:
On Fri, Jul 17, 2015 at 12:44 AM, YH Huang yh.hu...@mediatek.com wrote:
On Thu, 2015-07-16 at 23:21
Signed-off-by: Jandy Gou qingsong@ck-telecom.com
---
drivers/iio/magnetometer/mmc35240.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/iio/magnetometer/mmc35240.c
b/drivers/iio/magnetometer/mmc35240.c
index 7a2ea71..9bc542d 100644
---
Signed-off-by: Jandy Gou qingsong@ck-telecom.com
---
.../devicetree/bindings/iio/magnetometer/mmc35240.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iio/magnetometer/mmc35240.txt
diff --git
Hi,
On Fri, Jul 17, 2015 at 04:57:11PM +0800, Chen-Yu Tsai wrote:
Hi Vishnu,
This patch did not make v4.2-rc1.
A33 support requires this patch. Otherwise the clock tree
is absent and nothing works.
It got delayed and is in v4.2-rc2.
Maxime
--
Maxime Ripard, Free Electrons
Embedded
From: Alan Tull at...@opensource.altera.com
Add simple fpga bus. This is a bus that configures an fpga and its
bridges before populating the devices below it. This is intended
for use with device tree overlays.
Note that FPGA bridges are seen as reset controllers so no special
framework for
On Thu, Jul 16, 2015 at 6:55 PM, Tim Bird tim.b...@sonymobile.com wrote:
This binding is used to configure the driver for the coincell charger
found in Qualcomm PMICs.
Signed-off-by: Tim Bird tim.b...@sonymobile.com
Reviewed-by: Rob Herring r...@kernel.org
---
Changes in v3:
- change
From: Alan Tull at...@opensource.altera.com
Add a document spelling out usage of the simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
.../staging/fpga/Documentation/simple-fpga-bus.txt | 48
1 file changed, 48 insertions(+)
create mode 100644
From: Alan Tull at...@opensource.altera.com
New bindings document for simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
.../Documentation/bindings/simple-fpga-bus.txt | 61
1 file changed, 61 insertions(+)
create mode 100644
From: Alan Tull at...@opensource.altera.com
API to support programming FPGA.
The following functions are exported as GPL:
* fpga_mgr_buf_load
Load fpga from image in buffer
* fpga_mgr_firmware_load
Request firmware and load it to the FPGA.
* fpga_mgr_register
* fpga_mgr_unregister
From: Alan Tull at...@opensource.altera.com
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Michal Simek michal.si...@xilinx.com
---
v2: fpga_manager struct now contains struct device
On Mon, Jul 13, 2015 at 01:39:52PM +0100, Jon Hunter wrote:
Add power-domain binding documentation for the NVIDIA PMC driver in
order to support generic power-domains.
Signed-off-by: Jon Hunter jonath...@nvidia.com
---
.../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 99
2015-07-17 17:17 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
The Device Tree binding documentation for the Maxim max77686 regulators
has been moved from the Multi-Function Device DT binding section to its
own Documentation/devicetree/bindings/regulator/max77686.txt file.
Use a
On Mon, Jul 13, 2015 at 01:39:45PM +0100, Jon Hunter wrote:
Currently, the function tegra_powergate_set() simply sets the desired
powergate state but does not wait for the state to change. In some
circumstances this can be desirable. However, in most cases we should
wait for the state to
On Mon, Jul 13, 2015 at 01:39:46PM +0100, Jon Hunter wrote:
The following clean-ups have been made to the PMC code:
1. Add a macro for determining the state of a PMC powergate
2. Use the readx_poll_timeout() function instead of implementing a local
polling loop with a timeout.
3. Use a
-Original Message-
From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
Sent: Monday, July 13, 2015 3:18 PM
To: Wangzhou (B)
Cc: Gabriele Paoloni; James Morse; Bjorn Helgaas; Jingoo Han; Pratyush
Anand; Arnd Bergmann; fabrice.gasn...@st.com; Liviu Dudau; linux-
On Mon, Jul 13, 2015 at 01:39:49PM +0100, Jon Hunter wrote:
Add support to the tegra PCI driver for generic PM domains. However,
to ensure backward compatibility with older device tree blobs ensure
that the driver can work with or without generic PM domains. In order
to migrate to generic PM
From: Jianwei Wang jianwei.wang@gmail.com
Add DCU node, DCU is a display controller of Freescale
named 2D-ACE.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
Reviewed-by: Alison Wang
Hello Sergei,
On 07/17/2015 11:11 AM, Sergei Shtylyov wrote:
Hello.
On 7/17/2015 9:29 AM, Javier Martinez Canillas wrote:
The ePAR standard says that: the name of a node should be somewhat
ePAPR.
Thanks for pointing it out. I guess that Lee can fix the typo when applying?
On Mon, Jul 13, 2015 at 01:39:56PM +0100, Jon Hunter wrote:
From: Vince Hsu vin...@nvidia.com
Add power supply information which is board dependent for GK20A.
Signed-off-by: Vince Hsu vin...@nvidia.com
Signed-off-by: Jon Hunter jonath...@nvidia.com
---
On Mon, Jul 13, 2015 at 01:39:40PM +0100, Jon Hunter wrote:
The Tegra memory controller implements a flush feature to flush pending
accesses and prevent further accesses from occurring. This feature is
used when powering down IP blocks to ensure the IP block is in a good
state. The flushes are
The following patch is maybe a better solution
Gab
---
This patch is needed in order to unify the PCIe designware
framework for ARM and ARM64 architectures.
In the PCIe designware unification process we are calling
pci_create_root_bus() passing a sysdata parameter
that is the
On Mon, Jul 13, 2015 at 01:39:41PM +0100, Jon Hunter wrote:
From: Vince Hsu vin...@nvidia.com
This patch adds the hot reset register table and flush related callback
functions for Tegra30.
Signed-off-by: Vince Hsu vin...@nvidia.com
[jonath...@nvidia.com: Removed tegra_mc_ops and added
On Fri, Jul 17, 2015 at 11:57:55AM +0200, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jul 13, 2015 at 01:39:40PM +0100, Jon Hunter wrote:
The Tegra memory controller implements a flush feature to flush pending
accesses and prevent further accesses from occurring. This
Hi Ricardo,
On Jul 16, 2015, at 23:11 , Ricardo Ribalda Delgado
ricardo.riba...@gmail.com wrote:
Ping?
On vacations, but take a look at:
https://github.com/pantoniou/dtc
Regards
— Pantelis
On Fri, Jun 12, 2015 at 11:53 PM, Ricardo Ribalda Delgado
ricardo.riba...@gmail.com wrote:
On Thu, Jul 16, 2015 at 02:34:41PM +0100, Mark Rutland wrote:
Hi Will,
Hi Mark,
[adding David, since he's working on PCI/ITS stuff atm]
The below is an attempt at an MSI binding, derived from my original
example. It extends msi-parent inoto a phandle+(optional args) style
property.
I
On Fri, Jul 17, 2015 at 2:38 PM, Vinod Koul vinod.k...@intel.com wrote:
On Fri, Jul 17, 2015 at 09:54:48AM +0530, punnaiah choudary kalluri wrote:
your MUA is wrapping lines funny, please fix it
I have explored using the virt-dma to reduce the common list processing,
But
in this driver
On Mon, Jul 13, 2015 at 01:39:42PM +0100, Jon Hunter wrote:
From: Vince Hsu vin...@nvidia.com
This patch adds the hot reset register table and flush related callback
functions for Tegra114.
Signed-off-by: Vince Hsu vin...@nvidia.com
[jonath...@nvidia.com: Removed tegra_mc_ops and added
2015-07-17 17:17 GMT+09:00 Javier Martinez Canillas jav...@osg.samsung.com:
I added support for the max77802 drivers and have been maintaining them.
So add an entry for these drivers to make tools like get_maintainer.pl
to work and make people submitting patches add me to the CC list.
On Mon, Jul 13, 2015 at 01:39:43PM +0100, Jon Hunter wrote:
From: Vince Hsu vin...@nvidia.com
This patch adds the hot reset register table and flush related callback
functions for Tegra124.
Signed-off-by: Vince Hsu vin...@nvidia.com
[jonath...@nvidia.com: Removed tegra_mc_ops and added
From: Jianwei Wang jianwei.wang@gmail.com
This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM
simple panel driver.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
From: Jianwei Wang jianwei.wang@gmail.com
NEC represent NEC LCD Technologies, Ltd.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
---
From: Jianwei Wang jianwei.wang@gmail.com
Add a TFT LCD panel. the TFT LCD panel is WQVGA 480x272,
and the bpp is 24.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
Reviewed-by:
On Fri, Jul 17, 2015 at 11:34 AM, Jandy Gou qingsong@ck-telecom.com wrote:
Signed-off-by: Jandy Gou qingsong@ck-telecom.com
Acked-by: Daniel Baluta daniel.bal...@intel.com
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From: Jianwei Wang jianwei.wang@gmail.com
This patch add support for Two Dimensional Animation and Compositing
Engine (2D-ACE) on the Freescale SoCs.
2D-ACE is a Freescale display controller. 2D-ACE describes
the functionality of the module extremely well its name is a value
that cannot be
On Mon, Jul 13, 2015 at 01:39:48PM +0100, Jon Hunter wrote:
Add support to the tegra dc driver for generic PM domains. However,
to ensure backward compatibility with older device tree blobs ensure
that the driver can work with or without generic PM domains. In order
to migrate to generic PM
This patch fix typos found in Documentation/devicetree/bindings/clock.
Signed-off-by: Masanari Iida standby2...@gmail.com
---
Documentation/devicetree/bindings/clock/st/st,clkgen.txt | 4 ++--
Documentation/devicetree/bindings/clock/st/st,flexgen.txt | 2 +-
Am Dienstag, den 14.07.2015, 12:15 +0200 schrieb Hans Verkuil:
[...]
As you said, it's not public and without the formulas there is nothing you
can do but hardcode it.
If I understand this correctly these values depend on the link frequency,
so the DT should contain the link frequency and
On Mon, Jul 13, 2015 at 01:39:53PM +0100, Jon Hunter wrote:
Adds generic PM support to the PMC driver where the PM domains are
populated from device-tree and the PM domain consumer devices are
bound to their relevant PM domains via device-tree as well.
Update the
From: Mitchel Humpherys mitch...@codeaurora.org
On some platforms with tight power constraints it is polite to only
leave your clocks on for as long as you absolutely need them. Currently
we assume that all clocks necessary for SMMU register access are always
on.
Add some optional device tree
This series adds support for xlate callback to add master
devices configs using generic bindings and clocks/regulators
required to access smmu.
OF_IOMMU_DECLARE is used to register and probe the smmu controller
devices before the masters are added in of_platform_populate.
Here, we are registering
This adds of_xlate callback to arm-smmu driver. xlate callback
is called during device registration from DT for those master
devices attached to iommus using generic iommu bindings.
Signed-off-by: Sricharan R sricha...@codeaurora.org
---
drivers/iommu/arm-smmu.c | 36
On Fri, Jul 17, 2015 at 10:51:10AM -0500, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
This patchset adds two chunks plus documentation:
* fpga manager core: exports ABI functions that write an image to a FPGA
* DT Overlay support: simple-fpga-bus to
On 07/17/15 08:51, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
---
drivers/staging/Kconfig |2 +
drivers/staging/Makefile|1 +
drivers/staging/fpga/Kconfig| 14 ++
drivers/staging/fpga/Makefile |8 +
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