On Fri, Jul 24, 2015 at 03:16:23PM +0200, Stefan Agner wrote:
> This adds the NAND flash controller (NFC) peripherial. The driver
> supports the SLC NAND chips found on Freescale's Vybrid Tower System
> Module. The Micron NAND chip on the module needs 4-bit ECC per 512
> byte page. Use 24-bit ECC p
On Fri, Jul 24, 2015 at 06:34:12PM +0800, Jianwei Wang wrote:
> Add DCU node, DCU is a display controller of Freescale
> named 2D-ACE.
>
> Signed-off-by: Alison Wang
> Signed-off-by: Xiubo Li
> Signed-off-by: Jianwei Wang
For dts patches sent to me, please use prefix like "ARM: dts: ls1021a:
.
From: Dinh Nguyen
The dbg_base_clk can also have osc1 has a parent.
Signed-off-by: Dinh Nguyen
---
arch/arm/boot/dts/socfpga.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 86e0fb6..01bdaaa 100644
--
Signed-off-by: Zhou Wang
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8133cef..7cd8e47 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7854,6 +7854,13 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/xgene-pci-msi.tx
From: Gabriele Paoloni
This patch is needed in order to unify the PCIe designware framework for ARM and
ARM64 architectures. In the PCIe designware unification process we are calling
pci_create_root_bus() passing a "sysdata" parameter that is the same for both
ARM and ARM64 and is of type "struct
This patchset adds PCIe host support for HiSilicon SoC Hip05. The PCIe hosts
use PCIe IP core from Synopsys, So this driver is base on designware PCIe
driver.
Hip05 is an ARMv8 architecture SoC. It should be able to use ARM64 PCIe API in
designeware PCIe driver. So this patch also adds ARM64 supp
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init. Also set pp->root_bus_nr = 0 in
each PCIe host driver which is based on pcie-designware. This patch
This patch adds related DTS binding document for HiSilicon PCIe host driver.
Signed-off-by: Zhou Wang
---
.../devicetree/bindings/pci/hisilicon-pcie.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
This patch adds PCIe host support for HiSilicon SoC Hip05.
Signed-off-by: Zhou Wang
---
drivers/pci/host/Kconfig | 8 ++
drivers/pci/host/Makefile| 1 +
drivers/pci/host/pcie-hisi.c | 254 +++
3 files changed, 263 insertions(+)
create mode 100
Krzysztof Kozlowski wrote:
>
> On 24.07.2015 12:40, Kukjin Kim wrote:
> > On 07/24/15 09:30, Michael Turquette wrote:
> >> Quoting Kukjin Kim (2015-07-07 07:43:31)
> >>> Bartlomiej Zolnierkiewicz wrote:
> >
> > [...]
> >
> > Chanwoo Choi (3):
> > clk: samsung: exynos3250: Add cpu clock c
On 24-07-15, 15:16, Punit Agrawal wrote:
> Hi Viresh,
>
> Viresh Kumar writes:
>
> > On 22-07-15, 15:02, Punit Agrawal wrote:
> >> cpufreq-dt: Supply power coefficient when registering cooling devices
> >> cpufreq: arm_big_little: Add support to register a cpufreq cooling
> >> device
> >
On 2015/7/25 3:00, Rob Herring wrote:
> On Tue, Jul 21, 2015 at 3:01 AM, Wang Long wrote:
>> Update the last pr_warning callsite in drivers/of.
>
> That is obvious in the diff, but can you tell me why?
Hi Rob,
When we use script "./scripts/checkpatch.pl" to check a patch, using pr_warning
will
In order to use the mctrl_gpio helpers, we change the DT bindings:
ri-gpios renamed to rng-gpios. cd-gpios renamed to dcd-gpios.
However, no in-tree dts/dtsi specifies these, so no worries.
Signed-off-by: Niklas Cassel
---
.../bindings/serial/axis,etraxfs-uart.txt | 6 +++-
drivers/tty
Hi all,
I went ahead and generalized it to support all the resets I could
find in the TRM. I don't know if all of them are sensible, so we
need to carfully double check that. I also tried to add in the stuff
that was pointed out in v1.
If this looks good enough for a patch let me know.
Thanks f
Signed-off-by: Moritz Fischer
---
Documentation/devicetree/bindings/reset/zynq-reset-pl.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
diff --git a/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
b
Signed-off-by: Moritz Fischer
---
arch/arm/boot/dts/zynq-7000.dtsi| 43 -
arch/arm/boot/dts/zynq-parallella.dts | 2 +-
arch/arm/boot/dts/zynq-zc702.dts| 2 +-
arch/arm/boot/dts/zynq-zc706.dts| 2 +-
arch/arm/boot/dts/zynq-zed.dts
This adds a reset controller driver to control the Xilinx Zynq
SoC's various resets.
Signed-off-by: Moritz Fischer
---
drivers/reset/Makefile | 1 +
drivers/reset/reset-zynq.c | 142 +
2 files changed, 143 insertions(+)
create mode 100644 driver
looks good. possible to describe the chip we have.
> On Jul 23, 2015, at 9:52 AM, Mark Rutland wrote:
>
> Currently msi-parent is used by a few bindings to describe the
> relationship between a PCI root complex and a single MSI controller, but
> this property does not have a generic binding docum
Hi,
On Tue, Jul 07, 2015 at 05:34:21PM +0100, Adam Thomson wrote:
> diff --git a/Documentation/devicetree/bindings/power/da9150-fg.txt
> b/Documentation/devicetree/bindings/power/da9150-fg.txt
> new file mode 100644
> index 000..c3c76eb
> --- /dev/null
> +++ b/Documentation/devicetree/binding
On Thu, Jul 16, 2015 at 6:09 AM, Joerg Roedel wrote:
> Hi Will,
>
> On Thu, Jul 16, 2015 at 11:23:26AM +0100, Will Deacon wrote:
>> On Thu, Jul 16, 2015 at 09:30:43AM +0100, Joerg Roedel wrote:
>> > +struct of_phandle_args *of_alloc_phandle_args(int size)
>> > +{
>> > + struct of_phandle_args *a
On Fri, Jul 24, 2015 at 03:59:39PM -0500, Rob Herring wrote:
> On Fri, Jul 24, 2015 at 2:26 PM, Dmitry Torokhov
> wrote:
> > On Fri, Jul 24, 2015 at 02:14:57PM -0500, Rob Herring wrote:
> >> On Fri, Jul 24, 2015 at 1:26 PM, Dmitry Torokhov
> >> wrote:
> >> > Sometimes drivers might wish to transi
On Thu, Jul 16, 2015 at 04:55:31PM -0700, Tim Bird wrote:
> This binding is used to configure the driver for the coincell charger
> found in Qualcomm PMICs.
>
> Signed-off-by: Tim Bird
> ---
Looks reasonable.
Reviewed-by: Andy Gross
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation
On Thu, Jul 16, 2015 at 04:55:32PM -0700, Tim Bird wrote:
> This driver is used to configure the coincell charger found in
> Qualcomm PMICs.
>
> The driver allows configuring the current-limiting resistor for
> the charger, as well as the voltage to apply to the coincell
> (or capacitor) when char
On Thu, Jul 16, 2015 at 04:55:33PM -0700, Tim Bird wrote:
> Add framework for the coincell charger DT block in pm8941 file, and
> actual values for honami battery in the honami dts file.
>
> Signed-off-by: Tim Bird
> ---
Reviewed-by: Andy Gross
--
Qualcomm Innovation Center, Inc.
The Qualcom
On Fri, Jul 24, 2015 at 2:26 PM, Dmitry Torokhov
wrote:
> On Fri, Jul 24, 2015 at 02:14:57PM -0500, Rob Herring wrote:
>> On Fri, Jul 24, 2015 at 1:26 PM, Dmitry Torokhov
>> wrote:
>> > Sometimes drivers might wish to transition from index-based to named
>> > interrupt descriptions. To aid in dec
On Fri, Jul 24, 2015 at 12:26:19PM -0700, Dmitry Torokhov wrote:
> On Fri, Jul 24, 2015 at 02:14:57PM -0500, Rob Herring wrote:
> > On Fri, Jul 24, 2015 at 1:26 PM, Dmitry Torokhov
> > wrote:
> > > Sometimes drivers might wish to transition from index-based to named
> > > interrupt descriptions. T
On 07/21/2015 03:34 AM, Archit Taneja wrote:
> +
> +nand@0x1ac0 {
s/0x//
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord
On 24/07/15 11:26, Dmitry Torokhov wrote:
> Sometimes drivers might wish to transition from index-based to named
> interrupt descriptions. To aid in decision-making when parsing device
> tree data let's provide a helper that will indicate the scheme that is
> being used.
>
> Signed-off-by: Dmitry
On Wed, Jun 03, 2015 at 11:02:05AM +0200, Richard Weinberger wrote:
> On Wed, Apr 1, 2015 at 11:30 AM, Zubair Lutfullah Kakakhel
> wrote:
> > NEMC is going via greg-kh. They went through greg's char-misc-testing and
> > just got applied here.
> >
> > https://git.kernel.org/cgit/linux/kernel/git/gr
On Fri, Jul 24, 2015 at 02:14:57PM -0500, Rob Herring wrote:
> On Fri, Jul 24, 2015 at 1:26 PM, Dmitry Torokhov
> wrote:
> > Sometimes drivers might wish to transition from index-based to named
> > interrupt descriptions. To aid in decision-making when parsing device
> > tree data let's provide a
On Fri, Jul 24, 2015 at 1:26 PM, Dmitry Torokhov
wrote:
> Sometimes drivers might wish to transition from index-based to named
> interrupt descriptions. To aid in decision-making when parsing device
> tree data let's provide a helper that will indicate the scheme that is
> being used.
Generally,
On Tue, Jul 21, 2015 at 04:04:45PM +0530, Archit Taneja wrote:
> The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
> compatible string.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archit Taneja
> ---
Reviewed-by: Andy Gross
--
Qualcomm Innovation Center, Inc.
On Tue, Jul 21, 2015 at 3:01 AM, Wang Long wrote:
> Update the last pr_warning callsite in drivers/of.
That is obvious in the diff, but can you tell me why?
Rob
> Signed-off-by: Wang Long
> ---
> drivers/of/fdt.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --gi
On Fri, Jul 24, 2015 at 12:11:20PM +0530, Sekhar Nori wrote:
> Hi Greg,
>
> On Tuesday 14 July 2015 06:19 PM, Tony Lindgren wrote:
> > * Peter Hurley [150714 05:24]:
> >> On 07/14/2015 04:02 AM, Sekhar Nori wrote:
> >>> This series works around "Advisory 21" as documented in
> >>> AM437x SoC erra
On Tue, Jul 21, 2015 at 04:04:46PM +0530, Archit Taneja wrote:
> Enable the NAND controller node on the AP148 platform. Provide pinmux
> information.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archit Taneja
> ---
Looks fine.
Reviewed-by: Andy Gross
--
Qualcomm Innovation Center, In
On Tue, Jul 21, 2015 at 04:04:46PM +0530, Archit Taneja wrote:
> Enable the NAND controller node on the AP148 platform. Provide pinmux
> information.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archit Taneja
> ---
One nit though. The subject mispells Enable.
--
Qualcomm Innovation Cen
On Tue, Jul 21, 2015 at 04:04:44PM +0530, Archit Taneja wrote:
> Add DT bindings document for the Qualcomm NAND controller driver.
>
> Cc: devicetree@vger.kernel.org
>
> Signed-off-by: Archit Taneja
> ---
Acked-by: Andy Gross
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center
On Wed, Jun 03, 2015 at 12:30:44AM -0700, vn...@altera.com wrote:
> From: VIET NGA DAO
>
> Altera Quad SPI Controller is a soft IP which enables access to
> Altera EPCS, EPCQ and Mircon flash chips. This patch adds driver
> for these devices.
>
> Signed-off-by: VIET NGA DAO
>
> ---
> v4:
> - A
Quoting Kukjin Kim (2015-07-23 21:08:27)
> On 07/24/15 12:40, Kukjin Kim wrote:
> > On 07/24/15 09:30, Michael Turquette wrote:
> >> Quoting Kukjin Kim (2015-07-07 07:43:31)
> >>> Bartlomiej Zolnierkiewicz wrote:
> >
> > [...]
> >
> > Chanwoo Choi (3):
> > clk: samsung: exynos3250: Add
Sometimes drivers might wish to transition from index-based to named
interrupt descriptions. To aid in decision-making when parsing device
tree data let's provide a helper that will indicate the scheme that is
being used.
Signed-off-by: Dmitry Torokhov
---
The intent is to it like this:
On Thu, Jul 23, 2015 at 05:10:42PM +0800, Leilk Liu wrote:
This basically seems fine but there's a couple of issues that should be
relatively easy to fix:
> + mdata->cur_transfer = xfer;
> + mtk_spi_prepare_transfer(master, xfer);
> + mtk_spi_setup_packet(master, xfer);
> +
> + cn
On Fri, Jul 24, 2015 at 11:39 AM, Rob Herring wrote:
> On Fri, Jul 24, 2015 at 8:10 AM, Rob Clark wrote:
>> On Thu, Jul 23, 2015 at 3:52 PM, Bjorn Andersson
>> wrote:
>>> Add the possibility of specifying the default brightness in DT.
>>>
>>> Signed-off-by: Bjorn Andersson
>>> ---
>>>
>>> This
On Thu, Jul 23, 2015 at 05:10:41PM +0800, Leilk Liu wrote:
> Change-Id: I6cadbf2e51d2cc4eacd518a24d5a9a1da93d4db5
> Signed-off-by: Leilk Liu
Please don't include noise like Change-Id in upstream commits and please
use subject lines reflecting the style for the subsystem.
signature.asc
Descripti
On Fri, Jul 24, 2015 at 3:06 PM, Lee Jones wrote:
> On Thu, 23 Jul 2015, Jassi Brar wrote:
>
>> >> > +static void sti_mbox_enable_channel(struct mbox_chan *chan)
>> >> > +{
>> >> > + struct sti_channel *chan_info = chan->con_priv;
>> >> > + struct sti_mbox_device *mdev = chan_info->mde
The patch
regulator: qcom-spmi: Add vendor specific configuration
has been applied to the regulator tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 h
On Fri, Jul 24, 2015 at 11:24:34AM +0100, Mark Brown wrote:
> On Fri, Jul 24, 2015 at 10:58:47AM +0100, Lee Jones wrote:
> > On Thu, 23 Jul 2015, Mark Brown wrote:
> > > I have no idea what's going on here, sorry. I've not been reading this
> > > thread.
> > All of the information you need is in
On Fri, Jul 24, 2015 at 06:43:13AM +0100, Yong Wu wrote:
> On Tue, 2015-07-21 at 15:59 +0100, Will Deacon wrote:
> > On Thu, Jul 16, 2015 at 10:04:34AM +0100, Yong Wu wrote:
> > > +static void mtk_iommu_tlb_flush_all(void *cookie)
> > > +{
> > > + struct mtk_iommu_domain *domain = cookie;
> >
On Fri, Jul 24, 2015 at 06:24:26AM +0100, Yong Wu wrote:
> On Tue, 2015-07-21 at 18:11 +0100, Will Deacon wrote:
> > On Thu, Jul 16, 2015 at 10:04:32AM +0100, Yong Wu wrote:
> > > +/* level 2 pagetable */
> > > +#define ARM_SHORT_PTE_TYPE_LARGE BIT(0)
> > > +#define ARM_SHORT_PTE_SMAL
On Mon, 2015-07-20 at 15:32 +0800, Zhao Qiang wrote:
> From: Zhao Qiang
>
> p1010rdb-pb use the irq[4:5] for inta and intb to pcie,
> it is active-high, so set it.
What about revisions of p1010rdb other than pb?
> Signed-off-by: Zhao Qiang
> Change-Id: I29db41b4a8b5a67c18151099884edda6de4d9d1a
Hi Tony,
On 07/23/2015 11:30 PM, Tony Lindgren wrote:
> * Suman Anna [150723 09:25]:
>> Hi Tony,
>>
>> On 07/23/2015 02:24 AM, Tony Lindgren wrote:
>>> * Suman Anna [150722 09:25]:
On 07/22/2015 12:26 AM, Tony Lindgren wrote:
>
> I don't like using syscon for tinkering directly with
On Fri, Jul 24, 2015 at 8:10 AM, Rob Clark wrote:
> On Thu, Jul 23, 2015 at 3:52 PM, Bjorn Andersson
> wrote:
>> Add the possibility of specifying the default brightness in DT.
>>
>> Signed-off-by: Bjorn Andersson
>> ---
>>
>> This depends on the patch moving pm8941-wled to backlight [1]. The dt
On Fri, Jul 24, 2015 at 06:30:12PM +0300, Andy Shevchenko wrote:
> On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen wrote:
> > With this series applied:
> > m25p80 spi32766.0: m25p40 (512 Kbytes)
> Mark, what do you think about this? For me it looks okay.
Please don't send content
On Wed, 2015-06-24 at 18:34 +0200, Michael van der Westhuizen wrote:
> The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to
> 32bit
> accesses") globally changed all register access in the dw_apb_ssi
> driver
> to 32 bit access, which breaks data register (FIFO) access on
> picoXcell
On Thu, Jul 23, 2015 at 2:52 PM, Bjorn Andersson
wrote:
> Add the possibility of specifying the default brightness in DT.
>
> Signed-off-by: Bjorn Andersson
> ---
>
> This depends on the patch moving pm8941-wled to backlight [1]. The dt property
> is used by several other backlight drivers, so I
On Fri, 17 Jul 2015, Eric Anholt wrote:
> Signed-off-by: Eric Anholt
> Acked-by: Lee Jones (previous version with pm-domains)
For this version:
Acked-by: Lee Jones
> Acked-by: Stephen Warren
> ---
>
> v2: Drop pm-domains stuff since I've dropped it from the firmware
> driver for now,
On Fri, 17 Jul 2015, Eric Anholt wrote:
> This driver will provide support for calls into the firmware that will
> be used by other drivers like cpufreq and vc4.
>
> Signed-off-by: Eric Anholt
> Acked-by: Stephen Warren
> ---
>
> v2: Improve commit message, point to mailbox.txt for how mboxes
Hi,
On Fri, Jun 26, 2015 at 12:59:17PM +0200, Hans de Goede wrote:
> This adds a driver for the usb power_supply bits of the axp20x PMICs.
>
> I initially started writing my own driver, before coming aware of
> Bruno Prémont's excellent earlier RFC with a driver for this.
>
> My driver was lacki
DT chaps,
Please can you take a look at this binding.
In particular the use of the 'ranges' property to store device 'mode'.
> This patch documents the DT bindings for the Atmel Flexcom which will be
> introduced by sama5d2x SoCs. These bindings will be used by the actual
> Flexcom driver to be
On Fri, 24 Jul 2015, Lee Jones wrote:
> On Fri, 24 Jul 2015, Nicolas Ferre wrote:
>
> > Le 23/07/2015 21:48, Boris Brezillon a écrit :
> > > On Thu, 23 Jul 2015 18:42:55 +0200
> > > Cyrille Pitchen wrote:
> > >
> > >> This patch documents the DT bindings for the Atmel Flexcom which will be
> >
Hi,
On Fri, Jun 26, 2015 at 12:59:14PM +0200, Hans de Goede wrote:
> Add binding documentation for the usb power supply part of the AXP20x pmic.
> [...]
> +Example:
> +
> [...]
> +
> + usb_power_supply: usb_power_supply {
use usb-pow
On Fri, 24 Jul 2015, Nicolas Ferre wrote:
> Le 23/07/2015 21:48, Boris Brezillon a écrit :
> > On Thu, 23 Jul 2015 18:42:55 +0200
> > Cyrille Pitchen wrote:
> >
> >> This patch documents the DT bindings for the Atmel Flexcom which will be
> >> introduced by sama5d2x SoCs. These bindings will be
Hi Viresh,
Viresh Kumar writes:
> On 22-07-15, 15:02, Punit Agrawal wrote:
>> cpufreq-dt: Supply power coefficient when registering cooling devices
>> cpufreq: arm_big_little: Add support to register a cpufreq cooling
>> device
>
> Acked-by: Viresh Kumar
Thanks for the acks.
Once the
Hi Guenter,
Guenter Roeck writes:
> On 07/22/2015 07:02 AM, Punit Agrawal wrote:
>> Add support to create thermal zones based on the temperature sensors
>> provided by the SCP. The thermal zones can be defined using the
>> thermal DT bindings and should refer to the SCP sensor id to select
>> th
Hi Guenter,
Guenter Roeck writes:
> On 07/22/2015 07:02 AM, Punit Agrawal wrote:
>> Create a driver to add support for SoC sensors exported by the System
>> Control Processor (SCP) via the System Control and Power Interface
>> (SCPI). The supported sensor types is one of voltage, temperature,
>>
Hi,
> This looks sane, and lets me describe the thing I have on my desk, so
> I'm happy. I have a couple of general thoughts below, but I don't intend
> that they should stand in the way of this proposal as-is.
Good to hear that this doesn't fall apart at the sight of a real system!
> On 23/07
This patch contains device tree node definition for JPEG codec peripheral
found in the Renesas R-Car r8a7790 SoC.
Signed-off-by: Mikhail Ulyanov
---
arch/arm/boot/dts/r8a7790.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a779
This patch contains device tree node definition for JPEG codec peripheral
found in the Renesas R-Car r8a7791 SoC.
Signed-off-by: Mikhail Ulyanov
---
arch/arm/boot/dts/r8a7791.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a779
This series of patches contains device tree nodes definitions for JPEG
codec peripheral found in the Renesas R-Car SoCs.
This series of patches is against the renesas-devel-20150720-v4.2-rc3
of https://kernel.googlesource.com/pub/scm/linux/kernel/git/horms/renesas
The driver itself was accepted b
This driver supports Freescale NFC (NAND flash controller) found on
Vybrid (VF610), MPC5125, MCF54418 and Kinetis K70. The driver has
been tested on 8-bit and 16-bit NAND interface and supports ONFI
parameter page reading.
Limitations:
- DMA and pipelining not used
- Pages larger than 2k are not s
Signed-off-by: Bill Pringlemeir
Signed-off-by: Stefan Agner
---
.../devicetree/bindings/mtd/vf610-nfc.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/vf610-nfc.txt
diff --git a/Documentation/devicetree/bindings
This adds the NAND flash controller (NFC) peripherial. The driver
supports the SLC NAND chips found on Freescale's Vybrid Tower System
Module. The Micron NAND chip on the module needs 4-bit ECC per 512
byte page. Use 24-bit ECC per 2k page, which is supported by the
driver.
Signed-off-by: Bill Pri
Enable NAND access by adding pinmux and NAND flash controller node
to device tree. The NAND chips currently used on the Colibri VF61
requires 8-bit ECC per 512 byte page, hence specify 32-bit ECC
strength per 2k page size.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/vf-colibri.dtsi | 32 ++
This adds hardware ECC support using the BCH encoder in the NFC IP.
The ECC encoder supports up to 32-bit correction by using 60 error
correction bytes. There is no sub-page ECC step, ECC is calculated
always accross the whole page (up to 2k pages). Raw writes writes
are possible through the common
This seventh revision simplifies the config symbols somewhat, but
is otherwise just a rebase version on current l2-mtd/master.
I reran the MTD tests, they still all succeed.
Some more information and the full test log can be found in the
cover letter of the last revision v6:
http://thread.gmane.o
On Thu, Jul 23, 2015 at 3:52 PM, Bjorn Andersson
wrote:
> Add the possibility of specifying the default brightness in DT.
>
> Signed-off-by: Bjorn Andersson
> ---
>
> This depends on the patch moving pm8941-wled to backlight [1]. The dt property
> is used by several other backlight drivers, so I
On Friday, July 24, 2015 05:00:13 PM Daniel Kurtz wrote:
> On Fri, Jul 24, 2015 at 4:40 PM, Matthias Brugger
>
> wrote:
> > On Monday, July 20, 2015 04:17:15 PM YH Huang wrote:
> >> Document the device-tree binding of MediatTek display PWM.
> >> The PWM has one channel to control the backlight br
On Fri 2015-07-24 07:39:15, atull wrote:
> On Fri, 24 Jul 2015, Pavel Machek wrote:
>
> Hi Pavel,
>
> Thanks for your your feedback in cleaning up these docs.
>
> > Hi!
> >
> > > +What:/sys/class/fpga_manager//state
> > > +Date:July 2015
> > > +KernelVersion: 4.2
> > >
On Fri, 24 Jul 2015, Pavel Machek wrote:
Hi Pavel,
Thanks for your your feedback in cleaning up these docs.
> Hi!
>
> > +What: /sys/class/fpga_manager//state
> > +Date: July 2015
> > +KernelVersion: 4.2
> > +Contact: Alan Tull
> > +Description: Read fpga m
Hi Stephen,
> -Original Message-
> From: linux-arm-kernel [mailto:linux-arm-kernel-
> boun...@lists.infradead.org] On Behalf Of Stephen Boyd
> Sent: Tuesday, July 21, 2015 11:48 PM
> To: Sricharan R
> Cc: devicetree@vger.kernel.org; linux-arm-...@vger.kernel.org;
> will.dea...@arm.com; io.
Hi Will,
> -Original Message-
> From: linux-arm-msm-ow...@vger.kernel.org [mailto:linux-arm-msm-
> ow...@vger.kernel.org] On Behalf Of Will Deacon
> Sent: Tuesday, July 21, 2015 8:31 PM
> To: Sricharan R
> Cc: linux-arm-ker...@lists.infradead.org;
io...@lists.linux-foundation.org;
> device
Hi Mark,
This looks sane, and lets me describe the thing I have on my desk, so
I'm happy. I have a couple of general thoughts below, but I don't intend
that they should stand in the way of this proposal as-is.
On 23/07/15 17:52, Mark Rutland wrote:
The existing IOMMU bindings are able to spe
* Sekhar Nori [150723 23:44]:
> Hi Greg,
>
> On Tuesday 14 July 2015 06:19 PM, Tony Lindgren wrote:
> > * Peter Hurley [150714 05:24]:
> >> On 07/14/2015 04:02 AM, Sekhar Nori wrote:
> >>> This series works around "Advisory 21" as documented in
> >>> AM437x SoC errata[1]. This errata prevents UA
* Sekhar Nori [150714 01:05]:
> Add "ti,dra742-uart" to the compatible list so the driver
> workaround for UART module disable errata is enabled.
>
> This does not break backward compatibility as existing DTBs
> should continue to work with newer kernels albeit without the
> capability to idle th
On Wednesday 22 July 2015 06:02 PM, Franklin S Cooper Jr wrote:
> SPI Davinci driver has been updated to allow SOCs to specify their minimum
> prescale value. Update the various SOCs board files that use this driver with
> their proper prescaler limit.
>
> Signed-off-by: Franklin S Cooper Jr
Ack
On Wednesday 22 July 2015 06:02 PM, Franklin S Cooper Jr wrote:
> Currently the pre-scaler limit is incorrect. The value differs slightly
> for various devices so a single value can't be used. Using the compatible
> field select the correct pre-scaler limit.
>
> Add new compatible field value for
On Fri, 2015-07-24 at 12:31 +0100, Mark Rutland wrote:
> On Wed, Jul 22, 2015 at 10:47:18AM +0100, Ian Campbell wrote:
> > On Wed, 2015-07-22 at 09:47 +0100, Liviu Dudau wrote:
> > >
> > > Acked-by: Liviu Dudau
> >
> > Thanks.
> >
> > > Picking your brains here: would it be worth to have some v
Hi James,
On Fri, Jul 24, 2015 at 11:01 AM, James Liao wrote:
> This patch adds fixed clocks support by using CCF fixed-rate
> clock implementation.
>
> Signed-off-by: James Liao
> ---
> drivers/clk/mediatek/clk-mtk.c | 23 +++
> drivers/clk/mediatek/clk-mtk.h | 19 +
On Wed, Jul 22, 2015 at 10:47:18AM +0100, Ian Campbell wrote:
> On Wed, 2015-07-22 at 09:47 +0100, Liviu Dudau wrote:
> >
> > Acked-by: Liviu Dudau
>
> Thanks.
>
> > Picking your brains here: would it be worth to have some vendor directories
> > in
> > this shared area or we can hope that ther
On Fri, Jul 24, 2015 at 11:02 AM, James Liao wrote:
> This patch adds device nodes providing subsystem clocks on MT8173,
> includes mmsys, imgsys, vdecsys, vencsys and vencltsys.
>
> Signed-off-by: James Liao
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 37
> ++
On Fri, Jul 24, 2015 at 11:02 AM, James Liao wrote:
> Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
> is needed by USB 3.0.
>
> Signed-off-by: James Liao
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-apmixed.c | 137
> +
On Fri, Jul 24, 2015 at 11:02 AM, James Liao wrote:
> Most multimedia subsystem clocks will be accessed by multiple
> drivers, so it's a better way to manage these clocks in CCF.
> This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
> subsystems.
>
> Signed-off-by: James Liao
> ---
On Fri, Jul 24, 2015 at 11:02 AM, James Liao wrote:
> Remove the dependency from clk_null, and give all root clocks a
> typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts.
>
> dpi_ck was removed due to no clock reference to it.
>
> Replace parent clock of infra_cpum with cpum_ck
> At the begin of my work on this patchset I even denied clock disable call if
> slave is registered (to minimize code that can affect transfer).
I hacked something like this, but it seems it was not enough.
> If only slave mode is used, then this logic is not needed.
This is not sufficent. We
This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM
simple panel driver.
Signed-off-by: Alison Wang
Signed-off-by: Xiubo Li
Signed-off-by: Jianwei Wang
Acked-by: Daniel Vetter
---
.../bindings/panel/nec,nl4827hc19_05b.txt | 7 ++
drivers/gpu/drm/panel/panel-sim
NEC represent NEC LCD Technologies, Ltd.
Signed-off-by: Alison Wang
Signed-off-by: Xiubo Li
Signed-off-by: Jianwei Wang
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documen
Add a TFT LCD panel. the TFT LCD panel is WQVGA "480x272",
and the bpp is 24.
Signed-off-by: Alison Wang
Signed-off-by: Xiubo Li
Signed-off-by: Jianwei Wang
---
arch/arm/boot/dts/ls1021a-twr.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts
Add Alison and myself as maintainers of the Freescale DCU DRM driver.
Signed-off-by: Alison Wang
Signed-off-by: Xiubo Li
Signed-off-by: Jianwei Wang
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6761318..387a84a 100644
--- a/MAINTA
Add DCU node, DCU is a display controller of Freescale
named 2D-ACE.
Signed-off-by: Alison Wang
Signed-off-by: Xiubo Li
Signed-off-by: Jianwei Wang
---
arch/arm/boot/dts/ls1021a.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/
Resend v12 for lack of patch 0/6
This patchset add support for Two Dimensional Animation and Compositing
Engine (2D-ACE) on the Freescale LS102x SoCs.
Changed in v12
-Add one patch for MAINTAINER entry for drm/layerscape
Adviced by Daniel Vetter
-Add #include
Changed in V11
-set regmap_config.
This patch add support for Two Dimensional Animation and Compositing
Engine (2D-ACE) on the Freescale SoCs.
2D-ACE is a Freescale display controller. 2D-ACE describes
the functionality of the module extremely well its name is a value
that cannot be used as a token in programming languages.
Instead
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