On Wed, Jul 29, 2015 at 6:20 AM, Tomeu Vizoso
tomeu.viz...@collabora.com wrote:
On 29 July 2015 at 08:14, Tomeu Vizoso tomeu.viz...@collabora.com wrote:
On 28 July 2015 at 17:31, Rob Herring robherri...@gmail.com wrote:
On Tue, Jul 28, 2015 at 8:54 AM, Tomeu Vizoso
tomeu.viz...@collabora.com
On Wed, Jul 29, 2015 at 7:49 PM, Michal Simek michal.si...@xilinx.com wrote:
Add i2c eeprom memories on i2c bus.
Thanks for the patch.
Feel free to add
Reviewed-by: Shubhrajyoti Datta shubh...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Change eeprom
Hi Uwe,
On 07/29/2015 12:35 AM, Uwe Kleine-König wrote:
Hello Guenter,
[ ... ]
always-running is meant to indicate that the watchdog can not be stopped
(meaning a timer has to be used to send keepalives while the watchdog
device is closed). The documentation specifically states that.
On 29/07/15 17:08, nick wrote:
On 2015-07-29 09:52 AM, Roger Quadros wrote:
On 29/07/15 15:13, nick wrote:
On 2015-07-29 08:06 AM, Roger Quadros wrote:
Tony,
On 13/07/15 15:40, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [150713 03:07]:
Tony,
On 13/07/15 10:10, Tony Lindgren
On Wed, Jul 29, 2015 at 8:22 AM, Ian Campbell ian.campb...@citrix.com wrote:
On Wed, 2015-07-29 at 20:07 +0900, Masahiro Yamada wrote:
Hi Ian,
2015-07-27 19:35 GMT+09:00 Ian Campbell ian.campb...@citrix.com:
Commit 9ccd608070b6 arm64: dts: add device tree for ARM SMM-A53x2 on
LogicTile
try to blindly find the cause for this issue.
# uname -a
Linux buildroot 4.2.0-rc4-next-20150729+ #97 Wed Jul 29 17:50:11 EEST
2015 avr32 GNU/Linux
Do you, guys, have that board (NGW100) or it's officially unsupported?
Sorry but we don't have AVR32-based board in our office. Hans-Christian
On 29 July 2015 at 16:00, Mark Brown broo...@kernel.org wrote:
On Wed, Jul 29, 2015 at 12:19:57PM +0200, Michal Suchanek wrote:
Please use subject lines matching the style for the subsytsem so people
can spot that the patch is in some way relevant.
The controller-data subnode has no
On Wed, Jul 29, 2015 at 06:19:24PM +0200, Michal Suchanek wrote:
On 29 July 2015 at 16:00, Mark Brown broo...@kernel.org wrote:
On Wed, Jul 29, 2015 at 12:19:57PM +0200, Michal Suchanek wrote:
Please use subject lines matching the style for the subsytsem so people
can spot that the patch
Hi Martin,
Am 28.07.2015 um 12:48 schrieb Martin Sperl:
On 28.07.2015 08:18, Martin Sperl wrote:
Hi Stephen!
But the bigger question you have not answered is: “where should such an
auxiliar driver go in the kernel tree?” i.e. which directory?
One thing: could the module be a regulator?
Den 29.07.2015 18:37, skrev Stefan Wahren:
Hi Martin,
Am 28.07.2015 um 12:48 schrieb Martin Sperl:
On 28.07.2015 08:18, Martin Sperl wrote:
Hi Stephen!
But the bigger question you have not answered is: “where should such an
auxiliar driver go in the kernel tree?” i.e. which directory?
One
On 29/07/15 18:26, nick wrote:
On 2015-07-29 11:12 AM, Roger Quadros wrote:
On 29/07/15 17:08, nick wrote:
On 2015-07-29 09:52 AM, Roger Quadros wrote:
On 29/07/15 15:13, nick wrote:
On 2015-07-29 08:06 AM, Roger Quadros wrote:
Tony,
On 13/07/15 15:40, Tony Lindgren wrote:
* Roger
Hi Bjorn
Liviu and Rob already acked, do you think it is ok to merge this?
Cheers
Gab
-Original Message-
From: Gabriele Paoloni
Sent: Monday, July 27, 2015 4:17 PM
To: Gabriele Paoloni; a...@arndb.de; lorenzo.pieral...@arm.com;
Wangzhou (B); bhelg...@google.com;
On Tue, Jul 28, 2015 at 08:38:33PM +0100, Lina Iyer wrote:
Hello,
I am looking to find a way to uniquely identify a device in the driver.
Here is an example -
big: power-controller@1 {
compatible = soc,foo;
...
};
little:
On Wed, Jul 29, 2015 at 06:19:24PM +0200, Michal Suchanek wrote:
On 29 July 2015 at 16:00, Mark Brown broo...@kernel.org wrote:
I can't tell from this commit message what the issue you're trying to
fix is, sorry. Nodes without compatible strings are entirely normal and
don't need
On Wed, Jul 29 2015 at 03:44 -0600, Sudeep Holla wrote:
On 28/07/15 20:38, Lina Iyer wrote:
Hello,
I am looking to find a way to uniquely identify a device in the driver.
Here is an example -
big: power-controller@1 {
compatible = soc,foo;
...
On Sat, Jul 25, 2015 at 04:21:23AM +0100, Zhou Wang wrote:
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init. Also set pp-root_bus_nr = 0 in
each
Hi Gabriele,
As far as I can tell, this is not specific to PCIe, so please use PCI in
the subject as a generic term that includes both PCI and PCIe.
On Mon, Jul 27, 2015 at 11:17:03PM +0800, Gabriele Paoloni wrote:
From: gabriele paoloni gabriele.paol...@huawei.com
This patch is needed
On Wed, Jul 29, 2015 at 08:21:34PM +0200, Michal Suchanek wrote:
On 29 July 2015 at 19:16, Mark Brown broo...@kernel.org wrote:
It will not break anything. It will just spam dmesg.
I'm confused - if all this change does is to spam dmesg then what's the
point?
Presumably when your SPI
On Mon, Jul 27, 2015 at 08:20:29PM -0700, Bjorn Andersson wrote:
Add device tree binding documentation for the Qualcomm Shared Memory
Device, used for communication between the various CPUs in the Qualcomm
SoCs.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
Applied,
This patch adds support for United Radiant Technology
UMSH-8596MD-xT 7.0 WVGA TFT LCD panels
(both LVDS and parallel versions) to DRM
panel-simple driver.
Signed-off-by: Maciej Szmigiero m...@maciej.szmigiero.name
---
.../devicetree/bindings/panel/urt,umsh-8596md.txt | 11 +
On Wed, Jul 29, 2015 at 11:12:30AM -0700, Tim Bird wrote:
Greg,
At this point I've got Reviewed-by from Rob on the binding and dts bits,
and Reviewed-by from Andy Gross on the complete patch series (v3).
I believe I've addressed all issues raised. Can you please add this
(v3) to
On 29.07.2015, at 18:37, Stefan Wahren i...@lategoodbye.de wrote:
Hi Martin,
Am 28.07.2015 um 12:48 schrieb Martin Sperl:
On 28.07.2015 08:18, Martin Sperl wrote:
Hi Stephen!
But the bigger question you have not answered is: “where should such an
auxiliar driver go in the kernel
On Fri 24 Jul 10:41 PDT 2015, Rob Clark wrote:
On Fri, Jul 24, 2015 at 11:39 AM, Rob Herring robherri...@gmail.com wrote:
On Fri, Jul 24, 2015 at 8:10 AM, Rob Clark robdcl...@gmail.com wrote:
On Thu, Jul 23, 2015 at 3:52 PM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
Add the
On 07/29, Lee Jones wrote:
On Tue, 28 Jul 2015, Stephen Boyd wrote:
On 07/28, Viresh Kumar wrote:
Cc'ing few people (whom I cc'd last time as well :)).
On 27-07-15, 16:20, Lee Jones wrote:
+ - opp-hz : CPU frequency [Hz] for this OPP [See:
./opp.txt]
+ -
[+cc Andrew]
On Wed, Jul 29, 2015 at 07:44:18PM +, Gabriele Paoloni wrote:
-Original Message-
From: Bjorn Helgaas [mailto:bhelg...@google.com]
Sent: Wednesday, July 29, 2015 6:21 PM
To: Gabriele Paoloni
On Mon, Jul 27, 2015 at 11:17:03PM +0800, Gabriele Paoloni wrote:
On 07/28/2015 05:54 AM, Srinivas Kandagatla wrote:
+
+ panel_3p3v: panel_3p3v {
+ compatible = regulator-fixed;
+ pinctrl-0 = disp_en_gpios;
+ pinctrl-names = default;
+ regulator-min-microvolt
On Tue, 2015-07-28 at 11:14PM -0700, Moritz Fischer wrote:
Hi Sören,
On Tue, Jul 28, 2015 at 3:53 PM, Sören Brinkmann
soren.brinkm...@xilinx.com wrote:
On Mon, 2015-07-27 at 09:52PM -0700, Moritz Fischer wrote:
Hi Sören,
thanks for your feedback.
On Mon, Jul 27, 2015 at 7:58 PM,
On Wed, Jul 29, 2015 at 4:35 PM, Paul Bolle pebo...@tiscali.nl wrote:
On di, 2015-07-28 at 18:45 +0800, Ley Foon Tan wrote:
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
+config PCIE_ALTERA
+ bool Altera PCIe controller
+ depends on ARCH_SOCFPGA
+ depends on OF
On 29 July 2015 at 19:16, Mark Brown broo...@kernel.org wrote:
On Wed, Jul 29, 2015 at 06:19:24PM +0200, Michal Suchanek wrote:
On 29 July 2015 at 16:00, Mark Brown broo...@kernel.org wrote:
I can't tell from this commit message what the issue you're trying to
fix is, sorry. Nodes without
On Wed, Jul 29, 2015 at 9:19 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Tue, Jul 28, 2015 at 11:45:42AM +0100, Ley Foon Tan wrote:
[...]
+static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
+{
+ int err, res_valid = 0;
+ struct device
Greg,
At this point I've got Reviewed-by from Rob on the binding and dts bits,
and Reviewed-by from Andy Gross on the complete patch series (v3).
I believe I've addressed all issues raised. Can you please add this
(v3) to drivers/misc?
Let me know if you want me to re-send anything.
Thanks
On 07/29/2015 06:09 AM, Kishon Vijay Abraham I wrote:
For beagle x15, both the vdd and io lines are connected to the
same regulator (ldo1_reg). However vmmc_aux is populated to vdd_3v3.
Remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
On Mon, Jul 27, 2015 at 08:20:31PM -0700, Bjorn Andersson wrote:
Add binding documentation for the Qualcomm Resource Power Manager (RPM)
using shared memory (Qualcomm SMD) as transport mechanism. This is found
in 8974 and newer based devices.
The binding currently describes the rpm itself
Hi Bjorn
Many Thanks for your reply
I have commented back inline with resolutions from my side.
If you're ok with them I'll send it out a new version in the appropriate
patchset
Cheers
Gab
-Original Message-
From: Bjorn Helgaas [mailto:bhelg...@google.com]
Sent: Wednesday, July
On 07/28/2015 05:53 AM, Srinivas Kandagatla wrote:
+
+ sdcc4_pwrseq:pwrseq {
Missing space here between label and node name.
+ compatible = mmc-pwrseq-simple;
+ reset-gpios = pm8921_gpio 43 GPIO_ACTIVE_LOW;
+ };
+
Also
On Fri 24 Jul 08:29 PDT 2015, Rob Herring wrote:
On Thu, Jul 23, 2015 at 2:52 PM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
Add the possibility of specifying the default brightness in DT.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
This depends on
Hi Borislav,
+
+static void xgene_edac_l3_hw_init(struct edac_device_ctl_info *edac_dev,
+ bool enable)
arg alignment. It should be
function name(arg1, arg2,
arg3, arg4,
arg5...
Check your other functions too.
I will check and
Hi Lee,
+ linux-clk ml
Quoting Lee Jones (2015-07-22 06:04:13)
These new API calls will firstly provide a mechanisms to tag a clock as
critical and secondly allow any knowledgeable driver to (un)gate clocks,
even if they are marked as critical.
Suggested-by: Maxime Ripard
Quoting Lee Jones (2015-07-28 06:00:55)
On Tue, 28 Jul 2015, Maxime Ripard wrote:
On Mon, Jul 27, 2015 at 09:53:38AM +0100, Lee Jones wrote:
On Mon, 27 Jul 2015, Maxime Ripard wrote:
On Wed, Jul 22, 2015 at 02:04:13PM +0100, Lee Jones wrote:
These new API calls will firstly
On 07/29, James Liao wrote:
From: Sascha Hauer s.ha...@pengutronix.de
On the MT8173 the clocks are provided by different units. To enable
the critical clocks we must be sure that all parent clocks are already
registered, otherwise the parents of the critical clocks end up being
unused and
Quoting Lee Jones (2015-07-22 06:04:10)
Lots of platforms contain clocks which if turned off would prove fatal.
The only way to recover from these catastrophic failures is to restart
the board(s). Now, when a clock provider is registered with the
framework it is possible for a list of
On Wed, Jul 29, 2015 at 10:04:27AM -0500, Felipe Balbi wrote:
On Mon, Jul 27, 2015 at 03:21:59PM +0800, Peter Chen wrote:
On Thu, Jul 23, 2015 at 11:37:24AM +0800, Li Jun wrote:
Change for v8:
- Add Peter's ACk for chipidea driver; and Roger's Reviewed-by for patch
07, 21~23.
-
Quoting Lee Jones (2015-07-27 01:53:38)
On Mon, 27 Jul 2015, Maxime Ripard wrote:
On Wed, Jul 22, 2015 at 02:04:13PM +0100, Lee Jones wrote:
These new API calls will firstly provide a mechanisms to tag a clock as
critical and secondly allow any knowledgeable driver to (un)gate clocks,
Hi,
2015-07-30 0:23 GMT+09:00 Rob Herring robherri...@gmail.com:
On Wed, Jul 29, 2015 at 8:22 AM, Ian Campbell ian.campb...@citrix.com wrote:
On Wed, 2015-07-29 at 20:07 +0900, Masahiro Yamada wrote:
Hi Ian,
2015-07-27 19:35 GMT+09:00 Ian Campbell ian.campb...@citrix.com:
Commit
On Wed, Jul 29, 2015 at 01:16:02AM +0300, Sergei Shtylyov wrote:
Define the SILK board dependent part of the Ether device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original patch by Vladimir Barinov
vladimir.bari...@cogentembedded.com.
Signed-off-by: Sergei
On Wed, Jul 29, 2015 at 01:14:59AM +0300, Sergei Shtylyov wrote:
Add the initial device tree for the R8A7794 SoC based SILK low cost board.
SCIF2 serial port support is included, so that the serial console can work.
Based on the original patch by Vladimir Barinov
Hi Stephen,
On Wed, 2015-07-29 at 17:27 -0700, Stephen Boyd wrote:
On 07/29, James Liao wrote:
From: Sascha Hauer s.ha...@pengutronix.de
On the MT8173 the clocks are provided by different units. To enable
the critical clocks we must be sure that all parent clocks are already
On Wed, Jul 29, 2015 at 04:39:10PM -0700, Loc Ho wrote:
Debug folder node shows up at /sys/kernel/debug/file here while the
MC debug node shows up at /sys/kernel/debug/edac where file here is
the driver node name. It would be better if everything shows up at
/sys/kernel/debug/edac. For this to
On Tue, Jul 28, 2015 at 8:19 AM, Tomeu Vizoso
tomeu.viz...@collabora.com wrote:
This function is just a getter for struct acpi_device.dev and is needed
in the implementation of the fwnode API when building with !CONFIG_ACPI.
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
Changes
On Tue, Jul 28, 2015 at 8:19 AM, Tomeu Vizoso
tomeu.viz...@collabora.com wrote:
Delay matches of platform devices until late_initcall, when we are sure
that all built-in drivers have been registered already. This is needed
to prevent deferred probes because of some drivers not having
On Thu, Jul 30, 2015 at 07:24:03AM +0800, Li Jun wrote:
On Wed, Jul 29, 2015 at 10:04:27AM -0500, Felipe Balbi wrote:
On Mon, Jul 27, 2015 at 03:21:59PM +0800, Peter Chen wrote:
On Thu, Jul 23, 2015 at 11:37:24AM +0800, Li Jun wrote:
Change for v8:
- Add Peter's ACk for chipidea
On Wed, Jul 29, 2015 at 10:30:22AM +0200, Lothar Waßmann wrote:
Hi,
With this setting and AHBBRST at SBUSCFG as Incremental burst of
unspecified length, each unburst size can be taken as one single
transfer.
It is benefit for unburst size transfer.
What is an
On Wed, Jul 29, 2015 at 09:11:41PM -0500, Felipe Balbi wrote:
On Thu, Jul 30, 2015 at 07:24:03AM +0800, Li Jun wrote:
On Wed, Jul 29, 2015 at 10:04:27AM -0500, Felipe Balbi wrote:
On Mon, Jul 27, 2015 at 03:21:59PM +0800, Peter Chen wrote:
On Thu, Jul 23, 2015 at 11:37:24AM +0800, Li Jun
On 2015/7/30 1:24, Lorenzo Pieralisi wrote:
On Sat, Jul 25, 2015 at 04:21:23AM +0100, Zhou Wang wrote:
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to
On Wed, Jul 29, 2015 at 02:54:46PM +0800, Jianwei Wang wrote:
Changed in v13
-set regmap_config.cache_type to REGCACHE_RBTREE
-add call drm_modeset_lock_all before drm_mode_config_reset
This was a bug in one of my recently merged patches, please don't call
drm_modeset_lock_all before
Just a nit, I'm afraid.
On di, 2015-07-28 at 02:07 +0300, Vladimir Barinov wrote:
--- /dev/null
+++ b/drivers/iio/industrialio-triggered-event.c
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
Add DCU node, DCU is a display controller of Freescale
named 2D-ACE.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
---
arch/arm/boot/dts/ls1021a.dtsi | 10 ++
1 file changed, 10
Add a TFT LCD panel. the TFT LCD panel is WQVGA 480x272,
and the bpp is 24.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
---
arch/arm/boot/dts/ls1021a-twr.dts | 11 +++
1 file
On Wed, Jul 29, 2015 at 1:58 AM, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Ley,
On 28/07/15 11:45, Ley Foon Tan wrote:
This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.
Can't you read this configuration from the HW?
No,
Currently we find that if a usdhc is choosed to boot system, then ROM
code will set the burst length enable bit of this usdhc as 0.
This will make performance drop a lot if this usdhc's burst length is
16. So this patch set back the burst_length_enable bit as 1, which is
the default value, and
On 29/07/15 09:52, Ley Foon Tan wrote:
On Wed, Jul 29, 2015 at 1:58 AM, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Ley,
On 28/07/15 11:45, Ley Foon Tan wrote:
This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.
Can't you
On Wed, Jul 29, 2015 at 10:30:22AM +0200, Lothar Waßmann wrote:
Hi,
With this setting and AHBBRST at SBUSCFG as Incremental burst of
unspecified length, each unburst size can be taken as one single transfer.
It is benefit for unburst size transfer.
What is an 'unburst'?
Assume
On 07/23/2015 09:05 PM, R, Vignesh wrote:
On 7/16/2015 9:01 PM, R, Vignesh wrote:
Hi,
On 07/16/2015 03:24 AM, Paul Walmsley wrote:
Hi,
some comments.
On Wed, 3 Jun 2015, Vignesh R wrote:
Add hwmod entries for the PWMSS on DRA7.
Set l4_root_clk_div as the main_clk of PWMSS. It is
On Wed, Jul 29, 2015 at 3:21 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Jul 29, 2015 at 02:54:46PM +0800, Jianwei Wang wrote:
Changed in v13
-set regmap_config.cache_type to REGCACHE_RBTREE
-add call drm_modeset_lock_all before drm_mode_config_reset
This was a bug in one of my recently
On wo, 2015-07-29 at 00:58 -0700, Christoph Hellwig wrote:
Btw, who came up with that meaning? The default Linux license is GPLv2
only and unless othewise specified that's what we should get by default.
I cobbled together a short history of these license idents in
This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM
simple panel driver.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
Acked-by: Daniel Vetter daniel.vet...@ffwll.ch
---
This patch add support for Two Dimensional Animation and Compositing
Engine (2D-ACE) on the Freescale SoCs.
2D-ACE is a Freescale display controller. 2D-ACE describes
the functionality of the module extremely well its name is a value
that cannot be used as a token in programming languages.
Add Alison and myself as maintainers of the Freescale DCU DRM driver.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff
On Wed, Jul 29, 2015 at 1:00 AM, Dinh Nguyen dinh.li...@gmail.com wrote:
On Tue, Jul 28, 2015 at 5:45 AM, Ley Foon Tan lf...@altera.com wrote:
This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.
Signed-off-by: Ley Foon Tan
Add a required property fsl,imx7d-usdhc in binding doc.
Add an optional property fsl,tuning-step in binding doc.
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
On 28/07/15 20:38, Lina Iyer wrote:
Hello,
I am looking to find a way to uniquely identify a device in the driver.
Here is an example -
big: power-controller@1 {
compatible = soc,foo;
...
};
little: power-controller@2 {
On Thu, 2015-07-23 at 22:40 +0800, Daniel Kurtz wrote:
Hi Yong,
On Thu, Jul 16, 2015 at 5:04 PM, Yong Wu yong...@mediatek.com wrote:
This patch add the iommu/larbs nodes for mt8173
To what tree does this apply?
Please rebase these patches (especially this one) on an Matthias'
current
On di, 2015-07-28 at 18:45 +0800, Ley Foon Tan wrote:
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
+config PCIE_ALTERA
+ bool Altera PCIe controller
+ depends on ARCH_SOCFPGA
+ depends on OF
+ select PCI_MSI_IRQ_DOMAIN if PCI_MSI
+ help
+ Say Y
Changed in v14
-Remove drm_modeset_lock_all before drm_mode_config_reset
Changed in v13
-set regmap_config.cache_type to REGCACHE_RBTREE
-add call drm_modeset_lock_all before drm_mode_config_reset
-adjust patch order for creating pull request
Changed in v12
-Add one patch for MAINTAINER entry
On 07/27/2015 04:42 PM, Srinivas Kandagatla wrote:
Hi Greg/Kevin,
This patchset adds a new simple NVMEM framework to kernel, and it is tested
with various drivers like QCOM thermal sensors, QCOM cpr driver,
begal bone cape manager and few more on the way.
Can you please consider this as 4.3
Hello Guenter,
On Tue, Jul 28, 2015 at 02:21:55PM -0700, Guenter Roeck wrote:
On Tue, Jul 28, 2015 at 10:33:48PM +0200, Uwe Kleine-König wrote:
This is just a suggestion up to now, I don't have any code yet to share.
Apart from minor rewording to make the document easier to understand and
On Tue, 28 Jul 2015, Stephen Boyd wrote:
On 07/28, Viresh Kumar wrote:
Cc'ing few people (whom I cc'd last time as well :)).
On 27-07-15, 16:20, Lee Jones wrote:
These OPPs are used in ST's CPUFreq implementation.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
NEC represent NEC LCD Technologies, Ltd.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
Hi,
With this setting and AHBBRST at SBUSCFG as Incremental burst of
unspecified length, each unburst size can be taken as one single transfer.
It is benefit for unburst size transfer.
What is an 'unburst'?
Lothar Waßmann
--
___
On 29/07/15 09:49, Rajendra Nayak wrote:
On 07/27/2015 04:42 PM, Srinivas Kandagatla wrote:
Hi Greg/Kevin,
This patchset adds a new simple NVMEM framework to kernel, and it is
tested
with various drivers like QCOM thermal sensors, QCOM cpr driver,
begal bone cape manager and few more on the
tuning-step is the delay cell steps in tuning procedure. The default value
of tuning-step is 1. For imx6 series usdhc, tuning procedure can be passed
when the tuning-step value is 1. But imx7d usdhc need the tuning-step value
as 2, otherwise it can't pass the tuning procedure.
So this patch add
imx7d-sdb board has a eMMC5.0 on usdhc3. This eMMC support HS400.
This patch add usdhc3 support for HS400
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
arch/arm/boot/dts/imx7d-sdb.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts
i.MX7D support eMMC HS400 mode, this mode can run in 8 bit,200MHZ
DDR mode. So the I/O speed improve a lot compare to SD3.0
The default burst length is 8, if we don't change this value, in
HS400 mode, when we do eMMC read operation, we can find that the
clock signal will stop for a period of
The imx7d usdhc is derived from imx6sx, the difference is that
imx7d support HS400.
So introduce a new compatible string for imx7d and add HS400
support for imx7d usdhc.
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 66
Changes for v3:
-Add property describe in binding doc.
Haibo Chen (6):
mmc: sdhci-esdhc-imx: add imx7d support and support HS400
mmc: sdhci-esdhc-imx: add tuning-step seting support
ARM: dts: imx7d-sdb: add eMMC5.0 support
mmc: sdhci-esdhc-imx: add compatible string in bingding doc
mmc:
On Wed, Jul 29, 2015 at 09:56:50AM +0200, Paul Bolle wrote:
+MODULE_LICENSE(GPL);
And, according to include/linux/module.h, this states the license is GPL
v2 or later. So either the comment or the ident used in the
Btw, who came up with that meaning? The default Linux license is GPLv2
On 07/27/2015 03:16 PM, Kishon Vijay Abraham I wrote:
pbias device creation got broken once SCM cleanup got merged.
This patch series re-enables device creation by adding
simple-bus in the compatible property of the syscon
dt node.
validated this series in DRA72, OMAP4 PANDA and OMAP5 UEVM
Am Mittwoch, 29. Juli 2015, 14:52:25 schrieb James Liao:
The dpi_ck clock can be removed because it not actually used
in topckgen and subsystems.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
From our past discussions this change looks about right, and should still
become _part of
Hi Sören,
On Tue, Jul 28, 2015 at 3:53 PM, Sören Brinkmann
soren.brinkm...@xilinx.com wrote:
On Mon, 2015-07-27 at 09:52PM -0700, Moritz Fischer wrote:
Hi Sören,
thanks for your feedback.
On Mon, Jul 27, 2015 at 7:58 PM, Sören Brinkmann
soren.brinkm...@xilinx.com wrote:
Hi Moritz,
On
On Mon, 2015-07-27 at 14:23 +0100, Robin Murphy wrote:
On 16/07/15 10:04, Yong Wu wrote:
This patch adds support for mediatek m4u (MultiMedia Memory Management
Unit).
Signed-off-by: Yong Wu yong...@mediatek.com
[...]
+static void mtk_iommu_flush_pgtable(void *ptr, size_t size, void
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-apmixed.c | 107 +
This patchset is based on 4.2-rc1 and [1], and contains minor fixes and
subsystem clocks support for Mediatek MT8173.
The previous reviews can be found in [2]. The most different from previous
patchset are adding separated patches for minor coding fixes, and refining
USB clock implementation by
NEC represent NEC LCD Technologies, Ltd.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang jianwei.wang@gmail.com
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
This patch add support for Two Dimensional Animation and Compositing
Engine (2D-ACE) on the Freescale SoCs.
2D-ACE is a Freescale display controller. 2D-ACE describes
the functionality of the module extremely well its name is a value
that cannot be used as a token in programming languages.
Changed in v13
-set regmap_config.cache_type to REGCACHE_RBTREE
-add call drm_modeset_lock_all before drm_mode_config_reset
-adjust patch order for creating pull request
Changed in v12
-Add one patch for MAINTAINER entry for drm/layerscape
Adviced by Daniel Vetter
-Add #include
On Wed, Jul 29, 2015 at 07:51:55AM +0200, Sascha Hauer wrote:
Hi Peter,
On Wed, Jul 29, 2015 at 10:42:06AM +0800, Peter Chen wrote:
The system bus and chipidea IP have different limitations for
both host and device mode.
For example, with below errata, we need to enable SDIS(Stream
Remove the dependency from clk_null, and give all root clocks a
typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts.
dpi_ck was removed due to no clock reference to it.
Replace parent clock of infra_cpum with cpum_ck, which is an external
clock and can be defined in the device
From: Sascha Hauer s.ha...@pengutronix.de
On the MT8173 the clocks are provided by different units. To enable
the critical clocks we must be sure that all parent clocks are already
registered, otherwise the parents of the critical clocks end up being
unused and get disabled later.
On MT8173, for
Add __init for clock registration functions, and add __initdata for
mtk_gate_regs initial structures.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/clk-gate.c | 2 +-
drivers/clk/mediatek/clk-mt8173.c | 6 +++---
drivers/clk/mediatek/clk-mtk.c| 13
This patch adds fixed clocks support by using CCF fixed-rate
clock implementation.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/clk-mtk.c | 23 +++
drivers/clk/mediatek/clk-mtk.h | 17 +
2 files changed, 40 insertions(+)
diff
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