On 2015年08月05日 00:11, Srinivas Kandagatla wrote:
Hi Shunqian,
Sorry for delay in reply, I was on Holidays..
Thanks for testing.
On 31/07/15 10:27, Shunqian Zheng wrote:
1. Without the following diff, `hexdump
/sys/bus/nvmem/devices/rockchip-efuse0/nvmem` is wrong with INVALID
ARGUMENT:
On 07/28/2015 05:54 AM, Srinivas Kandagatla wrote:
@@ -618,5 +633,77 @@
compatible = qcom,tcsr-apq8064, syscon;
reg = 0x1a40 0x100;
};
+
+ hdmi: qcom,hdmi-tx@4a0 {
+ compatible =
On 08/05/2015 09:43 PM, Moritz Fischer wrote:
Michal,
On Tue, Aug 4, 2015 at 8:10 AM, Philipp Zabel p.za...@pengutronix.de wrote:
Hi Moritz,
Am Dienstag, den 04.08.2015, 08:05 -0700 schrieb Moritz Fischer:
Hi Philip,
On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel p.za...@pengutronix.de
From SAMA5D4, the watchdog timer is upgrated with a new feature,
which is describled as in the datasheet, WDT_MR can be written
until a LOCKMR command is issued in WDT_CR.
That is to say, as long as the bootstrap and u-boot don't issue
a LOCKMR command, WDT_MR can be written more than once in the
The compatible atmel,sama5d4-wdt supports the SAMA5D4 watchdog driver
and the watchdog's WDT_MR register can be written more than once.
Signed-off-by: Wenyou Yang wenyou.y...@atmel.com
---
.../bindings/watchdog/atmel-sama5d4-wdt.txt| 35
1 file changed, 35
On Wed, 2015-08-05 at 10:50 +0200, Sascha Hauer wrote:
On Tue, Aug 04, 2015 at 09:54:19PM +0800, Scott Shu wrote:
This adds a CPU power domain driver for the Mediatek SCPSYS unit on
MT6580.
Signed-off-by: Scott Shu scott@mediatek.com
---
drivers/soc/mediatek/mtk-scpsys.c |
This changes of_fdt_unflatten_tree() so that it returns the allocated
memory chunk for unflattened device-tree, which can be released once
it's obsoleted.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
drivers/of/fdt.c | 11 ++-
include/linux/of_fdt.h | 2 +-
2 files
The original implementation of pnv_ioda_setup_dma() iterates the
list of PEs and configures the DMA32 space for them one by one.
The function was designed to be called during PHB fixup time.
When configuring PE's DMA32 space in pcibios_setup_bridge(), in
order to support PCI hotplug, we have to
The patch intends to add standalone driver to support PCI hotplug
for PowerPC PowerNV platform, which runs on top of skiboot firmware.
The firmware identified hotpluggable slots and marked their device
tree node with proper ibm,slot-pluggable and ibm,reset-by-firmware.
The driver simply scans
The patch exports 4 functions, which base on corresponding OPAL
APIs to get or set PCI slot status. Those functions are going to
be used by PCI hotplug module in subsequent patches:
pnv_pci_get_device_tree() opal_get_device_tree()
pnv_pci_get_presence_status()
pnv_pci_reset_secondary_bus(), invoked by pcibios_reset_secondary_bus()
on PowerNV platform. The latter can't be called on root bus. So the
former needn't cover root bus as well.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-powernv.c | 12
This renames pcibios_{add,remove}_pci_devices to avoid conflicts
with names of weak functions in PCI subsystem. This doesn't
introduce logicial changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pci-bridge.h | 4 ++--
arch/powerpc/kernel/eeh_driver.c
The patch introduces helper function pnv_ioda_init_pe(), which
initialize PE instance after reserving or allocating PE#, to
simplify the code. The patch doesn't introduce behavioural
changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c | 20
Each PHB maintains one instance of struct pci_controller_ops,
which includes various callbacks called by PCI subsystem. In the
definition of this struct, some callbacks have explicit names for
its arguments, but the left don't have.
This adds all explicit names of the arguments to the callbacks
The patch cleans up DMA32 in pci-ioda.c. It shouldn't introduce
behavioural changes:
* Rename various fields in struct pnv_phb and struct pnv_ioda_pe
as 32-bits DMA should be related to DMA, not TCE.
* Removed struct pnv_ioda_pe::tce32_segcount.
Signed-off-by: Gavin Shan
This moves pcibios_find_pci_bus() to PowerPC kernel directory
so that it can be reused by hotplug code for pSeries and PowerNV
platform at the same time. Also, the function is renamed to
of_node_to_pci_bus().
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
Acked-by: Benjamin Herrenschmidt
PowerNV platform is running on top of skiboot firmware, which has
changes to support PCI slots. PCI slots are identified by PHB's
OPAL ID (PHB slot) or combo of that and PCI slot ID. The patch
changes argument names of opal_pci_reset() and opal_pci_poll()
to reflect the firmware's change.
This introduces one more argument to of_fdt_unflatten_tree()
to specify the root node for the FDT blob, which is going to be
unflattened. In the result, the function can be used to unflatten
FDT blob, which represents device sub-tree in PowerNV hotplug
driver.
Signed-off-by: Gavin Shan
During the PCI plugging event, the PCI devices are rescanned and
their IO and MMIO resources are reassigned. However, the PowerNV
platform will assign PE# based on that, which depends on updating
to window of bridge of the PE's primary bus.
The patch updates the windows of bridge of PE's primary
This adds the refcount to PE, which represents number of PCI
devices contained in the PE. When last device leaves from the
PE, the PE together with its consumed resources (IO, DMA, PELTM,
PELTV) are released, to support PCI hotplug.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
Some subordinate PCI devices of one particular PCI bus might ask
for fundamental reset because the default (hot) reset isn't enough
for those PCI devices to be up successfully after reset.
This iterates all PCI devices behind the specified PCI bus and issues
fundamental reset if any one PCI
The pci_dn instances are allocated from memblock or bootmem when
creating PCI controller (hoses) in setup_arch(). The PCI hotplug,
which will be supported by proceeding patches, will release PCI
device nodes and their corresponding pci_dn on unplugging event.
The pci_dn instance memory chunks
This converts pnv_eeh_poll() to pnv_pci_poll() in order to:
* Return linux error code other than OPAL error code.
* The return value from last OPAL call, requested delay, is
passed to pnv_pci_poll() and delay accordingly. Thus one
call to opal_pci_poll() is saved.
* More
Each PHB maintains an array helping to translate RID (Request
ID) to PE# with the assumption that PE# takes 8 bits, indicating
that we can't have more than 256 PEs. However, pci_dn-pe_number
already had 4-bytes for the PE#.
The patch extends the PE# capacity so that each of them will be
4-bytes
The skiboot firmware might provide the capability of resetting PCI
slot by property ibm,reset-by-firmware on the PCI slot associated
device node. The patch checks on the property and route the reset
to firmware if the property exists. Otherwise, we fail back to the
old path as before.
Previously we wouldn't remove pdn because PCI hotplug isn't
supported. update_dn_pci_info() is called at system booting
time to create pdn for PCI device nodes. However, it's going
to be changed later because of PCI hotplug.
This converts update_dn_pci_info() to add_pci_device_node_info(),
The patch moves functions related to releasing PE around so that
we don't need extra declaration for them in subsequent patches.
Also, it fixes warnings from scripts/checkpatch.pl. It doesn't
introduce any behavioural changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
Every PHB maintains a list of PEs based on their DMA32 weight. After
patch powerpc/powernv: Create PEs dynamically, the list is useless
and it's safe to remove it.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c | 18 --
This renames the fields related to PE# in struct pnv_phb for
better reflecting of their usages as Alexey suggested. It doesn't
introduce behavioural changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-powernv.c | 2 +-
For P7IOC, the whole available DMA32 space, which is below the
MEM32 space, is divided evenly into 256MB segments. The number
of continuous segments assigned to one particular PE depends on
the PE's DMA weight that is calculated based on the type of each
PCI devices contained in the PE, and PHB's
Hello,
Because the watchdog WDT_MR register can be written more than once,
its work mechanism is different from the at91sam9260 watchdog driver.
Open the device file to enable the watchdog hardware, close to disable it,
and ping it from the user space directly to keep it alive.
Changes from v3.0
Hi Lothar,
Thank you for your review.
-Original Message-
From: Lothar Waßmann [mailto:l...@karo-electronics.de]
Sent: 2015年8月5日 18:41
To: Yang, Wenyou
Cc: w...@iguana.be; robh...@kernel.org; pawel.m...@arm.com;
mark.rutl...@arm.com; ijc+devicet...@hellion.org.uk;
pcibios_setup_bridge() is normally called to update PCI bridge
windows. It allocates PE for PCI buses. However it is not called
on a root bus which does not have an upstream bridge.
This reserves PE# for a root bus in advance. This will be used in
the subsequent patch to do setup.
Signed-off-by:
The original implementation of pnv_ioda_setup_pe_seg() configures
IO and M32 segments by separate logics, which can be merged by
by caching @seg_bitmap, @seg_size, @win in advance. The patch
shouldn't cause any behavioural changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
On P7IOC, the whole DMA32 space is divided evenly to 256MB segments.
Each PE can consume one or multiple DMA32 segments. Current code
doesn't trace the available DMA32 segments and those consumed by
one particular PE. It's conflicting with PCI hotplug.
The patch introduces one bitmap to PHB to
The PowerNV PCI hotplug driver is going to use the OF changeset
to manage the changed device sub-tree, which requires those OF
changeset functions are exported.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
drivers/of/dynamic.c | 65 ---
Currently, the PEs and their associated resources are assigned
in ppc_md.pcibios_fixup() except those consumed by SRIOV VFs.
The function is called for once after PCI probing and resources
assignment is finished which isn't hotplug friendly.
The patch creates PEs dynamically by
The available PE#, represented by a bitmap in the PHB, is allocated
in ascending order. It conflicts with the fact that M64 segments are
assigned in same order. In order to avoid the conflict, the patch
allocates PE# in descending order.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
The patch overrides pcibios_setup_bridge(), called to update PCI
bridge windows at completion of PCI resource assignment, to assign
PE and setup various (resource) mapping in next patch.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pci-bridge.h | 2 ++
Several functions used to configure PE take pe_number to indentify
PE instance. As the pe_number is included in PE instance after it
is reserved or allocated. It's convienent for those functions to
return PE instance which includes the required pe_number.
Signed-off-by: Gavin Shan
The device tree nodes will be changed dynamically on PCI hotplug
events on PowerNV platform. This enables CONFIG_OF_DYNAMIC on
PowerNV platform to support that.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/Kconfig | 1 +
1 file changed, 1 insertion(+)
In hotplug case, function pcibios_add_pci_devices() is called to
rescan the specified PCI bus, which might not have any child devices.
Access to the PCI bus's child device node will cause kernel crash
without exception.
This adds condition of skipping scanning PCI bus without child devices
in
This simplifies pnv_eeh_reset() by avoiding the unnecessary nested
if statement. No logicial changes introduced by this.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-powernv.c | 65 +---
1 file changed, 31 insertions(+), 34
There're 3 windows (IO, M32 and M64) for PHB, root port and upstream
port of the PCIE switch behind root port. In order to support PCI
hotplug, we extend the start/end address of those 3 windows of root
port or upstream port to the start/end address of the 3 PHB's windows.
The current
unflatten_dt_node() is called recursively to unflatten FDT nodes
with the assumption that FDT blob has only one root node, which
isn't true when the FDT blob represents device sub-tree. This
improves the function to supporting device sub-tree that have
multiple nodes in the first level:
*
Currently, PowerPC PowerNV platform utilizes ppc_md.pcibios_fixup(),
which is called for once after PCI probing and resource assignment
are completed, to allocate platform required resources for PCI devices:
PE#, IO and MMIO mapping, DMA address translation (TCE) table etc.
Obviously, it's not
The series of patches intend to support PCI slot for PowerPC PowerNV platform,
which is running on top of skiboot firmware. The patchset requires corresponding
changes from skiboot firmware, which is sent to skib...@lists.ozlabs.org
for review. The PCI slots are exposed by skiboot with device node
The patch enables M64 window on P7IOC, which has been enabled on
PHB3. Different from PHB3 where 16 M64 BARs are supported and each
of them can be owned by one particular PE# exclusively or divided
evenly to 256 segments, each P7IOC PHB has 16 M64 BARs and each
of them are divided into 8 segments.
The patches moves those fields of struct pnv_phb that are related
to PE# allocation around. No logical change.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci.h | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git
Nobody is using the this function. The patch drops it.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
Reviewed-by: Alexey Kardashevskiy a...@ozlabs.ru
---
arch/powerpc/platforms/powernv/pci-ioda.c | 71 ---
1 file changed, 71 deletions(-)
diff --git
The patch is adding 6 bitmaps, three to PE and three to PHB, to track
the consumed by one particular PE, which can be released once the PE
is destroyed during PCI unplugging time. Also, we're using fixed
quantity of bits to trace the used IO, M32 and M64 segments by PEs
in one particular PHB.
On Wednesday 05 August 2015 06:05 PM, Alexandre Belloni wrote:
On 05/08/2015 at 17:31:22 +0530, Keerthy wrote :
This is a special one where in the enable bit is present in the rtc register
space and not in the prcm register space. Since there was a concern on the
external clock not being
On Tue, 2015-08-04 at 18:42 +0100, Mark Brown wrote:
On Wed, Jul 29, 2015 at 07:04:32PM +0800, Leilk Liu wrote:
Signed-off-by: Leilk Liu leilk@mediatek.com
Please use subject lines reflecting the style for the subsystem so
people can spot if patches are relevant to them.
OK, I will
Added the basic driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. The initial release of this driver supports
only memory to memory transfers.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- Modified the defines to start with ZYNQMP_DMA perfix
- Changed
On Thursday 06 August 2015 12:41 AM, Robert Jarzmik wrote:
My next slot is probably this comming Sunday. I'll do the test and report
Thanks a lot.
Thanks,
Vaibhav
--
To unsubscribe from this list: send the line unsubscribe devicetree in
the body of a message to majord...@vger.kernel.org
On Wednesday 05 August 2015 10:21 PM, Felipe Balbi wrote:
On Wed, Aug 05, 2015 at 09:48:08PM +0530, Keerthy wrote:
On Wednesday 05 August 2015 09:44 PM, Felipe Balbi wrote:
On Wed, Aug 05, 2015 at 09:21:05PM +0530, Keerthy wrote:
Felipe,
On Wednesday 05 August 2015 09:01 PM, Felipe Balbi
Hi Guenter,
Thank you for your review.
-Original Message-
From: Guenter Roeck [mailto:li...@roeck-us.net]
Sent: 2015年8月5日 23:05
To: Yang, Wenyou; w...@iguana.be; robh...@kernel.org; pawel.m...@arm.com;
mark.rutl...@arm.com; ijc+devicet...@hellion.org.uk; ga...@codeaurora.org
Cc:
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
---
.../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61
Commit(def56bb input: snvs_pwrkey: use wakeup-source
as deivce tree property name) replaces the property name
of wakeup with wakeup-source, update this change
in i.MX6SX dtsi accordingly.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6sx.dtsi | 2 +-
1 file changed, 1
Add i.MX6UL SNVS power key support.
Signed-off-by: Anson Huang b20...@freescale.com
---
This patch is based on my last patch under review:
(ARM: dts: imx6ul: add RTC support).
arch/arm/boot/dts/imx6ul.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi
On 08/04/2015 07:35 PM, Wenyou Yang wrote:
From SAMA5D4, the watchdog timer is upgrated with a new feature,
which is describled as in the datasheet, WDT_MR can be written
until a LOCKMR command is issued in WDT_CR.
That is to say, as long as the bootstrap and u-boot don't issue
a LOCKMR
On Monday 27 July 2015 07:41 PM, Matt Porter wrote:
On Tue, Jul 21, 2015 at 06:11:05PM +0530, Vaibhav Hiremath wrote:
With addition of PXA910 family of devices, the TWSI module supports
new feature which allows us to adjust SCLK. i2c-pxa driver takes input
configuration in nsec and converts
On Monday 27 July 2015 07:39 PM, Matt Porter wrote:
On Tue, Jul 21, 2015 at 06:11:02PM +0530, Vaibhav Hiremath wrote:
Driver will now supports enable/disable across msg xfer, which user
can control it by new DT property -
i2c-disable-after-xfer : If set, driver will disable I2C module after
On Tue, 2015-08-04 at 16:36 +0100, Mark Brown wrote:
On Tue, Aug 04, 2015 at 01:18:15PM +0200, Sjoerd Simons wrote:
Sjoerd Simons (4):
ASoC: dt-bindings: add rockchip tranceiver bindings
ASoc: rockchip: Add rockchip SPDIF transceiver driver
I only appear to have patch 2 (with the
On Tue, Aug 04, 2015 at 04:16:56PM +0800, James Liao wrote:
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.
Signed-off-by: James Liao
On Tue, Aug 04, 2015 at 04:16:54PM +0800, James Liao wrote:
Remove the dependency from clk_null, and give all root clocks a
typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts.
dpi_ck was removed due to no clock reference to it.
Replace parent clock of infra_cpum with
Hi Simon,
On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman ho...@verge.net.au wrote:
On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
I have tentatively queued this up in its own branch,
cpg-mstp-clock-domain-for-v4.3.
Where possible I prefer not to apply non-DTS/DTSI patches on top
On 05 August 2015 02:55 Alexandre Belloni wrote:
Subject: Re: [PATCH V3 3/3] rtc: da9063: Add DA9062 RTC capability to DA9063
RTC driver
On 21/07/2015 at 11:29:07 +0100, S Twiss wrote :
From: S Twiss stwiss.opensou...@diasemi.com
Add DA9062 RTC support into the existing DA9063 RTC
On Wed, Aug 5, 2015 at 2:46 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Tue, Aug 04, 2015 at 04:16:56PM +0800, James Liao wrote:
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for
Hello Dmitry,
On 15-08-03 14:04:09, Dmitry Torokhov wrote:
Hi Sanchayan,
On Mon, Aug 03, 2015 at 08:55:44PM +0530, maitysancha...@gmail.com wrote:
Hello Dmitry,
On 15-07-21 10:20:44, Dmitry Torokhov wrote:
Hi Stefan,
On Tue, Jul 21, 2015 at 04:43:36PM +0200, Stefan Agner
On Wed, Aug 05, 2015 at 03:26:29PM +0800, Daniel Kurtz wrote:
On Wed, Aug 5, 2015 at 2:46 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Tue, Aug 04, 2015 at 04:16:56PM +0800, James Liao wrote:
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to
On Wed, Aug 5, 2015 at 3:36 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Wed, Aug 05, 2015 at 03:26:29PM +0800, Daniel Kurtz wrote:
On Wed, Aug 5, 2015 at 2:46 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Tue, Aug 04, 2015 at 04:16:56PM +0800, James Liao wrote:
Most multimedia
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
Add syscon-phy-power property and remove the deprecated ctrl-module
property from SATA PHY node. Since omap_control_sata note is no longer
used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Roger Quadros
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Roger Quadros rog...@ti.com
cheers,
-roger
---
arch/arm/boot/dts/dra7.dtsi |
On Wed, Aug 5, 2015 at 3:50 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Wed, Aug 05, 2015 at 03:41:49PM +0800, Daniel Kurtz wrote:
On Wed, Aug 5, 2015 at 3:36 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Wed, Aug 05, 2015 at 03:26:29PM +0800, Daniel Kurtz wrote:
On Wed, Aug 5,
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
Add syscon-phy-power property and remove the deprecated ctrl-module
property from USB PHY devicetree nodes.
Since omap_control_usb2phy1, omap_control_usb3phy1 and
omap_control_usb2phy2 devicetree nodes are no longer used, remove it.
s/it/them
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
Add syscon-phy-power property and remove the deprecated ctrl-module
property from USB PHY device tree node.
Since am43xx_control_usb2phy1 and am43xx_control_usb2phy2
devicetree nodes are no longer used, remove it.
Signed-off-by: Kishon
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
Add syscon-phy-power property and remove the deprecated ctrl-module
property from USB PHY devicetree node.
Since omap_control_usb2phy and omap_control_usb3phy devicetree nodes
are no longer used, remove it.
Signed-off-by: Kishon Vijay
* Kishon Vijay Abraham I kis...@ti.com [150804 07:11]:
Deprecate using phy-omap-control driver to write to the mailbox register
and start using *syscon* framework to do the same.
..
@@ -512,6 +558,40 @@ static const struct musb_platform_ops omap2430_ops = {
static u64 omap2430_dmamask =
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
Add syscon-phy-power property and remove the deprecated ctrl-module
property from USB PHY dt node.
Since omap_control_usb2phy devicetree node is no longer used,
remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Roger
Kishon,
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
Add syscon-otghs property and remove the deprecated ctrl-module
property from MUSB devicetree node.
Since omap_control_usbotg devicetree node is no longer used, remove
it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
On 05/08/15 11:02, Roger Quadros wrote:
Kishon,
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
Add syscon-otghs property and remove the deprecated ctrl-module
property from MUSB devicetree node.
Since omap_control_usbotg devicetree node is no longer used, remove
it.
Signed-off-by:
On Wed, Aug 05, 2015 at 03:39:29PM +0800, Chen Haibo-B51421 wrote:
-Original Message-
From: Dong Aisheng [mailto:aisheng.d...@freescale.com]
Sent: Monday, August 03, 2015 8:10 PM
To: Chen Haibo-B51421
Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, add a new
compatible string.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
On 05/08/15 11:23, Roger Quadros wrote:
On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, add a new
compatible string.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
On Tue, Aug 4, 2015 at 8:34 PM, Matt Porter mpor...@konsulko.com wrote:
On Tue, Aug 04, 2015 at 05:52:17PM +0100, Jonathan Cameron wrote:
On 3 August 2015 21:56:47 BST, Matt Porter mpor...@konsulko.com wrote:
This series adds a driver for the MAX6675 SPI thermocouple converter.
The device
On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
Deprecate using phy-omap-control driver to power on/off the PHY,
and use *syscon* framework to do the same. This handles
powering on/off the PHY for the USB2 PHYs used in various TI SoCs.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Hi all,
On Wed, Jun 10, 2015 at 6:44 PM, Gary Bisson
gary.bis...@boundarydevices.com wrote:
Hi all,
This patch is the follow-up of a request from Philipp to add the Okaya display
to the simple panel driver.
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/346657.html
v2:
-
Hi Guenter,
Thank you very much for your review.
I will send a new version to resolve them.
-Original Message-
From: Guenter Roeck [mailto:li...@roeck-us.net]
Sent: 2015年8月5日 14:14
To: Yang, Wenyou; w...@iguana.be; robh...@kernel.org; pawel.m...@arm.com;
mark.rutl...@arm.com;
Yeah, we could start i2c.txt, probably better to have separate new
patch all together.
I will start such a file today as part of the i2c slave framework
update which introduces flags to the reg property. Will post to the i2c
list this week.
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On Thursday 23 July 2015 09:23 PM, Lee Jones wrote:
On Tue, 21 Jul 2015, Vaibhav Hiremath wrote:
88PM860 family of device supports dual phase mode on BUCK1 supply
providing total 6A capacity.
Note that by default they operate independently with 3A capacity.
This patch updates the devicetree
Hi,
On 27/07/2015 at 09:37:20 -0400, Matt Porter wrote :
+Required properties:
+- compatible : must contain nxp,lpc1788-rtc
+- reg : Specifies base physical address and size of the
registers.
+- interrupts : A single interrupt specifier.
+- clocks : Must
On Tue, Aug 04, 2015 at 09:54:19PM +0800, Scott Shu wrote:
This adds a CPU power domain driver for the Mediatek SCPSYS unit on
MT6580.
Signed-off-by: Scott Shu scott@mediatek.com
---
drivers/soc/mediatek/mtk-scpsys.c | 250
+++
On Tuesday 21 July 2015 06:11 PM, Vaibhav Hiremath wrote:
With addition of PXA910 family of devices, the TWSI module supports
SCL clock adjustment using ILCR register.
This patch enables the control and configuration of ICLR through DT
properties,
i2c-sclk-high-time-ns:
SCLK high time
On Thursday 23 July 2015 09:22 PM, Lee Jones wrote:
On Tue, 21 Jul 2015, Vaibhav Hiremath wrote:
Update header file with required macros for 32KHz buffered clock
output of 88PM800 family of device.
These macros will be used in clk provider driver.
Signed-off-by: Vaibhav Hiremath
Add the missing L2 cache-controller node. This will allow migration to
the generic l2c OF initialization.
The L2 cache is an ARM L2C-310 (r3p1), of size 512 KiB (64 KiB x 8
ways).
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v4:
- New,
- Commit eeedcea69e927857 (ARM: 8395/1:
Add the missing L2 cache-controller node. This will allow migration to
the generic l2c OF initialization.
The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x
8 ways).
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v4:
- Commit eeedcea69e927857 (ARM: 8395/1:
{,~}L2C_AUX_CTRL_SHARED_OVERRIDE in
machine_desc.l2c_aux_{val,mask}, as there's no DT property for
this.
- Add L1 cache to DT.
Dependencies:
- This series applies to renesas-devel-20150805-v4.2-rc5,
- Patch 2 depends on patch 1,
- Patch 4 depends on patch 2,
- Patch 5 depends on patch 1 and on ARM: 8395/1
Migrate the generic r8a7740 platform from calling l2x0_of_init() to the
generic l2c OF initialization.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v4:
- This depends on commit eeedcea69e927857 (ARM: 8395/1: l2c: Add
support for the arm,shared-override property), which is
Describe the L1 cache in the CPU node:
- L1 instruction cache: 32 KiB (8 KiB x 4 ways),
- L1 data cache: 32 KiB (8 KiB x 4 ways).
Add a link to the L2 cache.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v4:
- No changes,
v3:
- No changes,
v2:
- New.
---
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