在 2015/8/8 5:32, Joachim Eastwood 写道:
Hi Shawn,
On 6 August 2015 at 08:44, Shawn Lin shawn@rock-chips.com wrote:
DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch
Hi David,
On Sat, Aug 8, 2015 at 2:11 AM, David Daney dda...@caviumnetworks.com wrote:
On 08/07/2015 05:05 PM, Rafael J. Wysocki wrote:
[cut]
It is actually useful to people as far as I can say.
Also, if somebody is going to use properties with ACPI, why whould
they use a different set of
Hello Sato-san,
Unfortunately this patch did not Cc myself, Stephen Boyd or the
linux-...@vger.kernel.org mailing list. As such Stephen and I did not
have a chance to review it. Even more unfortunate was that it was ninja
merged by maintainers without our ack. :-/
Quoting Yoshinori Sato
Hi,
On Thu, Jul 30, 2015 at 5:45 PM, Mikhail Yakshin grey...@whiteboxes.ch wrote:
Hi,
I've been analyzing various boards based on Allwinner A20 CPU and
X-Powers AXP209 PMU (to make a proper configuration for our board,
Whitebox Labs Watermelon).
There are some things very common and some
On 07/29/2015 02:57 PM, Vladimir Barinov wrote:
Add periodic polling functionality to SYSFS trigger
Daniel's hrtimer trigger should be used for this instead of modifying the
sysfs trigger timer. See https://lkml.org/lkml/2015/5/8/367
He said he'll send out a new version shortly.
- Lars
--
To
Raspberry Pi uses a DWC2 USB controller and a SMSC USB Ethernet adaptor.
Driver model support for these was recently merged.
This series does the following:
- Move Raspberry Pi to use device tree control (u-boot-dtb.bin instead of
u-boot.bin)
- Remove GPIO platform data (now uses device
This binding differs from that of Linux. Update it and change existing
users.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Rename binding file to pl01x.txt
Changes in v2: None
arch/arm/dts/stv0991.dts | 2 +-
doc/device-tree-bindings/serial/pl01x.txt |
On Fri, Aug 7, 2015 at 7:09 AM, Mark Brown broo...@kernel.org wrote:
On Thu, Aug 06, 2015 at 04:11:43PM +0200, Tomeu Vizoso wrote:
When looking up a regulator through its OF node, probe it if it hasn't
already.
The goal is to reduce deferred probes to a minimum, as it makes it very
Hi,
On 07/29/2015 02:57 PM, Vladimir Barinov wrote:
Support triggered events.
This is useful for chips that don't have their own interrupt sources.
It allows to use generic/standalone iio triggers for those drivers.
Thanks for the patch. Can you describe in more detail how
Hi Shawn,
On 6 August 2015 at 08:44, Shawn Lin shawn@rock-chips.com wrote:
DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these
On 6 August 2015 at 08:46, Shawn Lin shawn@rock-chips.com wrote:
DesignWare MMC Controller's transfer mode should be decided
at runtime instead of compile-time. So we remove this config
option and read dw_mmc's register to select DMA master.
Signed-off-by: Shawn Lin
[+cc jingooh...@gmail.com]
On 2015/8/6 16:09, Zhou Wang wrote:
This patchset adds PCIe host support for HiSilicon SoC Hip05. The PCIe hosts
use PCIe IP core from Synopsys, So this driver is base on designware PCIe
driver.
Hip05 is an ARMv8 architecture SoC. It should be able to use ARM64
[+cc jingooh...@gmail.com]
On 2015/8/6 16:09, Zhou Wang wrote:
From: gabriele paoloni gabriele.paol...@huawei.com
Commit f4c55c5a3f7f PCI: designware: Program ATU with untranslated
address added the calculation of PCI BUS addresses in designware,
storing them in new fields added in struct
[+cc jingooh...@gmail.com]
On 2015/8/6 16:09, Zhou Wang wrote:
From: gabriele paoloni gabriele.paol...@huawei.com
Commit f4c55c5a3f7f PCI: designware: Program ATU with untranslated
address added the calculation of PCI BUS addresses in designware,
storing them in new fields added in struct
[+cc jingooh...@gmail.com]
On 2015/8/6 16:09, Zhou Wang wrote:
From: gabriele paoloni gabriele.paol...@huawei.com
This patch is needed in order to unify the PCIe designware framework for ARM
and
ARM64 architectures. In the PCIe designware unification process we are calling
[+cc jingooh...@gmail.com]
On 2015/8/6 16:09, Zhou Wang wrote:
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init.
In past, we use:
i.MX6UL can be powered off by programming SNVS.
When long press ON/OFF button(5 seconds),
PMIC_ON_REQ pin will be set to low and external
PMIC will be powered off.
And system can be powered on by long press ON/OFF
button again.
Signed-off-by: Anson Huang b20...@freescale.com
---
[+cc jingooh...@gmail.com]
On 2015/8/6 16:09, Zhou Wang wrote:
This patchset adds PCIe host support for HiSilicon SoC Hip05. The PCIe hosts
use PCIe IP core from Synopsys, So this driver is base on designware PCIe
driver.
Hip05 is an ARMv8 architecture SoC. It should be able to use ARM64
[+cc jingooh...@gmail.com]
On 2015/8/6 16:09, Zhou Wang wrote:
This patch adds PCIe host support for HiSilicon SoC Hip05.
Signed-off-by: Zhou Wang wangzh...@hisilicon.com
---
drivers/pci/host/Kconfig | 8 ++
drivers/pci/host/Makefile| 1 +
drivers/pci/host/pcie-hisi.c | 254
[+cc jingooh...@gmail.com]
On 2015/8/6 16:09, Zhou Wang wrote:
This patch adds related DTS binding document for HiSilicon PCIe host driver.
Signed-off-by: Zhou Wang wangzh...@hisilicon.com
---
.../devicetree/bindings/pci/hisilicon-pcie.txt | 46
++
1 file
[+cc jingooh...@gmail.com]
On 2015/8/6 16:09, Zhou Wang wrote:
Signed-off-by: Zhou Wang wangzh...@hisilicon.com
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8133cef..7cd8e47 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@
On 6 August 2015 at 22:19, Rob Herring robherri...@gmail.com wrote:
On Thu, Aug 6, 2015 at 9:11 AM, Tomeu Vizoso tomeu.viz...@collabora.com
wrote:
Delay matches of platform devices with OF nodes until late_initcall,
when we are sure that all built-in drivers have been registered already.
On 6 August 2015 at 23:33, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Aug 06, 2015 at 06:14:00PM +0200, Geert Uytterhoeven wrote:
On Thu, Aug 6, 2015 at 3:51 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Aug 06, 2015 at 05:55:23PM +0530, Vignesh R
Am Donnerstag, den 06.08.2015, 20:36 +0100 schrieb Srinivas Kandagatla:
Hi Philipp,
Could you add Greg KH in the CC, for next merge window, we can request
Greg to take this driver via his tree.
Once the comments are fixed you can add my
Acked-by: Srinivas Kandagatla
The OMAP GPMC module has certain registers dedicated for NAND
access and some NAND bits mixed with other GPMC functionality.
For the NAND dedicated registers we have the struct gpmc_nand_regs.
The NAND driver needs to access NAND specific bits from the
following non-dedicated registers
1)
This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
This patch adds the Altera PCIe host controller driver.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
drivers/pci/host/Kconfig | 7 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera.c | 532 +
3 files changed, 540
Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory
Signed-off-by: Ley Foon Tan lf...@altera.com
---
arch/arm/include/asm/Kbuild | 1 +
1 file changed, 1 insertion(+)
This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
drivers/pci/host/Kconfig | 8 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera-msi.c |
This is the 3rd version of patch set to add support for Altera PCIe host
controller with MSI feature on Altera FPGA device families. This patchset
mainly resolve comments from Marc Zyngier in v2.
It is based on patch series from Marc Zyngier Per-device MSI domain
platform MSI [1] to get rid of
On Fri, Aug 7, 2015 at 10:20 AM, James Liao jamesjj.l...@mediatek.com wrote:
Hi Sascha,
On Thu, 2015-08-06 at 12:20 +0200, Sascha Hauer wrote:
On Thu, Aug 06, 2015 at 05:13:21PM +0800, Daniel Kurtz wrote:
On Thu, Aug 6, 2015 at 5:00 PM, James Liao jamesjj.l...@mediatek.com
wrote:
Hi
On Wed, Aug 05, 2015 at 06:38:42PM +0800, Haibo Chen wrote:
Currently we find that if a usdhc is choosed to boot system, then ROM
code will set the burst length enable bit of this usdhc as 0.
This will make performance drop a lot if this usdhc's burst length is
configed. So this patch set
After setting ahb burst configuration as 0, we can increase tx/rx
burst size, it will improve the USB performance
Signed-off-by: Peter Chen peter.c...@freescale.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 4
arch/arm/boot/dts/imx6sl.dtsi | 3 +++
arch/arm/boot/dts/imx6sx.dtsi | 3 +++
3
On 05/08/15 17:18, Kishon Vijay Abraham I wrote:
Hi Roger,
On Wednesday 05 August 2015 01:55 PM, Roger Quadros wrote:
On 05/08/15 11:23, Roger Quadros wrote:
On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off
The system bus and chipidea IP have different limitations for
both host and device mode.
For example, with below errata, we need to enable SDIS(Stream Disable
Mode) at host mode. But we don't want it for device mode at the
same system.
TAR 9000378958
Title: Non-Double Word Aligned Buffer Address
It is used to override the default setting for burst size, changing
burst size takes effect only when the SBUSCFG.AHBBRST = 0.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 10 ++
1 file changed, 10 insertions(+)
diff
It can improve the USB performance when choosing larger
burst size at some systems (bus size is larger), there is
no side effect if this burst size is larger than bus size.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 8
Stream mode enable is known for better performance, this stream mode
enable patch has been passed with stress tests at device mode for
imx6sl and imx6sx, and no issue is found.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/chipidea/ci_hdrc_imx.c | 16 ++--
1 file
The user can adjust it through dts or platform data
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/chipidea/bits.h | 4
drivers/usb/chipidea/ci.h| 1 +
drivers/usb/chipidea/core.c | 35 +++
include/linux/usb/chipidea.h | 4
4
With this setting and AHBBRST at SBUSCFG as Incremental burst of
unspecified length, each non-burst size can be taken as single
transfer. It is benefit for non-burst size transfer.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/chipidea/usbmisc_imx.c | 12 ++--
1 file
The users can change it through dts or platform data if they
want to change the default value.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/chipidea/bits.h | 3 +++
drivers/usb/chipidea/core.c | 14 ++
include/linux/usb/chipidea.h | 2 ++
3 files changed, 19
On 08/07/2015 01:08 PM, Michal Suchanek wrote:
Now since the description is clearer it's obvious that ti-qspi cannot
work fully mmapped as fsl-qspi does because the setup has to be done
over normal spi access and using non-m25p80 devices on the same bus is
a requirement.
The place where
On 07/08/15 08:46, Philipp Zabel wrote:
Nobody. I had initially copied the code that actually senses the fuses,
but since this happens during power-on reset anyway (all values are
stored in shadow registers), I didn't see the point and dropped it for
now.
The shadow registers are clocked
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.
The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 122
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/mtd/nand/omap2.c | 26 ++
1 file changed,
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
TODO: For now only dra7-evm and omap3-beagle are fixed.
Once series is reviewed I'll update this patch to
fix all omap boards.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts
This series are based on 4.2-rc1 and provide three patches to add mediatek spi
driver.
Change in v5:
1. add changelogs in the individual patches.
2. modify clk relevant implement.
3. describe dt-binding document in more detail.
Change in v4:
1. fix Mark Brown review comment.
Change in v3:
1.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
Change in this patch:
1. change this patch title.
2. change MTK SPI device to MTK SPI controller.
3. pad-select is a vendor property, so change it to mediatek,pad-select.
4. modify the property of clock and clock name.
5. explain what the
Manage NAND interrupts here using the GPMC IRQ ops.
This causes performance in prefetch-irq mode to be increased
from
[ 38.252811] mtd_speedtest: eraseblock write speed is 5576 KiB/s
[ 39.265259] mtd_speedtest: eraseblock read speed is 8192 KiB/s
to
[ 35.666446] mtd_speedtest: eraseblock
On 6 August 2015 at 22:14, Rob Herring robherri...@gmail.com wrote:
On Thu, Aug 6, 2015 at 9:11 AM, Tomeu Vizoso tomeu.viz...@collabora.com
wrote:
Hello,
I have a problem with the panel on my Tegra Chromebook taking longer
than expected to be ready during boot (Stéphane Marchesin reported
This patch adds MT8173 spi bus controllers into device tree.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
Change in this patch:
1. pad-select is a vendor property, so change it to mediatek,pad-select.
2. modify the property of clocks and clock-names.
---
This patch adds basic spi bus for MT8173.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
Change in this patch:
1. change pad-select to mediatek,pad-select.
2. modify clk relevant implement.
---
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1
Signed-off-by: Ley Foon Tan lf...@altera.com
---
MAINTAINERS | 16
1 file changed, 16 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fd60784..32f5287 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7759,6 +7759,14 @@ F: include/linux/pci*
F: arch/x86/pci/
This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
.../devicetree/bindings/pci/altera-pcie-msi.txt| 27
.../devicetree/bindings/pci/altera-pcie.txt| 49 ++
2
On Fri, Aug 7, 2015 at 4:05 PM, Daniel Kurtz djku...@chromium.org wrote:
On Fri, Aug 7, 2015 at 10:20 AM, James Liao jamesjj.l...@mediatek.com wrote:
Hi Sascha,
On Thu, 2015-08-06 at 12:20 +0200, Sascha Hauer wrote:
On Thu, Aug 06, 2015 at 05:13:21PM +0800, Daniel Kurtz wrote:
On Thu, Aug
On Thursday 06 August 2015 03:21 PM, Tony Lindgren wrote:
* Alexandre Belloni alexandre.bell...@free-electrons.com [150806 02:50]:
On 06/08/2015 at 12:36:54 +0300, Grygorii Strashko wrote :
Pls, correct me if I'm not right. Is below what you propose?
Doard dts:
/ {
rtc_32k_ext_clk:
On 8/6/2015 23:33, Russell King - ARM Linux wrote:
On Thu, Aug 06, 2015 at 06:14:00PM +0200, Geert Uytterhoeven wrote:
Irrespective of the dummy bytes.
What if the spi device is not a FLASH ROM, but some other device,
which receives a data packet that accidentally looks like an m25p80 READ
If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git
We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.
Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: Roger Quadros rog...@ti.com
---
omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: Roger Quadros rog...@ti.com
---
.../bindings/{bus/ti-gpmc.txt = memory-controllers/omap-gpmc.txt}| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename
Add device_timings, gpmc_timings and gpmc_setting to
gpmc platform data.
Signed-off-by: Roger Quadros rog...@ti.com
---
include/linux/omap-gpmc.h | 134 --
include/linux/platform_data/gpmc-omap.h | 139
2 files changed,
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros rog...@ti.com
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30
As there could be more thermal zones on a system and
more variety in thermal governors provided in kernel,
this patch provides flexibility of governor selection
for a thermal zone declared in device tree.
Change-Id: Ie4a75d762709cbbe9f1806dae325d13f71982e78
Signed-off-by: Chung-yih Wang
2015-08-07 16:09 GMT+09:00 Chung-Yih Wang (王崇懿) cyw...@chromium.org:
As there could be more thermal zones on a system and
more variety in thermal governors provided in kernel,
this patch provides flexibility of governor selection
for a thermal zone declared in device tree.
How is this a
On Wed, Aug 05, 2015 at 06:38:37PM +0800, Haibo Chen wrote:
The imx7d usdhc is derived from imx6sx, the difference is that
imx7d support HS400.
So introduce a new compatible string for imx7d and add HS400
support for imx7d usdhc.
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
On Wed, Aug 05, 2015 at 06:38:38PM +0800, Haibo Chen wrote:
tuning-step is the delay cell steps in tuning procedure. The default value
of tuning-step is 1. Some boards or cards need another value to pass the
tuning procedure. For example, imx7d-sdb board need the tuning-step value
as 2,
It is used to change ahb burst configuration for platforms, it is
vendor specific.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git
The zero-length packet is the sendor tells the receiver that there
is no more data, so it is only needed at the TX side.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/chipidea/udc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi all,
In this series, I add several new interfaces for chipidea driver,
they are mainly for system configuration adjustment. The USB
performance may be improved with these configuration changing,
but each vendor driver owner needs to consult with your IC
owner which configuration parameters are
Hi,
We do a couple of things in this series which result in
cleaner device tree implementation, faster perfomance and
multi-platform support. As an added bonus we get new GPI/Interrupt pins
for use in the system.
- Establish a custom interface between NAND and GPMC driver. This is
needed because
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/mtd/nand/omap2.c | 29 +---
The WAIT pins support falling edge interrupts so add irqchip
support to the gpiochip model.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 111 +
1 file changed, 111 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c
GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.
They must use gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 2 +-
Provide functions to enable/disable NAND IRQs, get
NAND event status and clear NAND events.
The NAND events of interest are TERMCOUNT and FIFOEVENT.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 50 ++
NAND IRQs will now be managed directly in the OMAP NAND driver
so remove the IRQchip model.
Another patch will add back GPIO-IRQchip code to handle the
WAITPIN interrupts.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/gpmc-nand.c | 4 +-
drivers/memory/omap-gpmc.c |
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops-nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/mtd/nand/omap2.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
Deprecate nand register passing via platform data and use
gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/gpmc-nand.c | 2 --
drivers/mtd/nand/omap2.c | 9 -
include/linux/platform_data/mtd-nand-omap2.h
On 29/07/15 23:55, Stephen Boyd wrote:
On 07/28/2015 05:53 AM, Srinivas Kandagatla wrote:
+
+sdcc4_pwrseq:pwrseq {
Missing space here between label and node name.
I will fix this in next version.
+compatible = mmc-pwrseq-simple;
+reset-gpios = pm8921_gpio
On Fri, Aug 07, 2015 at 05:53:01PM +0800, Chen Haibo-B51421 wrote:
-Original Message-
From: Dong Aisheng [mailto:aisheng.d...@freescale.com]
Sent: Friday, August 07, 2015 3:39 PM
To: Chen Haibo-B51421
Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
On 29/07/15 23:46, Stephen Boyd wrote:
On 07/28/2015 05:54 AM, Srinivas Kandagatla wrote:
+
+panel_3p3v: panel_3p3v {
+compatible = regulator-fixed;
+pinctrl-0 = disp_en_gpios;
+pinctrl-names = default;
+regulator-min-microvolt =
This driver handles the i.MX On-Chip OTP Controller found in
i.MX6Q/D, i.MX6S/DL, i.MX6SL, and i.MX6SX SoCs. Currently it
just returns the values stored in the shadow registers.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
Acked-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
This patch documents the i.MX6 OCOTP device tree binding.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings/nvmem/imx-ocotp.txt | 20
1 file changed, 20 insertions(+)
create mode 100644
Hi,
These patches add support for the i.MX On-Chip OTP (eFuse) Controller found
in i.MX6Q/D, i.MX6S/DL, i.MX6SL, and i.MX6SX SoCs to the NVMEM framework.
Greg, could you take them into the char-misc tree together with the NVMEM
framework?
Changes since v1:
- Dropped unneeded clk.h include
-
On 08/06/2015 01:22 PM, Govindraj Raja wrote:
From: Ezequiel Garcia ezequiel.gar...@imgtec.com
The Pistachio SoC provides four general purpose timers, and allow
to implement a clocksource driver.
This driver can be used as a replacement for the MIPS GIC and MIPS R4K
clocksources and sched
hi,
On Fri, 2015-07-31 at 14:45 +0100, Mark Rutland wrote:
Hi,
Sorry for my late reply to a prior version of this series, but I still
have concerns with some of the properties.
I'll repeat those below.
On Fri, Jul 31, 2015 at 02:03:53PM +0100, Chunfeng Yun wrote:
add a DT binding
On 06/08/15 17:21, Geert Uytterhoeven wrote:
Hi Sudeep,
On Wed, Aug 5, 2015 at 12:58 PM, Sudeep Holla sudeep.ho...@arm.com wrote:
On 05/08/15 11:44, Geert Uytterhoeven wrote:
On Wed, Aug 5, 2015 at 11:34 AM, Sudeep Holla sudeep.ho...@arm.com
wrote:
[..]
Any particular reason whey you
On Fri, Aug 07, 2015 at 08:09:39AM +0100, Chung-Yih Wang (王崇懿) wrote:
As there could be more thermal zones on a system and
more variety in thermal governors provided in kernel,
this patch provides flexibility of governor selection
for a thermal zone declared in device tree.
Change-Id:
On Wed, 2015-08-05 at 23:31 +0100, Russell King - ARM Linux wrote:
On Wed, Aug 05, 2015 at 08:44:11PM +0200, Matthias Brugger wrote:
On Tuesday, July 14, 2015 01:18:26 PM Yingjoe Chen wrote:
This series add SMP brinup support for MediaTek SoCs. This is based
on v4.2-rc1 and Matthias' next
On 08/06/2015 03:17 AM, Wenyou Yang wrote:
The compatible atmel,sama5d4-wdt supports the SAMA5D4 watchdog driver
and the watchdog's WDT_MR register can be written more than once.
Signed-off-by: Wenyou Yang wenyou.y...@atmel.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
---
From: Ezequiel Garcia ezequiel.gar...@imgtec.com
The Pistachio SoC provides four general purpose timers, and allow
to implement a clocksource driver.
This driver can be used as a replacement for the MIPS GIC and MIPS R4K
clocksources and sched clocks, which are clocked from the CPU clock.
Given
Hi Daniel,
-Original Message-
From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org]
Sent: 07 August 2015 11:28 AM
To: Govindraj Raja; linux-ker...@vger.kernel.org; linux-m...@linux-mips.org;
devicetree@vger.kernel.org
Cc: Thomas Gleixner; Andrew Bresticker; James Hartley; Damien
We've everything we need to support the gmac on Colombus, turn it on.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31-colombus.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts
The Auxtek-T003 HDMI stick is an A10s based HDMI stick with USB wifi,
and composite video out support.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 159 +++
2
On 08/06/2015 03:16 AM, Wenyou Yang wrote:
From SAMA5D4, the watchdog timer is upgrated with a new feature,
which is describled as in the datasheet, WDT_MR can be written
until a LOCKMR command is issued in WDT_CR.
That is to say, as long as the bootstrap and u-boot don't issue
a LOCKMR
Hi Lars,
On 07.08.2015 16:45, Lars-Peter Clausen wrote:
Hi,
On 07/29/2015 02:57 PM, Vladimir Barinov wrote:
Support triggered events.
This is useful for chips that don't have their own interrupt sources.
It allows to use generic/standalone iio triggers for those drivers.
Thanks for the
On Fri, Aug 7, 2015 at 9:18 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Thanks Kevin,
On 07/08/15 17:13, Kevin Hilman wrote:
Srinivas Kandagatla srinivas.kandaga...@linaro.org writes:
This patchset adds a new simple NVMEM framework to kernel, and it is
tested
with
Hi Peter,
On Friday 07 August 2015 05:18 PM, Peter Robinson wrote:
On Wed, Aug 5, 2015 at 11:00 AM, Tony Lindgren t...@atomide.com wrote:
* Grygorii Strashko grygorii.stras...@ti.com [150729 02:01]:
On 07/27/2015 03:16 PM, Kishon Vijay Abraham I wrote:
pbias device creation got broken once
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