Instead of having each i2c driver individually parse device tree data in
case it or platform supports separate wakeup interrupt, and handle
enabling and disabling wakeup interrupts in their power management
routines, let's have i2c core do that for us.
Platforms wishing to specify separate wakeup
Hi Krzysztof,
On Monday 17 August 2015 11:20 AM, Krzysztof Kozlowski wrote:
2015-05-02 14:49 GMT+09:00 Krzysztof Kozlowski :
W dniu 28.04.2015 o 20:02, Pankaj Dubey pisze:
Hi Kukjin,
Any updated for this patch. Without this PMIC RTC is not working on
SMDK5250.
Could you resend the patch af
Dear Ganapatrao,
On Fri, 14 Aug 2015 22:09:34 +0530
Ganapatrao Kulkarni wrote:
> adding dt file for Cavium's Thunder SoC in 2 Node topology
> using arm,associativity device node property.
>
> Signed-off-by: Ganapatrao Kulkarni
> ---
> arch/arm64/boot/dts/cavium/Makefile | 2 +-
>
Hi Krzysztof,
On Monday 17 August 2015 11:20 AM, Krzysztof Kozlowski wrote:
2015-05-02 14:49 GMT+09:00 Krzysztof Kozlowski :
W dniu 28.04.2015 o 20:02, Pankaj Dubey pisze:
Hi Kukjin,
Any updated for this patch. Without this PMIC RTC is not working on
SMDK5250.
Could you resend the patch af
Ho Marek,
> On Aug 17, 2015, at 9:48 PM, Marek Vasut wrote:
>
>> On Tuesday, August 18, 2015 at 04:35:55 AM, vikas wrote:
>> Hi Marek,
>>
>>> On 08/13/2015 08:28 PM, Marek Vasut wrote:
>>> From: Graham Moore
>>>
>>> Add binding document for the Cadence QSPI controller.
>>>
>>> Signed-off-b
On Tuesday, August 18, 2015 at 04:35:55 AM, vikas wrote:
> Hi Marek,
>
> On 08/13/2015 08:28 PM, Marek Vasut wrote:
> > From: Graham Moore
> >
> > Add binding document for the Cadence QSPI controller.
> >
> > Signed-off-by: Graham Moore
> > Signed-off-by: Marek Vasut
> > Cc: Alan Tull
> > Cc
On Fri, Aug 14, 2015 at 05:32:34AM +0200, Marek Vasut wrote:
> On Friday, August 14, 2015 at 05:28:12 AM, Marek Vasut wrote:
>
> > + /* Get flash device data */
> > + for_each_available_child_of_node(dev->of_node, np) {
...
> --->8---
>
> > + /*
> > +* Here is a 'nasty h
On Mon, 2015-08-17 at 15:23 +0200, Thierry Reding wrote:
> On Mon, Jul 20, 2015 at 04:17:16PM +0800, YH Huang wrote:
> > Add display PWM driver support to modify backlight for MT8173 and MT6595.
> > The PWM has one channel to control the brightness of the display.
> > When the (high_width / period)
Hi Marek,
On 08/13/2015 08:28 PM, Marek Vasut wrote:
> From: Graham Moore
>
> Add binding document for the Cadence QSPI controller.
>
> Signed-off-by: Graham Moore
> Signed-off-by: Marek Vasut
> Cc: Alan Tull
> Cc: Brian Norris
> Cc: David Woodhouse
> Cc: Dinh Nguyen
> Cc: Graham Moore
>
Hi Marek,
On 08/13/2015 08:28 PM, Marek Vasut wrote:
> From: Graham Moore
>
> Add support for the Cadence QSPI controller. This controller is
> present in the Altera SoCFPGA SoCs and this driver has been tested
> on the Cyclone V SoC.
>
> Signed-off-by: Graham Moore
> Signed-off-by: Marek Vasu
On Sun, Aug 16, 2015 at 1:24 AM, Jonathan Cameron wrote:
> On 12/08/15 07:01, Matt Ranostay wrote:
>> Add support for the PulsedLight LIDAR rangefinder sensor which allows
>> high speed (over 300Hz) distance measurements using Barker Coding within
>> 40 meter range.
>>
>> Support only tested on th
On Mon, 2015-08-17 at 15:23 +0200, Thierry Reding wrote:
> On Mon, Jul 20, 2015 at 04:17:15PM +0800, YH Huang wrote:
> > Document the device-tree binding of MediatTek display PWM.
>
> I already mentioned this a while back: s/MediatTek/MediaTek/.
>
Sorry, I will correct it to "MediaTek".
Regards,
Hi Thierry,
(2015/08/17 23:15), Thierry Reding wrote:
> Sorry for taking an awful long time to get around to this. The driver
> looks generally okay, but I have a few minor comments...
Thank you for the review!
> On Mon, Jun 15, 2015 at 06:08:44PM +0900, Yoshihiro Shimoda wrote:
>> This patch ad
On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote:
> I'm not very helpful here, so hopefully Viet can be of more use:
Yup :)
> On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote:
> > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote:
> > Also, I cannot find any d
I'm not very helpful here, so hopefully Viet can be of more use:
On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote:
> On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote:
> Also, I cannot find any documentation for this IP block even if I search
> through
> Quartus/QSys, is t
Quoting Geert Uytterhoeven (2015-08-04 05:34:06)
> On Tue, Aug 4, 2015 at 2:22 PM, Laurent Pinchart
> wrote:
> > On Monday 03 August 2015 01:53:23 Kuninori Morimoto wrote:
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> >> @@ -0,0 +1,93 @@
> >> +/ {
>
> >> + clocks {
Hi Kenneth,
just small minor question.
On Fri, Aug 14, 2015 at 1:30 PM, Kenneth Lee wrote:
> HNAE (Hisilicon Network Acceleration Engine) is a framework to provide a
> unified ring buffer interface for Hisilicon Network Acceleration Engines.
>
> With the interface, upper layer can work as ethern
Quoting Pi-Cheng Chen (2015-08-17 01:56:45)
> From: "pi-cheng.chen"
>
> This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
> for intermediate clock source switching.
>
> Signed-off-by: Pi-Cheng Chen
> Reviewed-by: Daniel Kurtz
Looks OK to me. Can I expect an mtk clk pull
On QCOM platforms using MTD devices storage (such as IPQ806x), SMEM is
used to store partition layout. This new parser can now be used to read
SMEM and use it to register an MTD layout according to its content.
Signed-off-by: Mathieu Olivari
---
Notes:
v2:
*Release the SPI device referen
QCOM platforms such as IPQ806x are using SMEM to store their flash
layout. This patch set adds the DT nodes required to instanciate SMEM
on IPQ806x and add an MTD parser using it.
This change is based on the SMEM driver posted here:
*https://lkml.org/lkml/2015/7/27/1125
v2:
*Release the SPI devic
Add one new node to the ipq806x.dtsi file to declare & register the
hardware spinlock devices. This mechanism is required to be used by
other drivers such as SMEM.
Signed-off-by: Mathieu Olivari
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --gi
SMEM is used on IPQ806x to store various board related information such
as boot device and flash partition layout. We'll declare it as a device
so we can make use of it thanks to the new SMEM soc driver.
Signed-off-by: Mathieu Olivari
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++-
1 file
On 8/14/2015 12:31 PM, Mark Brown wrote:
On Mon, Aug 03, 2015 at 12:59:48AM -0600, Sagar Dharia wrote:
+/**
+ * Qualcomm slimbus controller may experience interference on the lines
+ * causing some early messages (e.g. logical-address assignment) to be
+ * NACKed. Retry after sometime (typicall
Hi Mark,
On 8/14/2015 12:39 PM, Mark Brown wrote:
On Mon, Aug 03, 2015 at 12:59:49AM -0600, Sagar Dharia wrote:
@@ -459,6 +459,8 @@ int slim_register_controller(struct slim_controller *ctrl)
mutex_init(&ctrl->m_ctrl);
spin_lock_init(&ctrl->tx.lock);
spin_lock_init(&ctrl
Hi Ulf,
On 2015/8/12 13:07, Michal Simek wrote:
+linux-mmc
On 08/11/2015 04:53 PM, Michal Simek wrote:
On 08/11/2015 09:46 AM, Shawn Lin wrote:
This patch adds the compatible string in sdhci-of-arasan.c to
support sdhci-arasan5.1 version of controller. No documented
controller IP version is f
On Fri, Aug 14, 2015 at 10:48:17PM -0700, Bjorn Andersson wrote:
> On Fri 14 Aug 17:46 PDT 2015, Mathieu Olivari wrote:
>
> > On QCOM platforms using MTD devices storage (such as IPQ806x), SMEM is
> > used to store partition layout. This new parser can now be used to read
> > SMEM and use it to re
On 17/08/15 19:48, Andrew Lunn wrote:
>> TLC591xx is quite simple HW, and the code doing the HW programming
>> should be identical for a pwm and for a led driver. I don't see either a
>> pwm or a led driver being somehow superior. They are very similar simple
>> drivers, implementing a different
On 17 August 2015 at 22:18, Ezequiel Garcia
wrote:
> On 16 Aug 08:10 PM, Joachim Eastwood wrote:
> [..]
>> +
>> +static int 2(struct lpc2k_i2c *i2c)
>> +{
>> + unsigned long timeout = jiffies + msecs_to_jiffies(1000);
>> +
>> + /*1
>> + * If the transfer needs to abort for some reason
On 16 Aug 08:10 PM, Joachim Eastwood wrote:
[..]
> +
> +static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c)
> +{
> + unsigned long timeout = jiffies + msecs_to_jiffies(1000);
> +
> + /*
> + * If the transfer needs to abort for some reason, we'll try to
> + * force a stop conditi
From: Kenneth Lee
Date: Fri, 14 Aug 2015 18:30:19 +0800
> diff --git a/drivers/net/ethernet/hisilicon/hns/hnae.c
> b/drivers/net/ethernet/hisilicon/hns/hnae.c
> new file mode 100644
> index 000..fd09768
> --- /dev/null
> +++ b/drivers/net/ethernet/hisilicon/hns/hnae.c
...
> +static inline v
On 08/17/15 21:41, Mark Brown wrote:
On Mon, Aug 17, 2015 at 10:07:55AM +0300, Jyri Sarha wrote:
On 08/14/15 19:18, Mark Brown wrote:
On Fri, Aug 14, 2015 at 12:30:41PM +0300, Jyri Sarha wrote:
+ /* Called when ASoC starts an audio stream setup. The call
+* provides an audio ab
I haven't reviewed the code in detail, just had one comment I alluded to
in a private email the other day...
On Wed, 2015-08-05 at 15:28 +0100, Liviu Dudau wrote:
> diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c
> b/drivers/gpu/drm/arm/hdlcd_crtc.c
[...]
> +void hdlcd_set_scanout(struct hdlcd_drm
Stephen Warren writes:
> On 08/12/2015 06:56 PM, Eric Anholt wrote:
>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>
>> +DRM DRIVERS FOR VC4
>> +M: Eric Anholt
>> +T: git git://github.com/anholt/linux
>> +S: Maintained
>> +F: drivers/gpu/drm/vc4/*
>
> S: Supported
Fixed.
signature.asc
Descri
On Mon, Aug 17, 2015 at 10:00:07AM +0300, Jyri Sarha wrote:
> On 08/14/15 19:10, Mark Brown wrote:
> Don't you mean "omap-hdmi-audio", that is implemented in
> sound/soc/omap/omap-hdmi-audio.c ?
> That driver is bit different. It implements ASoC card and uses generic dummy
> codec. The "hdmi-audi
On Mon, Aug 17, 2015 at 10:07:55AM +0300, Jyri Sarha wrote:
> On 08/14/15 19:18, Mark Brown wrote:
> >On Fri, Aug 14, 2015 at 12:30:41PM +0300, Jyri Sarha wrote:
> >>+ /* Called when ASoC starts an audio stream setup. The call
> >>+* provides an audio abort callback for stoping an ongoing
>
Stephen Warren writes:
> On 08/12/2015 06:56 PM, Eric Anholt wrote:
>> We need to use it for getting video modes over HDMI.
>
>> diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
>
>> +i2c2: i2c@7e805000 {
>> +compatible = "brcm,bcm2835-i
Stephen Warren writes:
> On 08/12/2015 06:56 PM, Eric Anholt wrote:
>> Signed-off-by: Eric Anholt
>
> This one definitely needs a patch description, since someone might not
> know what a VC4 is, and "git log" won't show the text from the binding
> doc itself. I'd suggest adding the initial parag
r<#secure method=pgpmime mode=sign>
Stephen Warren writes:
> On 08/12/2015 06:56 PM, Eric Anholt wrote:
>> This is the start of a full VC4 driver. Right now this just supports
>> configuring the display using a pre-existing video mode (because
>> changing the pixel clock isn't available yet, and
On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote:
Hi!
[...]
> > Hi Brian,
> > It is really unfortunate that this controller is not able to read full
> > JEDEC ID. It only can provide 1 byte ID. I did discuss with IP
> > designer about this, but it is really unfortunate that they are
I apologize to ignore this email, since Jacek is taking over the
maintainership of LED subsystem. Please include him in the email
thread.
Thanks,
-Bryan
On Mon, Aug 17, 2015 at 9:48 AM, Andrew Lunn wrote:
>> TLC591xx is quite simple HW, and the code doing the HW programming
>> should be identica
> TLC591xx is quite simple HW, and the code doing the HW programming
> should be identical for a pwm and for a led driver. I don't see either a
> pwm or a led driver being somehow superior. They are very similar simple
> drivers, implementing a different interface. Whether the interface works
> for
On 17/08/15 17:21, Andrew Lunn wrote:
>>> If you think your PWM code is so much better, please submit a revert
>>> patch plus your PWM LED driver. We can find somebody to do a side by
>>> side review.
>>
>> It's not about the driver code. That can be cleaned up if needed. The
>> question is wheth
On Mon, Jul 27, 2015 at 03:10:23PM +0800, Viet Nga Dao wrote:
> On Sat, Jul 25, 2015 at 2:37 AM, Brian Norris
> wrote:
> > On Wed, Jun 03, 2015 at 12:30:44AM -0700, vn...@altera.com wrote:
> >> From: VIET NGA DAO
> >>
> >> Altera Quad SPI Controller is a soft IP which enables access to
> >> Alter
Hi Timo,
On Tue, Aug 04, 2015 at 11:08:01PM +0200, Timo Sigurdsson wrote:
> sun7i-a20.dtsi contains a cpufreq operating point at 0.9 volts. The minimum
> CPU voltage for the Allwinner A20 SoC, however, is 1.0 volts. Thus, raise
> the voltage for the lowest operating point to 1.0 volts in order to
On Sun, Aug 16, 2015 at 09:56:33AM +0100, Emil Velikov wrote:
> Hi Liviu,
Hi Emil,
>
> On 5 August 2015 at 15:28, Liviu Dudau wrote:
> > The HDLCD controller is a display controller that supports resolutions
> > up to 4096x4096 pixels. It is present on various development boards
> > produced by
Hi
On 07.08.2015 15:30, Chunfeng Yun wrote:
MTK xhci host controller defines some extra SW scheduling
parameters for HW to minimize the scheduling effort for
synchronous and interrupt endpoints. The parameters are
put into reseved DWs of slot context and endpoint context
...
+ * The TD siz
Em Thu, 30 Jul 2015 18:08:55 +0100
Peter Griffin escreveu:
> This patch adds in the required DT node for the c8sectpfe
> Linux DVB demux driver which allows the tsin channels
> to be used on an upstream kernel.
>
> Signed-off-by: Peter Griffin
> ---
> arch/arm/boot/dts/stihxxx-b2120.dtsi | 38
On Thu, Aug 06, 2015 at 05:55:57PM -0700, Florian Fainelli wrote:
> Add a binding documentation for the Broadcom BCM7038 PWM controller found in
> BCM7xxx chips.
>
> Signed-off-by: Florian Fainelli
> ---
> .../devicetree/bindings/pwm/brcm,bcm7038-pwm.txt | 22
> ++
> 1 fil
> > Hi Tomi
> >
> > Our discussions were going around in circles, no progress being made.
> > The subsystem maintainer is ultimately the one who needs to decide,
> > bar Linus himself. Bryan Wu has seen all the discussions, and
> > ultimately decided the driver was O.K, despite any unresolved issu
ATTENTION
Your Webmail has almost exceeded quota limit,
Login Below to confirm Webmail activity in our Database and
authenticate the validity of your Webmail Usage to increase your quota
to avoid temporal interruption and loss of files in your Webmail system.
Click Here To Validate Log
Sorry for taking an awful long time to get around to this. The driver
looks generally okay, but I have a few minor comments...
On Mon, Jun 15, 2015 at 06:08:44PM +0900, Yoshihiro Shimoda wrote:
> This patch adds support for R-Car SoCs PWM Timer.
This could be a little more verbose. You could say
On 17/08/15 16:27, Andrew Lunn wrote:
> On Mon, Aug 17, 2015 at 03:11:48PM +0300, Tomi Valkeinen wrote:
>> Hi Andrew, (and Brian),
(Sorry for typoing your name, Bryan =).
>> On 18/03/15 00:08, Andrew Lunn wrote:
>>> This patchset is a driver for the TI tlc59116 16 Channel i2c LED
>>> driver and
On Thu, 2015-08-13 at 10:35 +0200, Daniel Lezcano wrote:
> On 07/22/2015 10:14 AM, Yingjoe Chen wrote:
> > Spurious mtk timer interrupt is noticed at boot and cause kernel
> > crash. It seems if GPT is enabled, it will latch irq status even
> > when its IRQ is disabled. When irq is enabled afterwar
On Mon, Aug 17, 2015 at 03:11:48PM +0300, Tomi Valkeinen wrote:
> Hi Andrew, (and Brian),
>
> On 18/03/15 00:08, Andrew Lunn wrote:
> > This patchset is a driver for the TI tlc59116 16 Channel i2c LED
> > driver and tlc59108 8 Channel i2c LED driver. This driver is used on
> > the Belkin WRT1900AC
On Mon, Jul 20, 2015 at 04:17:15PM +0800, YH Huang wrote:
> Document the device-tree binding of MediatTek display PWM.
I already mentioned this a while back: s/MediatTek/MediaTek/.
Thierry
signature.asc
Description: PGP signature
On Mon, Jul 20, 2015 at 04:17:16PM +0800, YH Huang wrote:
> Add display PWM driver support to modify backlight for MT8173 and MT6595.
> The PWM has one channel to control the brightness of the display.
> When the (high_width / period) is closer to 1, the screen is brighter;
> otherwise, it is darke
On 08/17/15 10:57, Jyri Sarha wrote:
Missed one commet first time around...
On 08/14/15 19:18, Mark Brown wrote:
On Fri, Aug 14, 2015 at 12:30:41PM +0300, Jyri Sarha wrote:
...
+/* HDMI codec initalization data */
+struct hdmi_codec_pdata {
+struct device *dev; /* The HDMI encoder registe
On 12/08/15 23:21, Stefan Wahren wrote:
This patch adds the devicetree bindings for the Freescale MXS On Chip
OTP driver.
Signed-off-by: Stefan Wahren
Acked-by: Srinivas Kandagatla
---
.../devicetree/bindings/nvmem/mxs-ocotp.txt| 25
1 file changed, 25 i
On 12/08/15 23:21, Stefan Wahren wrote:
This patch brings read-only support for the On-Chip OTP cells
in the i.MX23 and i.MX28 processor. The driver implements the
new NVMEM provider API.
Signed-off-by: Stefan Wahren
Reviewed-by: Marek Vasut
---
drivers/nvmem/Kconfig | 11 ++
driver
On 15/08/15 08:21, Stefan Wahren wrote:
Hi Srinivas,
Srinivas Kandagatla hat am 11. August 2015 um
13:03 geschrieben:
This patch adds perm variable to nvmem_config structure which will allow
providers to specify the permissions required for the sysfs binary file.
This permission is applied
Hi Andrew, (and Brian),
On 18/03/15 00:08, Andrew Lunn wrote:
> This patchset is a driver for the TI tlc59116 16 Channel i2c LED
> driver and tlc59108 8 Channel i2c LED driver. This driver is used on
> the Belkin WRT1900AC access point and the C code is derived from code
> Belkin contributed to Op
On Mon, Aug 17, 2015 at 05:08:55PM +0530, Keerthy wrote:
>
>
> On Monday 17 August 2015 05:00 PM, Johan Hovold wrote:
> > On Mon, Aug 17, 2015 at 10:25:38AM +0530, Keerthy wrote:
> >> Configure the clock source to either internal clock
> >> or external clock based on the availability of the clock
On Thu 2015-08-13 12:37:29, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Add a document spelling out usage of the simple fpga bus.
>
> Signed-off-by: Alan Tull
Acked-by: Pavel Machek
Pavel
--
(englis
On Thu 2015-08-13 12:37:27, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> API to support programming FPGA.
I'd do s/fpga/FPGA/ in the comments, too. Otherwise looks ok to me.
Acked-by: Pavel Machek
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atr
On Thu 2015-08-13 12:37:32, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Add simple fpga bus. This is a bus that configures an fpga and its
> bridges before populating the devices below it. This is intended
> for use with device tree overlays.
>
> Note that FPGA bridges are seen as
On Thu 2015-08-13 12:37:30, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> New bindings document for simple fpga bus.
>
> Signed-off-by: Alan Tull
Acked-by: Pavel Machek
> + onchip_memory2_0: memory@0x0 {
> + d
Signed-off-by: Zhou Wang
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8133cef..7cd8e47 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7854,6 +7854,13 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/xgene-pci-msi.tx
This patch adds PCIe host support for HiSilicon SoC Hip05.
Signed-off-by: Zhou Wang
---
drivers/pci/host/Kconfig | 8 ++
drivers/pci/host/Makefile| 1 +
drivers/pci/host/pcie-hisi.c | 254 +++
3 files changed, 263 insertions(+)
create mode 100
From: gabriele paoloni
This patch is needed in order to unify the PCIe designware framework for ARM and
ARM64 architectures. In the PCIe designware unification process we are calling
pci_create_root_bus() passing a "sysdata" parameter that is the same for both
ARM and ARM64 and is of type "struct
From: gabriele paoloni
Commit f4c55c5a3f7f "PCI: designware: Program ATU with untranslated
address" added the calculation of PCI BUS addresses in designware,
storing them in new fields added in "struct pcie_port". This
calculation is done for every designware user even if is only
applicable to DR
This patchset adds PCIe host support for HiSilicon SoC Hip05. The PCIe hosts
use PCIe IP core from Synopsys, So this driver is base on designware PCIe
driver.
Hip05 is an ARMv8 architecture SoC. It should be able to use ARM64 PCIe API in
designeware PCIe driver. So this patch also adds ARM64 supp
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init.
In past, we use:
pci_common_init_dev
-> pcibios_init_hw
-> hw->scan (dw_pci
This patch adds related DTS binding document for HiSilicon PCIe host driver.
Signed-off-by: Zhou Wang
---
.../devicetree/bindings/pci/hisilicon-pcie.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
On Monday 17 August 2015 05:00 PM, Johan Hovold wrote:
On Mon, Aug 17, 2015 at 10:25:38AM +0530, Keerthy wrote:
Configure the clock source to either internal clock
or external clock based on the availability of the clocks.
External clock is preferred as it can be ticking during suspend.
Signe
On 12 August 2015 at 10:24, Chaotian Jing wrote:
> Schedule a workqueue to do tuning when CRC error
> Call mmc_hw_reset to re-init card when data timeout
Thanks to Adrian Hunter, the mmc core already supports re-tuning for
the above scenarios through the mmc_retune_*() APIs.
SDHCI driver has alr
On Mon, Aug 17, 2015 at 10:25:38AM +0530, Keerthy wrote:
> Configure the clock source to either internal clock
> or external clock based on the availability of the clocks.
> External clock is preferred as it can be ticking during suspend.
>
> Signed-off-by: Keerthy
> ---
>
> Changes in V2:
>
>
Mediatek MT8173 is an ARMv8 based quad-core (2*Cortex-A53 and
2*Cortex-A72) SoC with duall clusters. For each cluster, two voltage
inputs, Vproc and Vsram are supplied by two regulators. For the big
cluster, two regulators come from different PMICs. In this case, when
scaling voltage inputs of the
This patch adds the required properties in device tree to enable MT8173
cpufreq driver.
Signed-off-by: Pi-Cheng Chen
Acked-by: Viresh Kumar
---
It is based on the top of MT8173 SoC maintainer's tree:
https://github.com/mbgg/linux-mediatek.git v4.2-next/arm64
commit id: e26945245e414eff42ee1ffeae
Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
"include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory"
Signed-off-by: Ley Foon Tan
---
arch/arm/include/asm/Kbuild | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/
This patch adds the Altera PCIe host controller driver.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/Kconfig | 7 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera.c | 543 +
3 files changed, 551 insertions(+)
create mode
MT8173 is a ARMv8 based SoC with 2 clusters. All CPUs in a single cluster
share the same power and clock domain. This series tries to add cpufreq support
for MT8173 SoC. The v6 of this series is resent with Acks added.
changes in v6:
- Move clock and regulator consumer properties document to the d
This patch adds the clock and regulator consumer properties part of
document for CPU DVFS clocks on Mediatek MT8173 SoC.
Signed-off-by: Pi-Cheng Chen
Acked-by: Michael Turquette
Acked-by: Viresh Kumar
---
.../devicetree/bindings/clock/mt8173-cpu-dvfs.txt | 83 ++
1 file ch
Thanks, Arnd,
You are right. This is the same IP as hip04_mdio.c. We just mis-understand the
hardware design. We will merge them and re-submit the patches.
On Fri, Aug 14, 2015 at 10:57:28PM +0200, Arnd Bergmann wrote:
> On Friday 14 August 2015 18:30:20 Kenneth Lee wrote:
>
> > +#define MDIO_B
On Fri, Jun 27, 2014 at 11:18 AM, Linus Walleij
wrote:
> On Tue, Jun 24, 2014 at 4:46 PM, Denis Carikli wrote:
>> + irq_set_chip_and_handler(irq, &dummy_irq_chip,
>> +handle_level_irq);
>> + set_irq_flags(irq, IRQF_VALID);
>
> This function only exists
This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.
Signed-off-by: Ley Foon Tan
---
drivers/pci/host/Kconfig | 8 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera-msi.c | 322 +++
This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.
Signed-off-by: Ley Foon Tan
---
.../devicetree/bindings/pci/altera-pcie-msi.txt| 27
.../devicetree/bindings/pci/altera-pcie.txt| 49 ++
2 files changed, 7
Signed-off-by: Ley Foon Tan
---
MAINTAINERS | 16
1 file changed, 16 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fd60784..32f5287 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7759,6 +7759,14 @@ F: include/linux/pci*
F: arch/x86/pci/
F: arch/x86/k
This is the 4th version of patch set to add support for Altera PCIe host
controller with MSI feature on Altera FPGA device families. This patchset
mainly resolve comments from Marc Zyngier in v3.
It is based on patch series from Marc Zyngier "Per-device MSI domain &
platform MSI" [1] to get rid of
On Fri, Aug 14, 2015 at 09:26:21PM +0100, Bjorn Helgaas wrote:
> On Fri, Aug 14, 2015 at 11:43 AM, Will Deacon wrote:
> > On Fri, Aug 14, 2015 at 05:40:51PM +0100, Bjorn Helgaas wrote:
> >> Do we need support for pci-probe-only in pci-host-generic at all?
> >> You're removing the use in amd-overdr
From: "pi-cheng.chen"
This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
for intermediate clock source switching.
Signed-off-by: Pi-Cheng Chen
Reviewed-by: Daniel Kurtz
---
Changes in v5:
- Replace __initdata with __initconst to fix compiling error
Changes in v4:
- Fix s
Missed one commet first time around...
On 08/14/15 19:18, Mark Brown wrote:
On Fri, Aug 14, 2015 at 12:30:41PM +0300, Jyri Sarha wrote:
...
+/* HDMI codec initalization data */
+struct hdmi_codec_pdata {
+ struct device *dev; /* The HDMI encoder registering the codec */
Shouldn't this
From: Jason Jin
In u-boot, when set the video as console, the name 'vga' is used
as a general name for the video device, during the fdt_fixup_stdout
process, the 'vga' name is used to search in the dtb to setup the
'linux,stdout-path' node. Though the P1022 DIU is not VGA-compatible
device, to me
Hi Bjorn,
To be honest I'm wainting that Zhou patch (PCI: designware: Add ARM64
support) is accepted.
Because this patch allows to remove "pci: designware: remove
pci_common_init_dev()" from my patchset. I think it's more judicious
to do that.
I can send a v4 based on Zhou patchset ([PATCH v6 0/
On Fri, Aug 14, 2015 at 7:45 PM, Ian Lepore wrote:
> On Fri, 2015-08-14 at 09:27 -0500, Rob Herring wrote:
>> Ian:
>> > So if I want to write a FreeBSD i2c eeprom driver that uses DT data,
>> > what are my choices? I have exactly one: make my driver essentially a
>> > clone of the Linux driver,
On Mon, 17 Aug 2015, Barry Song wrote:
> 2015-07-22 21:04 GMT+08:00 Lee Jones :
> > Lots of platforms contain clocks which if turned off would prove fatal.
> > The only way to recover from these catastrophic failures is to restart
> > the board(s). Now, when a clock provider is registered with th
On 08/14/15 13:06, Russell King - ARM Linux wrote:
On Fri, Aug 14, 2015 at 12:30:44PM +0300, Jyri Sarha wrote:
+static int tda998x_write_aif(struct tda998x_priv *priv,
+struct hdmi_audio_infoframe *cea)
+{
+ uint8_t buf[HDMI_INFOFRAME_SIZE(AUDIO)];
+ int l
On 08/14/15 19:18, Mark Brown wrote:
On Fri, Aug 14, 2015 at 12:30:41PM +0300, Jyri Sarha wrote:
+struct hdmi_codec_ops {
+ /* For runtime clock configuration from ASoC machine driver.
+* A direct forward from set_sysclk in struct snd_soc_dai_ops.
+* Optional */
+ in
On 08/14/15 19:10, Mark Brown wrote:
On Fri, Aug 14, 2015 at 12:30:40PM +0300, Jyri Sarha wrote:
The hdmi stub codec has not been used since refactoring of OMAP HDMI
audio support.
grep tells me that the OMAP HDMI4 and HDMI5 drivers are still
registering this device in -next...
Really? My s
98 matches
Mail list logo
