On 2015. 8. 20., at PM 3:23, Yakir Yang wrote:
>
> Hi Jingoo & Archit,
>
>
>> On 08/20/2015 12:54 AM, Jingoo Han wrote:
>>> On 2015. 8. 20., at PM 1:29, Archit Taneja wrote:
>>> Hi,
>>>
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller
Hi Vinod,
On Thu, Aug 20, 2015 at 11:10 AM, Vinod Koul wrote:
> On Thu, Jul 30, 2015 at 05:41:06PM +0530, Rameshwar Prasad Sahu wrote:
>> + /* Invalidate unused source address field */
>> + for (; i < 4; i++)
>> + xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i));
>
Hi Maintainers,
On Fri, Aug 14, 2015 at 10:14 PM, Ganapatrao Kulkarni
wrote:
> On Fri, Aug 14, 2015 at 10:09 PM, Ganapatrao Kulkarni
> wrote:
>> v5:
>> - created base verion of numa.c which creates dummy numa without
>> using dt
>> on single socket platforms. Then added patch
On Fri, Aug 14, 2015 at 04:44:37PM +0200, Hans de Goede wrote:
> The gt90h is a pcb found in generic 9" tablets with an A23 soc, 1G RAM
> and 8G nand, rtl8723as usb wifi, 1 micro usb port and 1 micro sd slot.
>
> This commit adds a dts for v4 of the gt90h pcb.
>
> Signed-off-by: Hans de Goede
A
On Fri, Aug 14, 2015 at 04:44:35PM +0200, Hans de Goede wrote:
> From: Jelle van der Waa
>
> Enable the otg/drc usb controller on the pcDuino 3.
>
> Note this board has the otg-vbus connected directly to the 5v-dcc of
> the board, so there is no vbus0 regulator, nor vbus0-det.
Can it do OTG the
On Fri, Aug 14, 2015 at 04:44:34PM +0200, Hans de Goede wrote:
> From: Jelle van der Waa
>
> Add regulator configuration to the pcduino3 dts file.
>
> Signed-off-by: Jelle van der Waa
> Signed-off-by: Hans de Goede
Queued, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Ker
Hi,
On Fri, Aug 14, 2015 at 04:44:32PM +0200, Hans de Goede wrote:
> Add a simplefb node for tvencoder / composite-video output, such as found
> on the Auxtek-T003 and the CHIP.
>
> Signed-off-by: Hans de Goede
Queued, thanks!
I guess the CHIP will have to have the same change for the A13 DTS
Hi,
On Thursday 06 August 2015 02:17 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I [150805 07:10]:
>> On Wednesday 05 August 2015 01:31 PM, Tony Lindgren wrote:
>>>
>>> We don't have syscon-otghs and to me it seems we need a PHY driver
>>> as I pointed out at:
>>
>> If *syscon-otghs* is not
On Thu, Aug 20, 2015 at 11:43 AM, Vinod Koul wrote:
> On Thu, Aug 06, 2015 at 08:49:33AM +0530, Punnaiah Choudary Kalluri wrote:
>
>> + list_for_each_entry_safe(desc, next, &chan->done_list, node) {
>> + dma_async_tx_callback callback;
>> + void *callback_param;
>> +
>>
Hi Vinod,
On Thu, Aug 20, 2015 at 10:56 AM, Vinod Koul wrote:
> On Thu, Jul 30, 2015 at 05:41:05PM +0530, Rameshwar Prasad Sahu wrote:
>> This patch adds support for new feature CRC32C calculation in
>> dmaengine framework.
>
> Looks okay can you please update Documentation also
Thanks, I will u
This patch adds support for R-Car generation 3 USB2 PHY driver.
This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
with the HSUSB (USB2.0 peripheral) device.
So, the purpose of this driver is:
1) initializes some registers of SoC specific to use the
{ehci,ohci}-platform driver.
On Tue, Jul 21, 2015 at 06:44:39PM +0530, Rameshwar Prasad Sahu wrote:
> This patch adds ACPI support for the APM X-Gene DMA engine driver.
Applied, thanks
--
~Vinod
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Mo
Hi Jingoo & Archit,
On 08/20/2015 12:54 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 1:29, Archit Taneja wrote:
Hi,
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used
Hi,
On 08/19/2015 05:17 PM, Maxime Ripard wrote:
On Fri, Aug 07, 2015 at 05:22:34PM +0200, Hans de Goede wrote:
We've everything we need to support the gmac on Colombus, turn it on.
Signed-off-by: Hans de Goede
I recall that the phy was powered by one of the AXP221 regulators,
does it requi
On 08/20/2015 08:18 AM, Vinod Koul wrote:
> On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote:
+- interrupts: Should contain DMA channel interrupt
>>> channel interrupt or interrupts, former says it is plural
>>
>> ZynqMP DMA has single interrupt for each channel So, th
On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote:
> >> +- interrupts: Should contain DMA channel interrupt
> > channel interrupt or interrupts, former says it is plural
>
> ZynqMP DMA has single interrupt for each channel So, that is the reason
> i have explicitly mentione
On Thu, Aug 20, 2015 at 11:22 AM, Vinod Koul wrote:
> On Thu, Aug 06, 2015 at 08:49:32AM +0530, Punnaiah Choudary Kalluri wrote:
>> Device-tree binding documentation for Xilinx zynqmp dma engine used in
>> Zynq UltraScale+ MPSoC.
>>
>> Signed-off-by: Punnaiah Choudary Kalluri
>> ---
>> Changes in
On 2015. 8. 19., at PM 11:52, Yakir Yang wrote:
>
> Some edp screen with no hpd signal would need some delay time
> to ensure that screen would be ready for work, so we can expand
> the delay time in hpd detect function, it works prefectly on my
> rk3288 sdk board.
Then, this delay has a depende
On Thu, Aug 06, 2015 at 08:49:33AM +0530, Punnaiah Choudary Kalluri wrote:
> + list_for_each_entry_safe(desc, next, &chan->done_list, node) {
> + dma_async_tx_callback callback;
> + void *callback_param;
> +
> + list_del(&desc->node);
> +
> + cal
On 2015. 8. 20., at PM 1:29, Archit Taneja wrote:
>
> Hi,
>
>> On 08/19/2015 08:18 PM, Yakir Yang wrote:
>>
>> Hi all,
>>The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I split the common
>> code into bridge direct
On Thu, Aug 06, 2015 at 08:49:32AM +0530, Punnaiah Choudary Kalluri wrote:
> Device-tree binding documentation for Xilinx zynqmp dma engine used in
> Zynq UltraScale+ MPSoC.
>
> Signed-off-by: Punnaiah Choudary Kalluri
> ---
> Changes in v4:
> - None
> Changes in v3:
> - None
> Changes in v2:
> -
On 2015/8/20 10:53, Leo Yan wrote:
Add driver for Hi6220 mailbox, the mailbox communicates with MCU; for
sending data, it can support two methods for low level implementation:
one is to use interrupt as acknowledge, another is automatic mode which
without any acknowledge. These two methods have b
On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
> + nents = sg_nents(req->src);
> + sg_count = dma_map_sg(dev, req->src, nents, DMA_TO_DEVICE);
> + if (!sg_count) {
> + dev_err(dev, "Failed to map src sg");
> + return -ENOMEM;
mapping error
On Thu, Jul 30, 2015 at 05:41:06PM +0530, Rameshwar Prasad Sahu wrote:
> + /* Invalidate unused source address field */
> + for (; i < 4; i++)
> + xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i));
> +
> + /* Check whether requested buffer processed */
> + if
On Tuesday, August 18, 2015 at 10:18:33 PM, vikas wrote:
> Hi,
>
> On 08/18/2015 12:03 PM, Graham Moore wrote:
> > Hi all,
> >
> > On 08/18/2015 12:48 AM, Vikas MANOCHA wrote:
> >
> > [...]
> >
> > +Required properties:
> > +- compatible : Should be "cdns,qspi-nor".
> > +- reg : Con
On Thu, Jul 30, 2015 at 05:41:05PM +0530, Rameshwar Prasad Sahu wrote:
> This patch adds support for new feature CRC32C calculation in
> dmaengine framework.
Looks okay can you please update Documentation also
--
~Vinod
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Hi,
On Wednesday 19 August 2015 08:21 PM, Yakir Yang wrote:
> Signed-off-by: Yakir Yang
where's the commit message?
> ---
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
> collect the phy clocks and power control.
>
> Changes in v2: None
>
> .../devicetree/bindings/phy/
Hi,
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I
Add driver for Hi6220 mailbox, the mailbox communicates with MCU; for
sending data, it can support two methods for low level implementation:
one is to use interrupt as acknowledge, another is automatic mode which
without any acknowledge. These two methods have been supported in the
driver. For rece
Hi6220 mailbox supports up to 32 channels. Each channel is unidirectional
with a maximum message size of 8 words. I/O is performed using register
access (there is no DMA) and the cell raises an interrupt when messages
are received.
This patch series is to implement Hi6220 mailbox driver. It regist
Document the new compatible for Hisilicon Hi6220 mailbox driver.
Signed-off-by: Leo Yan
---
.../bindings/mailbox/hisilicon,hi6220-mailbox.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/hisilicon,hi6220-mailbox.txt
On Hi6220, below memory regions in DDR have specific purpose:
0x05e0, - 0x05ef,: For MCU firmware using at runtime;
0x0740,f000 - 0x0740,: For MCU firmware's section;
0x06df,f000 - 0x06df,: For mailbox message data.
This patch reserves these memory regions and add device nod
On Thu, Aug 20, 2015 at 12:32 AM, Mark Brown wrote:
> On Wed, Aug 19, 2015 at 12:20:01PM +0800, Chen-Yu Tsai wrote:
>> Hi everyone,
>>
>> This is my third attempt at adding support for Allwinner's Reduced
>> Serial Bus (RSB), which is used to communicate with PMICs and other
>> peripherals on thei
Hi Dave,
On 08/19/2015 06:54 PM, Dave Airlie wrote:
On 20 August 2015 at 00:48, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and
On Wed, Aug 19, 2015 at 07:44:10PM +0200, Lars-Peter Clausen wrote:
> On 08/19/2015 07:12 PM, Vinod Koul wrote:
> > On Tue, Jul 28, 2015 at 11:38:06AM +0200, Lars-Peter Clausen wrote:
> >>> where is device side programming ?
> >>
> >> in the start_transfer() function.
> >
> > I must have missed th
On 20 August 2015 at 00:48, Yakir Yang wrote:
>
> Hi all,
>The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code.
Hello Brian,
On Thu, Aug 20, 2015 at 12:18 AM, Brian Norris wrote:
> When getting translated from a downstream device tree that used slightly
> different DT bindings, these regulators got labeled with the
> "on-in-suspend" state, when they were actually supposed to be turned off
> for S3 suspend.
Hello Brian,
On Thu, Aug 20, 2015 at 12:18 AM, Brian Norris wrote:
> This DTS file was submitted with non-upstream bindings. I happened
> across this while reviewing the jaq DTS.
>
> Signed-off-by: Brian Norris
> Cc: Alexandru M Stan
> Cc: Douglas Anderson
> ---
> Did not test minnie
>
> v1 ->
Hello Brian,
[...]
> +
> +&rk808 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
> + dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
> + <&gpio7 15 GPIO_ACTIVE_HIGH>;
I see the dvs-gpios DT property is documented in the downstream
Chrom
On Wed, Aug 19, 2015 at 03:38:43PM -0700, Alexandru Stan wrote:
> On Wed, Aug 19, 2015 at 3:18 PM, Brian Norris
> wrote:
>
> > +++ b/Documentation/devicetree/bindings/arm/rockchip.txt
>
> ...
>
> > +- Google Jaq (Haier Chromebook 11):
>
>
> Could you add s/)/ and more)/ similar to what Jerry
Define the SILK board dependent part of the VIN0 device node.
Add the device node for Analog Devices ADV7180 video decoder to I2C1 bus.
Add the necessary subnodes to interconnect VIN0 and ADV7180 devices.
Based on the Henninger VIN0/ADV8170 device tree patch by myself.
Signed-off-by: Sergei
Define the generic R8A7794 part of the VIN[01] device nodes. Add aliases for
the VIN[01] device nodes.
Signed-off-by: Sergei Shtylyov
---
arch/arm/boot/dts/r8a7794.dtsi | 20
1 file changed, 20 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7794.dtsi
Hello.
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20150819-v4.2-rc7' tag. Here we add the VIN and ADV7180
video decoder device tree support on the R8A7794/SILK board. The patchset
requires previously posted SILK SD
When getting translated from a downstream device tree that used slightly
different DT bindings, these regulators got labeled with the
"on-in-suspend" state, when they were actually supposed to be turned off
for S3 suspend. This was harmless, but not intentional, AFAICT.
Let's turn them off to get
This DTS file was submitted with non-upstream bindings. I happened
across this while reviewing the jaq DTS.
Signed-off-by: Brian Norris
Cc: Alexandru M Stan
Cc: Douglas Anderson
---
Did not test minnie
v1 -> v2:
- use "off-in-suspend", as that's the equivalent to the downstream
'regulator-
a.k.a. Haier Chromebook 11
Signed-off-by: Brian Norris
Cc: Alexandru M Stan
Cc: Douglas Anderson
---
v1 -> v2:
- add overlooked DT binding doc
- fixup regulator suspend state for LDO_REG2
Documentation/devicetree/bindings/arm/rockchip.txt | 7 +
arch/arm/boot/dts/Makefile
On 08/20/2015 12:57 AM, Sergei Shtylyov wrote:
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20150819-v4.2-rc7' tag. Here we add the I2C device tree support
for the R8A7794/SILK board.
[1/2] ARM: shmobile: r8
Define the SILK board dependent part of the I2C1 device node.
Signed-off-by: Sergei Shtylyov
---
arch/arm/boot/dts/r8a7794-silk.dts | 13 +
1 file changed, 13 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7794-silk.dts
=
Define the generic R8A7794 parts of the I2C[0-5] device nodes.
Based on the original patch by Koji Matsuoka .
Signed-off-by: Sergei Shtylyov
---
arch/arm/boot/dts/r8a7794.dtsi | 73 +
1 file changed, 73 insertions(+)
Index: renesas/arch/arm/boot/dts/r
Hello.
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20150819-v4.2-rc7' tag. Here we add the I2C device tree support
for the R8A7794/SILK board.
[1/2] ARM: shmobile: r8a7794: add I2C DT support
[2/2] ARM: shmob
Hi Eric,
only a few nits.
Am 18.08.2015 um 23:54 schrieb Eric Anholt:
This is the start of a full VC4 driver. Right now this just supports
configuring the display using a pre-existing video mode (because
changing the pixel clock isn't available yet, and doesn't work when it
is). However, this
On Wed, Aug 19, 2015 at 03:52:55PM -0500, Pledge Roy-R01356 wrote:
> Sorry for digging up an old thread here Scott, but we never did close on this
> discussion. See my replies inline below
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Tuesday, May 12, 2015 6:46 PM
>
Hello,
On Wednesday 19 August 2015 09:49:28 Geert Uytterhoeven wrote:
> On Tue, Aug 18, 2015 at 2:20 AM, Michael Turquette wrote:
> > Quoting Geert Uytterhoeven (2015-08-04 05:34:06)
> >> On Tue, Aug 4, 2015 at 2:22 PM, Laurent Pinchart wrote:
> >>> On Monday 03 August 2015 01:53:23 Kuninori Morim
Sorry for digging up an old thread here Scott, but we never did close on this
discussion. See my replies inline below
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, May 12, 2015 6:46 PM
> To: Pledge Roy-R01356
> Cc: linuxppc-...@lists.ozlabs.org; devicetree@vger.kern
Hi Eric,
Am 18.08.2015 um 23:54 schrieb Eric Anholt:
VC4 is the GPU (display and 3D) subsystem present on the 2835 and some
other Broadcom SoCs.
This binding follows the model of msm, imx, sti, and others, where
there is a subsystem node for the whole GPU, with nodes for the
individual HW compo
From: David Daney
If the internal call to of_address_to_resource() fails, we end up
looping forever in of_find_matching_node_by_address(). This can be
caused by a defective device tree, or calling with an incorrect
matches argument.
Fix by calling of_find_matching_node() unconditionally at the
Acked-by: Moritz Fischer
On Wed, Aug 19, 2015 at 11:28 AM, atull wrote:
> On Mon, 17 Aug 2015, Pavel Machek wrote:
>
>> On Thu 2015-08-13 12:37:29, at...@opensource.altera.com wrote:
>> > From: Alan Tull
>> >
>> > Add a document spelling out usage of the simple fpga bus.
>> >
>> > Signed-off-by
On Mon, 17 Aug 2015, Pavel Machek wrote:
> On Thu 2015-08-13 12:37:29, at...@opensource.altera.com wrote:
> > From: Alan Tull
> >
> > Add a document spelling out usage of the simple fpga bus.
> >
> > Signed-off-by: Alan Tull
>
> Acked-by: Pavel Machek
>
On Wed, Aug 12, 2015 at 01:44:22PM -0500, Michael Welling wrote:
> On Wed, Aug 12, 2015 at 11:56:36AM +0530, Vignesh R wrote:
> > Hi Michael,
> >
> > + Dmitry
> >
> > On 08/12/2015 12:15 AM, Michael Welling wrote:
> > > Adds a device tree parameter to set the open delay on the touchscreen
> > > c
Ethernet switch on AP148 is connected through MDIO using GPIO 0 and 1.
We'll add the new node using the bitbang driver on these two pins.
Signed-off-by: Mathieu Olivari
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++-
1 file changed, 30 insertions(+), 1 deletion
This change adds GMAC nodes to IPQ806x platforms, both to the dtsi and
to the AP148 dts. This will provide ethernet connectivity to the device.
Signed-off-by: Mathieu Olivari
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 33
arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 +++
On 08/19/2015 07:12 PM, Vinod Koul wrote:
> On Tue, Jul 28, 2015 at 11:38:06AM +0200, Lars-Peter Clausen wrote:
>> +static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
>> +{
>> +struct axi_dmac *dmac = chan_to_axi_dmac(chan);
>> +struct virt_dma_desc *vdesc;
>> +struct axi_d
On Wed, Aug 19, 2015 at 11:37:58AM +0800, Leilk Liu wrote:
> TX_ENDIAN/RX_ENDIAN bits define whether to reverse the endian
> order of the data DMA from/to memory. The endian order should
> keep the same with cpu endian.
This doesn't apply, probably because it depends on your stylistic
changes patc
On Tue, Jul 28, 2015 at 11:38:06AM +0200, Lars-Peter Clausen wrote:
> +static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
> +{
> + struct axi_dmac *dmac = chan_to_axi_dmac(chan);
> + struct virt_dma_desc *vdesc;
> + struct axi_dmac_desc *desc;
> + struct axi_dmac_sg *sg
On 08/19/2015 06:32 PM, Vinod Koul wrote:
> On Tue, Jul 28, 2015 at 11:38:06AM +0200, Lars-Peter Clausen wrote:
>> +active = axi_dmac_active_desc(chan);
>> +if (!active)
>> +return;
>> +
>> +if (active->cyclic) {
>> +vchan_cyclic_callback(&active->vdesc);
>> +
On Wed, Aug 19, 2015 at 09:40:25AM +0100, Jens Wiklander wrote:
> Adds helpers to do SMC based on ARM SMC Calling Convention.
> CONFIG_HAVE_SMCCC is enabled for architectures that may support
> the SMC instruction. It's the responsibility of the caller to
> know if the SMC instruction is supported
From: Marcus Cooper
The A20-SOM-EVB is a reference design of a 2-layer board for the
A20-SOM.
It expands the features of A20-SOM by adding VGA connector, HDMI
connector, audio In/Out, LCD connector, 2 Mpix camera, gigabit
Ethernet, SATA, USB-OTG and 2 USB hosts.
This patch adds basic support for
On Wed, Aug 19, 2015 at 12:20:01PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This is my third attempt at adding support for Allwinner's Reduced
> Serial Bus (RSB), which is used to communicate with PMICs and other
> peripherals on their newer SoCs, such as the A23/A33/A80.
This is flagged as
On Tue 18 Aug 14:04 PDT 2015, Mathieu Olivari wrote:
> On QCOM platforms using MTD devices storage (such as IPQ806x), SMEM is
> used to store partition layout. This new parser can now be used to read
> SMEM and use it to register an MTD layout according to its content.
>
Still looks good, but yo
On Tue 18 Aug 14:04 PDT 2015, Mathieu Olivari wrote:
> SMEM is used on IPQ806x to store various board related information such
> as boot device and flash partition layout. We'll declare it as a device
> so we can make use of it thanks to the new SMEM soc driver.
>
Reviewed-by: Bjorn Andersson
On Tue 18 Aug 14:04 PDT 2015, Mathieu Olivari wrote:
> Add one new node to the ipq806x.dtsi file to declare & register the
> hardware spinlock devices. This mechanism is required to be used by
> other drivers such as SMEM.
>
Still looks good, but you should have added:
Reviewed-by: Bjorn Anders
Hi Lucas
First of all many thanks for the quick reply, really appreciated
> -Original Message-
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Wednesday, August 19, 2015 4:37 PM
> To: Gabriele Paoloni
> Cc: Wangzhou (B); Bjorn Helgaas; jingooh...@gmail.com; Pratyush Anand;
> A
On Tue, Jul 28, 2015 at 11:38:06AM +0200, Lars-Peter Clausen wrote:
> + active = axi_dmac_active_desc(chan);
> + if (!active)
> + return;
> +
> + if (active->cyclic) {
> + vchan_cyclic_callback(&active->vdesc);
> + } else {
> + while (active &&
do
On Wed, Jul 08, 2015 at 05:11:24PM +0100, Peter Griffin wrote:
> +static int
> +st_fdma_elf_sanity_check(struct st_fdma_dev *fdev, const struct firmware *fw)
> +{
> + const char *fw_name = fdev->pdata->fw_name;
> + struct elf32_hdr *ehdr;
> + char class;
> +
> + if (!fw) {
> +
Hi Gab,
Am Mittwoch, den 19.08.2015, 15:16 + schrieb Gabriele Paoloni:
> Hi Lucas
>
> I have rewritten the patch to take into account multiple controllers.
>
> As you can see now there is a static var in dw_pcie_host_init() that tracks
> the bus numbers used.
This is wrong. The DT specifies
On 19 August 2015 at 17:18, Wolfram Sang wrote:
> On Sun, Aug 16, 2015 at 08:10:15PM +0200, Joachim Eastwood wrote:
>> This patch set adds a I2C driver and documentation for the I2C
>> peripheral found on many NXP LPC MCUs.
>>
>> The driver is a rework of an old driver by Kevin Wells. It has been
On Wed, Aug 19, 2015 at 11:17 PM, Maxime Ripard
wrote:
> On Fri, Aug 07, 2015 at 05:22:34PM +0200, Hans de Goede wrote:
>> We've everything we need to support the gmac on Colombus, turn it on.
>>
>> Signed-off-by: Hans de Goede
>
> I recall that the phy was powered by one of the AXP221 regulators
2015-08-19 2:52 GMT-07:00 Thierry Reding :
> On Thu, Aug 06, 2015 at 05:55:58PM -0700, Florian Fainelli wrote:
>> Add support for the BCM7038-style PWM controller found in all BCM7xxx STB
>> SoCs.
>> This controller has a hardcoded 2 channels per controller, and cascades a
>> variable frequency ge
On Sun, Aug 16, 2015 at 08:10:15PM +0200, Joachim Eastwood wrote:
> This patch set adds a I2C driver and documentation for the I2C
> peripheral found on many NXP LPC MCUs.
>
> The driver is a rework of an old driver by Kevin Wells. It has been
> modified to support modern resource allocation, devi
On Fri, Aug 07, 2015 at 05:22:34PM +0200, Hans de Goede wrote:
> We've everything we need to support the gmac on Colombus, turn it on.
>
> Signed-off-by: Hans de Goede
I recall that the phy was powered by one of the AXP221 regulators,
does it require some additional stuff (like a recent u-boot),
Hi Lucas
I have rewritten the patch to take into account multiple controllers.
As you can see now there is a static var in dw_pcie_host_init() that tracks
the bus numbers used.
Drivers that do not specify the bus range in the DTB set pp->root_bus_nr =
DW_ROOT_NR_UNDEFINED.
Designware will check
On Fri, Aug 07, 2015 at 05:22:35PM +0200, Hans de Goede wrote:
> The Colombus development kit uses an optional 2048x1536 edp panel using
> an anx9804 parallel lcd to edp convertor. The anx9804 chip is controlled
> via an i2c bus which is connected to 2 regular gpio pins.
>
> Signed-off-by: Hans de
On Wed, Jul 08, 2015 at 05:11:22PM +0100, Peter Griffin wrote:
> This patch adds the DT binding documentation for the FDMA constroller
> found on STi based chipsets from STMicroelectronics.
>
> Signed-off-by: Ludovic Barre
> Signed-off-by: Peter Griffin
> ---
> Documentation/devicetree/bindings
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Add "analogix,need-force-
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Take Jingoo Han sugge
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Heiko suggest
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
dp phy driver which na
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76 -
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Add edid modes parse support
Changes in v2: None
drivers/gpu/drm/
Signed-off-by: Yakir Yang
---
Changes in v3:
- move dp hpd detect to connector detect function.
Changes in v2: None
drivers/gpu/drm/bridge/analogix_dp_core.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix_dp_core.c
b/drivers/gpu
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/b
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Heiko suggest, add rockchip dp phy driver,
collect the phy clocks and power control.
Changes in v2: None
.../devicetree/bindings/phy/rockchip-dp-phy.txt| 26 +++
drivers/phy/Kconfig| 7 +
drivers/phy/Ma
link_rate and lane_count already configed in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.
Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbp
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h| 16 ++
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relaies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.
Signed-off-by: Yaki
Hi Dan,
On Fri, Aug 14, 2015 at 12:01:06PM +0800, Daniel Kurtz wrote:
> On Tue, Aug 11, 2015 at 12:43 PM, Daniel Kurtz wrote:
> > Hi James,
> >
> > On Mon, Aug 10, 2015 at 5:50 PM, James Liao
> > wrote:
> >> This patchset is based on 4.2-rc2 and [1], and contains minor fixes and
> >> subsystem
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
avoid using some uncommo
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
control
This particular Client implementation uses shared memory in order
to pass messages between Mailbox users; however, it can be easily
hacked to support any type of Controller.
Signed-off-by: Lee Jones
---
drivers/mailbox/Kconfig| 7 +
drivers/mailbox/Makefile | 2 +
drivers/mailb
Signed-off-by: Lee Jones
---
.../devicetree/bindings/mailbox/sti-mailbox.txt| 52 ++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
diff --git a/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt
b/Do
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