On 10.12.2015 16:44, Krzysztof Kozlowski wrote:
> On 09.12.2015 22:58, Marek Szyprowski wrote:
>> Enable support for Multimedia Codec (MFC) device for all Exynos4412-based
... and one more finding: I think the abbreviation is Multi Format Codec.
BR,
Krzysztof
>> Odroid boards.
>>
>> Signed-off-b
On 09.12.2015 22:58, Marek Szyprowski wrote:
> Enable support for Multimedia Codec (MFC) device for all Exynos4412-based
> Odroid boards.
>
> Signed-off-by: Marek Szyprowski
> ---
> arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 24
> 1 file changed, 24 insertions(+)
Hi Gregory,
On Wed, Dec 09, 2015 at 06:49:43PM +0100, Gregory CLEMENT wrote:
> With device tree it is no more possible to reset the PHY at board
> level. Furthermore, doing in the driver allow to power down the PHY when
> the network interface is no more used.
>
> The patch introduces a new optio
Hi Simon
Thank you for your patch
> Add fallback compatibility strings for R-Car Gen2 and Gen3.
> This is in keeping with the fallback scheme being adopted wherever
> appropriate for drivers for Renesas SoCs.
>
> Also add SoC names.
>
> Signed-off-by: Simon Horman
> ---
(snip)
> Required pro
On 2015년 12월 10일 15:58, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus device-tree node of INT (internal) block
>> to enable the bus frequency. The following sub-blocks share
>
> "to enable the bus frequency scaling"
>
>> the VDD_INT power source:
On 2015년 12월 10일 16:08, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> THis patch adds the bus device tree nodes for both MIF (Memory) and INT
>> (Internal) block to enable the bus frequency.
>>
>> The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
>>
On 2015년 12월 10일 16:02, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch expands the voltage range of buck1/3 regulator due to as
>> following:
>> - MIF (Memory Interface) bus frequency needs the 9uV ~ 105uV V.
>> - INT (Internal) bus frequency needs 9000
On 2015년 12월 10일 16:12, Krzysztof Kozlowski wrote:
> On 10.12.2015 16:07, Chanwoo Choi wrote:
>> On 2015년 12월 10일 15:53, Krzysztof Kozlowski wrote:
>>> On 10.12.2015 15:43, Chanwoo Choi wrote:
On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
> On 10.12.2015 15:08, Chanwoo Choi wrote:
>>>
Hi Bjorn,
On 10.12.2015 00:19, Bjorn Helgaas wrote:
> [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
> questions below)]
>
> On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote:
>> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>>
>> Signed-o
On 10.12.2015 16:07, Chanwoo Choi wrote:
> On 2015년 12월 10일 15:53, Krzysztof Kozlowski wrote:
>> On 10.12.2015 15:43, Chanwoo Choi wrote:
>>> On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
On 10.12.2015 15:08, Chanwoo Choi wrote:
> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>>>
On 09.12.2015 13:08, Chanwoo Choi wrote:
> THis patch adds the bus device tree nodes for both MIF (Memory) and INT
> (Internal) block to enable the bus frequency.
>
> The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
> bus is parent device in INT block using VDD_INT.
>
> Sig
On 2015년 12월 10일 15:53, Krzysztof Kozlowski wrote:
> On 10.12.2015 15:43, Chanwoo Choi wrote:
>> On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
>>> On 10.12.2015 15:08, Chanwoo Choi wrote:
On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>>
On Tue, Dec 08, 2015 at 06:54:10PM +0100, Geert Uytterhoeven wrote:
> Change the console alias to "serial0", for consistency with other
> boards (the first unlabeled serial port is always called "serial0").
> Add serial port config to chosen/stdout-path.
>
> Signed-off-by: Geert Uytterhoeven
> --
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch expands the voltage range of buck1/3 regulator due to as following:
> - MIF (Memory Interface) bus frequency needs the 9uV ~ 105uV V.
> - INT (Internal) bus frequency needs 9uV ~ 100uV.
9->90 and duplicated "uV V". Maybe
On Tue, Dec 08, 2015 at 06:54:05PM +0100, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> This patch series updates the console parameters in the DTSes for
> various Renesas ARM boards.
>
> - For all of them, the serial port config is added to
> chosen/stdout-path, as per current be
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus device-tree node of INT (internal) block
> to enable the bus frequency. The following sub-blocks share
"to enable the bus frequency scaling"
> the VDD_INT power source:
> - LEFTBUS (parent device)
> - RIGHTBUS
> - PERIL
> - LCD0
>
On 10.12.2015 15:43, Chanwoo Choi wrote:
> On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
>> On 10.12.2015 15:08, Chanwoo Choi wrote:
>>> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus noes using VDD_INT for Exynos4
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch add dt node for PPMU_{DMC0|DMC1|LEFTBUS|RIGHTBUS} for
> exynos4412-odroidu3 board. Each PPMU dt node includes one event of
> 'PPMU Count3'.
>
> Signed-off-by: Chanwoo Choi
> ---
> arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 40
> ++
On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
> On 10.12.2015 15:08, Chanwoo Choi wrote:
>> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>>> On 09.12.2015 13:08, Chanwoo Choi wrote:
This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
Exynos4x12 has the following AXI
On 2015/12/9 23:31, Arnd Bergmann wrote:
> On Tuesday 08 December 2015 11:54:51 xuejiancheng wrote:
>> On 2015/12/7 14:37, xuejiancheng wrote:
>>>
>>> On 2015/12/4 18:49, Arnd Bergmann wrote:
On Friday 04 December 2015 10:27:58 xuejiancheng wrote:
>>
Maybe split out the sysctrl bind
On 10.12.2015 15:08, Chanwoo Choi wrote:
> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>>> Exynos4x12 has the following AXI buses to translate data between
>>> DRAM and sub-blocks.
On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>> Exynos4x12 has the following AXI buses to translate data between
>> DRAM and sub-blocks.
>>
>> Following list specifies the detailed rel
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
> Exynos4x12 has the following AXI buses to translate data between
> DRAM and sub-blocks.
>
> Following list specifies the detailed relation between DRAM and sub-blocks:
> - ACLK100 clock for
Rk3288-evb-act8846 and rk3288-evb-rk808 are the power boards of
rk3288-evb, they provide the same power supply interface to the
motherboard. Sort out them, put the public part to rk3288-evb.dtsi,
such as gmac and cpu-supply, leaving only the power section.
Signed-off-by: Chris Zhong
---
arch/a
vcc_wl and vcc_lcd are 2 gpio switches for rk3288-evb-act8846 board.
Signed-off-by: Chris Zhong
---
arch/arm/boot/dts/rk3288-evb-act8846.dts | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts
b/arch/arm/boot/dts/rk3288
According to the schematic, the name of REG8 should be vcc_tp, rather
than vcca_tp.
Signed-off-by: Chris Zhong
---
arch/arm/boot/dts/rk3288-evb-act8846.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts
b/arch/arm/boot/dts/rk3288-ev
Hi,
this short series adds generic, and soc-specific r8a7792 and r8a7793 compat
strings to the Renesas USBHS driver. The intention is to provide a complete
set of compat strings for known R-Car SoCs.
Changes since v1:
* Add R-Car Gen2 and Gen3 fallback compatibility strings rather than
a single
Add fallback compatibility strings for R-Car Gen2 and Gen3.
This is in keeping with the fallback scheme being adopted wherever
appropriate for drivers for Renesas SoCs.
Also add SoC names.
Signed-off-by: Simon Horman
---
v2
* Add R-Car Gen2 and Gen3 fallback compatibility strings rather than
a
Simply document new compatibility string.
As a previous patch adds a generic R-Car Gen2 compatibility string
there appears to be no need for a driver updates.
Signed-off-by: Simon Horman
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 2 ++
1 file changed, 2
On 12/03/2015 03:51 PM, Vignesh R wrote:
>
>
> On 12/01/2015 10:09 PM, Tony Lindgren wrote:
>> * Vignesh R [151130 20:46]:
>>> On 12/01/2015 04:04 AM, Tony Lindgren wrote:
...
>>
>> OK. They are both on L3 main so that won't cause any issues for separate
>> interconnect driver instances.
On Tue, Dec 08, 2015 at 05:26:20AM +, Kuninori Morimoto wrote:
>
> Hi
>
> These are v4 of thermal-zone support for r8a7790/r8a7791.
> Mainly, it cares return value of get_temp()
>
> I think 8) is needed on of-thermal (?)
>
> Kuninori Morimoto (8):
> 1) thermal: rcar: move rcar_thermal
On 2015년 12월 10일 12:17, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
>
> s/noes/nodes/
OK.
>
>> Exynos4x12 has the following AXI buses to translate data
>> between DRAM and DMC/ACP/C2C.
>>
>> Signed-off-b
Hi Anand,
On 2015년 12월 10일 13:14, Anand Moon wrote:
> Hi Chanwoo Choi,
>
> On 10 December 2015 at 05:42, Chanwoo Choi wrote:
>> Hi Anand,
>>
>> First of all, thanks for trying to test this series.
>>
>> On 2015년 12월 10일 04:05, Anand Moon wrote:
>>> Hi Chanwoo Choi,
>>>
>>> On 9 December 2015 at
Hi Chanwoo Choi,
On 10 December 2015 at 05:42, Chanwoo Choi wrote:
> Hi Anand,
>
> First of all, thanks for trying to test this series.
>
> On 2015년 12월 10일 04:05, Anand Moon wrote:
>> Hi Chanwoo Choi,
>>
>> On 9 December 2015 at 09:37, Chanwoo Choi wrote:
>>> This patch-set includes the two fea
This commit implements bindings in the eeprom_93xx46 driver allowing
device word size and read-only attributes to be specified via
devicetree.
Signed-off-by: Cory Tusar
Tested-by: Chris Healy
---
drivers/misc/eeprom/eeprom_93xx46.c | 49 +
1 file changed, 49
This commit adds support to the eeprom_93x46 driver allowing a GPIO line
to function as a 'select' or 'enable' signal prior to accessing the
EEPROM.
Signed-off-by: Cory Tusar
Tested-by: Chris Healy
---
drivers/misc/eeprom/eeprom_93xx46.c | 35 +++
include/linux/e
Atmel devices in this family have some quirks not found in other similar
chips - they do not support a sequential read of the entire EEPROM
contents, and the control word sent at the start of each operation
varies in bit length.
This commit adds quirk support to the driver and modifies the read
im
This commit documents bindings to be added to the eeprom_93xx46 driver
which will allow:
- Device word size and read-only attributes to be specified.
- A device-specific compatible string for use with Atmel AT93C46D
EEPROMs.
- Specifying a GPIO line to function as a 'select' or 'enable'
This series of patches adds an initial set of devicetree bindings to the
eeprom_93xx46 driver which mirror the configuration options previously
available as a platform device. These bindings are then extended to
include support for specific Atmel devices in this family and also to
support GPIO-bas
Compatible at93xx46 devices from both Microchip and Atmel expect a
word-based address, regardless of whether the device is strapped for 8-
or 16-bit operation. However, the offset parameter passed in when
reading or writing at a specific location is always specified in terms
of bytes.
This commit
On Wed, Dec 02, 2015 at 02:53:54PM +0900, Simon Horman wrote:
> In general Renesas hardware is not documented to the extent where the
> relationship between IP blocks on different SoCs can be assumed although
> they may appear to operate the same way. Furthermore the documentation
> typically does
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
s/noes/nodes/
> Exynos4x12 has the following AXI buses to translate data
> between DRAM and DMC/ACP/C2C.
>
> Signed-off-by: Chanwoo Choi
> ---
> arch/arm/boot/dts/exynos4x12.dtsi | 72
> +
Please fix the date and time on your computer.
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On Wed, Dec 09, 2015 at 01:10:18PM +0200, Peter Ujfalusi wrote:
> Hi Arnd, Vinod,
>
> As Arnd suggested, the two patch from the following series:
> https://www.mail-archive.com/linux-omap@vger.kernel.org/msg122201.html
>
> plus Acked-by from Arnd is available for pull if you prefer that way.
Sor
On Wed, Dec 09, 2015 at 12:12:27PM -0800, Tony Lindgren wrote:
> * Peter Ujfalusi [151209 00:19]:
> > Hi,
> >
> > Based on the discussion regarding to (convert am33xx to use the new eDMA
> > bindings):
> > https://www.mail-archive.com/linux-omap@vger.kernel.org/msg122117.html
> >
> > This two pa
On Wed, 2015-12-09 at 23:52 +0100, Linus Walleij wrote:
> On Thu, Nov 26, 2015 at 9:44 AM, Biao Huang wrote:
>
> > Add mt2701 support using mediatek common pinctrl driver.
> > MT2701 have some special pins need an extra setting register
> > than other ICs, so adding this support to common code.
>
On Wed, Dec 09, 2015 at 01:01:42PM -0800, Florian Fainelli wrote:
> Le 09/12/2015 12:40, Simon Arlott a écrit :
> > Add device tree binding for NAND on the BCM6368.
> >
> > The BCM6368 has a NAND interrupt register with combined status and enable
> > registers. It also requires a clock, so add an
On 2015년 12월 10일 11:09, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
>> Exynos3250 has following AXI buses to translate data between
>> DRAM and sub-blocks.
>>
>> Following list specifies the detailed relati
On 10.12.2015 11:17, Chanwoo Choi wrote:
> On 2015년 12월 10일 11:04, Krzysztof Kozlowski wrote:
>> On 10.12.2015 11:00, Chanwoo Choi wrote:
>>> On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
On 10.12.2015 10:09, Chanwoo Choi wrote:
> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>>>
On 2015년 12월 10일 10:22, Krzysztof Kozlowski wrote:
> On 10.12.2015 09:57, Krzysztof Kozlowski wrote:
>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>
>> (...)
>>
>>> .../devicetree/bindings/devfreq/exynos-bus.txt | 383 +++
>>
>> How about adding this file to the MAINTAINERS to devfreq exyno
On 2015년 12월 10일 11:04, Krzysztof Kozlowski wrote:
> On 10.12.2015 11:00, Chanwoo Choi wrote:
>> On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
>>> On 10.12.2015 10:09, Chanwoo Choi wrote:
On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>>
On Wed, Dec 09, 2015 at 10:50:35AM -0600, Rob Herring wrote:
> On Wed, Dec 9, 2015 at 9:27 AM, Qais Yousef wrote:
> > Hi,
> >
> > On 10/22/2015 12:55 PM, Jason Cooper wrote:
> >>
> >> On Thu, Oct 22, 2015 at 11:44:16AM +0100, Qais Yousef wrote:
> >>>
> >>> Is there anything more I can do to get mo
On 09-12-15, 15:58, Lee Jones wrote:
> This is a re-write of the original submission, hence why the
> change-log is omitted. Basically almost everything has changed.
> We are now using the new OPP framework and generic bindings
> written by Viresh.
>
> There are 'ARM' patches in the set which are
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
> Exynos3250 has following AXI buses to translate data between
> DRAM and sub-blocks.
>
> Following list specifies the detailed relation between DRAM and sub-blocks:
> - ACLK400 clock for MCU
On 09-12-15, 15:58, Lee Jones wrote:
> +/*
> + * Only match on "suitable for ALL versions" entries
> + *
> + * This will be used with the BIT() macro. It sets the
> + * top bit of a 32bit value and is equal to 0x8000.
> + */
> +#define DEFAULT_VERSION 31
Okay, I misread it in the
On 10.12.2015 11:00, Chanwoo Choi wrote:
> On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
>> On 10.12.2015 10:09, Chanwoo Choi wrote:
>>> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
On 09.12.2015 13:07, Chanwoo Choi wrote:
> This patch adds the DMC (Dynamic Memory Controller) bu
On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
> On 10.12.2015 10:09, Chanwoo Choi wrote:
>> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>>> On 09.12.2015 13:07, Chanwoo Choi wrote:
This patch adds the DMC (Dynamic Memory Controller) bus node for
Exynos3250 SoC.
The DMC i
On 2015년 12월 10일 10:31, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch updates the documentation for passive bus devices and adds the
>> detailed example of Exynos3250.
>>
>> Signed-off-by: Chanwoo Choi
>> ---
>> .../devicetree/bindings/devfreq/exynos-bus.txt
Provides an options to use the ptp clock routed from the Altera FPGA
fabric. Instead of the defalt eosc1 clock connected to the ARM HPS core.
This setting affects all emacs in the core as the ptp clock is common.
Acked-by: Rob Herring
Signed-off-by: Phil Reid
---
Documentation/devicetree/bindin
stmmac_config_sub_second_increment set the sub second increment to 20ns.
Driver is configured to use the fine adjustment method where the sub second
register is incremented when the acculumator incremented by the addend
register wraps overflows. This accumulator is update on every ptp clk
cycle. If
devm_get_clk looks in clock-name property for matching clock.
the ptp_ref_clk property is ignored.
Acked-by: Rob Herring
Signed-off-by: Phil Reid
---
Documentation/devicetree/bindings/net/stmmac.txt | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/Documentat
The DSA driver needs to be passed a reference to an mdio bus. Typically
the mac is configured to use a fixed link but the mdio bus still needs
to be registered so that it con configure the switch.
This patch follows the same process as the altera tse ethernet driver for
creation of the mdio bus.
A
Provide ability to specify a fixed phy in the device tree and
retain the mdio bus if no phy is found. This is needed where
a dsa is connected via a fixed phy and uses the mdio bus for config.
Fixed ptp ref clock calculatins for the stmmac when ptp ref clock
is running at <= 50Mhz. Also add device
On 2015년 12월 10일 10:25, Krzysztof Kozlowski wrote:
> On 10.12.2015 09:49, Chanwoo Choi wrote:
>> Hi,
>>
> (...)
>
>>>
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+
On Tue, Dec 8, 2015 at 2:07 PM, Bjorn Andersson
wrote:
> On Tue 08 Dec 13:29 PST 2015, John Stultz wrote:
>> diff --git a/arch/arm/boot/dts/qcom-apq8064-nexus7-flo.dts
>> b/arch/arm/boot/dts/qcom-apq8064-nexus7-flo.dts
>> index 5183d18..ee5dcb7 100644
>> --- a/arch/arm/boot/dts/qcom-apq8064-nexus
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch updates the documentation for passive bus devices and adds the
> detailed example of Exynos3250.
>
> Signed-off-by: Chanwoo Choi
> ---
> .../devicetree/bindings/devfreq/exynos-bus.txt | 244
> -
> 1 file changed, 241
On 10.12.2015 09:49, Chanwoo Choi wrote:
> Hi,
>
(...)
>>
>>> +
>>> + bus_dmc: bus_dmc {
>>> + compatible = "samsung,exynos-bus";
>>> + clocks = <&cmu_dmc CLK_DIV_DMC>;
>>> + clock-names = "bus";
>>> + operating-points-v2 = <&bus_dmc_opp_table>;
>>> +
On 10.12.2015 09:57, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>
> (...)
>
>> .../devicetree/bindings/devfreq/exynos-bus.txt | 383 +++
>
> How about adding this file to the MAINTAINERS to devfreq exynos entry?
> Unfortunately, in current linux-next, I can fi
On 10.12.2015 10:09, Chanwoo Choi wrote:
> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250
>>> SoC.
>>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC
On Wed, Dec 9, 2015 at 2:07 AM, Arnd Bergmann wrote:
> On Tuesday 08 December 2015 16:22:40 John Stultz wrote:
>> >> diff --git a/arch/arm/boot/dts/qcom-apq8064-nexus7-flo.dts
>> >> b/arch/arm/boot/dts/qcom-apq8064-nexus7-flo.dts
>> >> index 5183d18..ee5dcb7 100644
>> >> --- a/arch/arm/boot/dts/q
On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250
>> SoC.
>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
>> SDRAM devices. The bus includes the
On 09.12.2015 13:07, Chanwoo Choi wrote:
(...)
> .../devicetree/bindings/devfreq/exynos-bus.txt | 383 +++
How about adding this file to the MAINTAINERS to devfreq exynos entry?
Unfortunately, in current linux-next, I can find the entry for devfreq
exynos. However I saw patches adding s
On 2015년 12월 10일 09:53, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the DMC (Dynamic Memory Controller) bus frequency node
>> which includes the devfreq-events and regulator properties. The bus
>> frequency support the DVFS (Dynamic Voltage Frequency Sca
On 09.12.2015 13:07, Chanwoo Choi wrote:
> This patch adds the DMC (Dynamic Memory Controller) bus frequency node
> which includes the devfreq-events and regulator properties. The bus
> frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature
> with ondemand governor.
>
> The devfreq
Hi,
On 2015년 12월 10일 09:39, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the documentation for generic exynos bus frequency
>> driver.
>>
>> Signed-off-by: Chanwoo Choi
>> ---
>> .../devicetree/bindings/devfreq/exynos-bus.txt | 94
>> +
* Felipe Balbi [151208 10:05]:
>
> Hi,
>
> Grygorii Strashko writes:
> > ARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2.
> > But now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result.
> > Timekeeping core misbehaves. For example, execution of command
> > "sleep
On 09.12.2015 13:07, Chanwoo Choi wrote:
> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250
> SoC.
> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
> block.
>
> Fo
On 09.12.2015 13:07, Chanwoo Choi wrote:
> This patch adds the documentation for generic exynos bus frequency
> driver.
>
> Signed-off-by: Chanwoo Choi
> ---
> .../devicetree/bindings/devfreq/exynos-bus.txt | 94
> ++
> 1 file changed, 94 insertions(+)
> create mode 100
Hi Jeffy,
Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen:
> Initial release for rk3228 shared dtsi.
>
> Signed-off-by: Jeffy Chen
> ---
>
> arch/arm/boot/dts/rk3228.dtsi | 478
> ++
> 1 file changed, 478 insertions(+)
> create mode 100644 a
Hi Anand,
First of all, thanks for trying to test this series.
On 2015년 12월 10일 04:05, Anand Moon wrote:
> Hi Chanwoo Choi,
>
> On 9 December 2015 at 09:37, Chanwoo Choi wrote:
>> This patch-set includes the two features as following. The generic exynos bus
>> frequency driver is able to suppor
Am Mittwoch, 9. Dezember 2015, 17:04:09 schrieb Jeffy Chen:
> Add the devicetree binding for the cru on the rk3228 which quite similar
> structured as previous clock controllers.
>
> Signed-off-by: Jeffy Chen
applied to my clock branch with Rob's ack
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[+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
questions below)]
On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
> Signed-off-by: Ravi Kiran Gummalu
Am Mittwoch, 9. Dezember 2015, 17:04:07 schrieb Jeffy Chen:
> Add the dt-bindings header for the rk3228, that gets shared between
> the clock controller and the clock references in the dts.
>
> Signed-off-by: Jeffy Chen
applied to my clk branch for 4.5
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Hi Rob,
Am Mittwoch, 9. Dezember 2015, 14:12:00 schrieb Rob Herring:
> On Wed, Dec 09, 2015 at 05:04:09PM +0800, Jeffy Chen wrote:
> > Add the devicetree binding for the cru on the rk3228 which quite similar
> > structured as previous clock controllers.
> >
> > Signed-off-by: Jeffy Chen
>
> See
On Thu, Nov 26, 2015 at 9:44 AM, Biao Huang wrote:
> Add mt2701 support using mediatek common pinctrl driver.
> MT2701 have some special pins need an extra setting register
> than other ICs, so adding this support to common code.
>
> Signed-off-by: Biao Huang
This looks uncontroversial, but I w
On Thu, Nov 26, 2015 at 9:44 AM, Biao Huang wrote:
> Add pinctrl and GPIO node to mt2701.dtsi
>
> Signed-off-by: Biao Huang
Acked-by: Linus Walleij
Take this through the ARM SoC tree as well.
Yours,
Linus Walleij
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On Thu, Nov 26, 2015 at 9:44 AM, Biao Huang wrote:
> Add pinfunc header file, mt2701 related dts will include it
>
> Signed-off-by: Biao Huang
Acked-by: Linus Walleij
Take this through ARM SoC as well.
Yours,
Linus Walleij
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On Thu, Nov 26, 2015 at 9:44 AM, Biao Huang wrote:
> From: Erin Lo
>
> The upcoming MTK pinctrl driver have a big pin table for each SoC
> and we don't want to bloat the kernel binary if we don't need it.
> Add config options so we can build for one SoC only. Add MT2701.
>
> Signed-off-by: Erin
ICP DAS calls LP-8x4x 'programmable automation controller'. It is
an industrial computer based on PXA270 SoC. They ship it with a 2.6.19
kernel and proprietary kernel module and userspace library to access
its industrial IO.
This patch allows to boot a modern kernel with device tree on
the device.
The BCM6358 contains power domains controlled with a register. Power
domains are indexed by bits in the register. Power domain bits can be
interleaved with other status bits and clocks in the same register.
Newer SoCs with dedicated power domain registers are active low.
Signed-off-by: Simon Arlo
The BCM6358 contains power domains controlled with a register. Power
domains are indexed by bits in the register. Power domain bits can be
interleaved with other status bits and clocks in the same register.
Newer SoCs with dedicated power domain registers are active low.
Signed-off-by: Simon Arlo
Hi,
On Wed, Dec 09, 2015 at 09:42:09AM -0800, Tim Bird wrote:
> Or maybe our power maintainers will chime in with some wisdom. I
> can't be the first person to be adding a charge pathway switch to
> mainline, so I'm open to doing it the "right way". :-)
I don't think there is a standard way for t
On Wed, Dec 9, 2015 at 3:58 AM, Andrzej Hajda wrote:
> Hi Rob,
>
> Thanks for review.
>
>
> On 12/09/2015 04:47 AM, Rob Herring wrote:
>> On Tue, Dec 08, 2015 at 02:49:05PM +0100, Andrzej Hajda wrote:
>>> SiI8620 transmitter converts eTMDS/HDMI signal to MHL 3.0. It is controlled
>>> via I2C bus.
On Wed, Dec 9, 2015 at 12:50 AM, Sascha Hauer wrote:
> On Tue, Dec 08, 2015 at 04:13:35PM -0800, John Stultz wrote:
>>
>> Is there a better way? Are enums for array indexes out of fashion?
>
> They are not, but you have declared a variable (reason_types) which you
> don't use. You probably meant t
On Wed, Dec 9, 2015 at 1:59 PM, Bjorn Andersson
wrote:
> On Wed 09 Dec 06:36 PST 2015, Rob Herring wrote:
>
>> On Wed, Dec 9, 2015 at 6:55 AM, Tim Bird wrote:
>> > On 12/08/2015 08:11 PM, Rob Herring wrote:
>> >> On Tue, Dec 08, 2015 at 04:40:16PM -0800, Tim Bird wrote:
>> >>> Add a binding for t
Le 09/12/2015 12:43, Simon Arlott a écrit :
> The BCM6368 has a NAND interrupt register with combined status and enable
> registers.
>
> As the BCM6328, BCM6362 and BCM6368 all use v2.1 controllers, the first
> variant that will work with this driver is the BCM63268 using a v4.0
> controller.
>
>
Le 09/12/2015 12:42, Simon Arlott a écrit :
> Attempt to enable a clock named "nand" as some SoCs have a clock for the
> controller that needs to be enabled.
>
> Signed-off-by: Simon Arlott
Reviewed-by: Florian Fainelli
> ---
> Resend, no changes.
>
> drivers/mtd/nand/brcmnand/brcmnand.c | 6
Le 09/12/2015 12:40, Simon Arlott a écrit :
> Add device tree binding for NAND on the BCM6368.
>
> The BCM6368 has a NAND interrupt register with combined status and enable
> registers. It also requires a clock, so add an optional clock to the
> common brcmnand binding.
>
Reviewed-by: Florian Fa
Hi Linus,
Please pull DT fixes for 4.4. I think this should be all for 4.4.
Rob
The following changes since commit 31ade3b83e1821da5fbb2f11b5b3d4ab2ec39db8:
Linux 4.4-rc3 (2015-11-29 18:58:26 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/robh
The BCM6368 has a NAND interrupt register with combined status and enable
registers.
As the BCM6328, BCM6362 and BCM6368 all use v2.1 controllers, the first
variant that will work with this driver is the BCM63268 using a v4.0
controller.
Set up the device by disabling and acking all interrupts, t
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