Fix a few typos and reword the description of the
'#qca,ddr-wb-channel-cells' property.
Signed-off-by: Alban Bedel <al...@free.fr>
CC: triv...@kernel.org
---
Changlog:
v2: * Fixed the truncated log message because of a
line starting with a #.
---
.../bindings/memory-controllers/ath
Add a missing quote in the example
Signed-off-by: Alban Bedel <al...@free.fr>
CC: triv...@kernel.org
---
.../devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/int
Fix a few typos and reword the description of the
Signed-off-by: Alban Bedel <al...@free.fr>
CC: triv...@kernel.org
---
.../bindings/memory-controllers/ath79-ddr-controller.txt | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
a/Documentation/devicetree/bi
Add a missing quote in the example
Signed-off-by: Alban Bedel <al...@free.fr>
CC: triv...@kernel.org
---
.../devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/int
Signed-off-by: Alban Bedel <al...@free.fr>
---
Changelog:
v2: * Fix the USB controller node name to follow ePAPR
* Enable the USB phy as it is now disabled per default
---
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arc
Signed-off-by: Alban Bedel <al...@free.fr>
---
Changelog:
v2: * Fix the USB controller node name to follow ePAPR
* Set the USB phy as disabled like the USB controller
---
arch/mips/boot/dts/qca/ar9132.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git
The ATH79 USB phy is very simple, it only have a reset. On some SoC a
second reset is used to force the phy in suspend mode regardless of the
USB controller status.
Signed-off-by: Alban Bedel <al...@free.fr>
---
Changelog:
v2: * Rebased on the simple PHY driver
* Added myself as main
configuration.
Alban
Alban Bedel (5):
phy: Add a driver for simple phy
devicetree: Add bindings for the ATH79 USB phy
phy: Add a driver for the ATH79 USB phy
MIPS: ath79: Add the EHCI controller and USB phy to the AR9132 dtsi
MIPS: ath79: Enable the USB port on the TL-WR1043ND
This driver is meant to take care of all trivial phys that don't need
any special configuration, it just enable a regulator, a clock and
deassert a reset. A public API is also included to allow re-using the
code in other drivers.
Signed-off-by: Alban Bedel <al...@free.fr>
---
drivers/phy/K
Signed-off-by: Alban Bedel <al...@free.fr>
---
.../devicetree/bindings/phy/phy-ath79-usb.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
diff --git a/Documentation/devicetree/bindings/phy/phy
+ }
> +
> + mips_hpt_frequency = clk_get_rate(clk) / 2;
> + clk_put(clk);
> +}
I wanted to use something similar on ATH79 once all boards moved to DT.
On the other hand I saw that BMIPS use a dedicated property on the CPU
node to represent the HPT frequency. If possible it wou
intc_of_init(
> + struct device_node *node, struct device_node *parent)
> +{
> + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
> + return ath79_misc_intc_of_init(node, parent);
> +}
> +
> +IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
> +
ce_node *parent)
> +{
> + ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
> + return ath79_misc_intc_of_init(node, parent);
> +}
> +
> +IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
> + ar7100_misc_intc_of_init);
>
> static
On Wed, 9 Sep 2015 11:04:06 +0200
Alexander Couzens <lyn...@fe80.eu> wrote:
> On Thu, 3 Sep 2015 10:32:45 +0200
> Alban <al...@free.fr> wrote:
>
> > > -IRQCHIP_DECLARE(ath79_misc_intc, "qca,ar7100-misc-intc",
> > > - ath79_mis
On Mon, 07 Sep 2015 15:20:42 +0200
Arnd Bergmann <a...@arndb.de> wrote:
> On Tuesday 01 September 2015 17:23:10 Alban Bedel wrote:
> >
> > this serie add a driver for the USB phy on the ATH79 SoCs and enable the
> > USB port on the TL-WR1043ND. The phy controller is re
_init(
> IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
> ar7100_misc_intc_of_init);
>
> +static int __init ar7240_misc_intc_of_init(
> + struct device_node *node, struct device_node *parent)
> +{
> + ath79_misc_irq_chip.irq_ack = ar
c, "qca,ar7100-misc-intc",
> + ar7100_misc_intc_of_init);
>
> static int __init ar79_cpu_intc_of_init(
> struct device_node *node, struct device_node *parent)
Otherwise that looks good.
Alban
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Signed-off-by: Alban Bedel <al...@free.fr>
---
arch/mips/boot/dts/qca/ar9132.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi
b/arch/mips/boot/dts/qca/ar9132.dtsi
index fb7734e..665ee84 100644
--- a/arch/mips/boot/d
Signed-off-by: Alban Bedel <al...@free.fr>
---
.../devicetree/bindings/phy/phy-ath79-usb.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
diff --git a/Documentation/devicetree/bindings/phy/phy
The ATH79 USB phy is very simple, it only have a reset. On some SoC a
second reset is used to force the phy in suspend mode regardless of the
USB controller status.
Signed-off-by: Alban Bedel <al...@free.fr>
---
drivers/phy/Kconfig | 8 +++
drivers/phy/Makefile| 1 +
d
Hi,
this serie add a driver for the USB phy on the ATH79 SoCs and enable the
USB port on the TL-WR1043ND. The phy controller is really trivial as it
only use reset lines.
Alban
Alban Bedel (4):
devicetree: Add bindings for the ATH79 USB phy
phy: Add a driver for the ATH79 USB phy
MIPS
Signed-off-by: Alban Bedel <al...@free.fr>
---
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
index 003015a..cd51199 100644
---
+ AR71XX_RESET_REG_MISC_INT_ENABLE);
__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
-
I would prefer to see this in another patch.
[...]
Alban
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More
be better to keep the same formatting as the surrounding code.
Could you keep the IRQCHIP_DECLARE() together with the init function
and remove the extra blank line?
Alban
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More
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/boot/dts/qca/ar9132.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi
b/arch/mips/boot/dts/qca/ar9132.dtsi
index 4759cff..fb7734e 100644
--- a/arch/mips/boot/dts/qca/ar9132.dtsi
+++ b/arch
Signed-off-by: Alban Bedel al...@free.fr
---
.../devicetree/bindings/reset/ath79-reset.txt| 20
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/ath79-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/ath79
Fix the clocks property documentation and use lower case for
hex values in the example.
Signed-off-by: Alban Bedel al...@free.fr
---
Documentation/devicetree/bindings/spi/spi-ath79.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi
On Mon, 15 Jun 2015 10:42:13 +0300
Antony Pavlov antonynpav...@gmail.com wrote:
On Wed, 10 Jun 2015 23:58:11 +0200
Alban al...@free.fr wrote:
On Mon, 8 Jun 2015 13:17:58 +0300
Antony Pavlov antonynpav...@gmail.com wrote:
IMHO AR9132 SoC can't work without external oscilator
frequency value.
I would prefer to keep the split between the files in sync with the
hardware. I understand that most simple board designs use a fixed
oscillator, but that might not always be the case.
Alban
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Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fixed the node names to respect ePAPR
* Fixed the missing 's' in 'fallbacks' and the 'clocks' property
v3: * Fix the compatible string for qca9550
---
.../devicetree/bindings/clock/qca,ath79-pll.txt| 33 ++
1 file
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fixed the node names to respect ePAPR
---
.../interrupt-controller/qca,ath79-misc-intc.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc
Add OF support for the CPU and MISC interrupt controllers of most
supported ATH79 devices.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/ath79/irq.c | 87 ++-
1 file changed, 86 insertions(+), 1 deletion(-)
diff --git a/arch/mips/ath79
These bindings support the GPIO controllers found on the Qualcomm
Atheros AR7xxx/AR9XXX SoC.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Add the ngpios property to have fewer fallbacks and simpler code
v3: * Fix missing 's' typo
* Fix the example to be valid with the binding
v4: * Fix
Add a DTS for TL-WR1043ND version 1 and allow to have it built in the
kernel to circumvent the broken u-boot found on these boards.
Currently only the UART, LEDs and buttons are supported.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Rebased for the new vendor directory structure
Replace the simple GPIO chip registration by a platform driver
and make ath79_gpio_init() just register the device.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Added an 'ngpios' property instead of the many matches
* Use a platform data struct to store the device config on
non-DT
Signed-off-by: Alban Bedel al...@free.fr
---
v3: * Put the new entry at the right place
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor
Allow using the SoC clocks in the device tree.
Signed-off-by: Alban Bedel al...@free.fr
---
v3: * Fix the compatible string for qca9550
v4: * Added missing Signed-off-by
---
arch/mips/ath79/clock.c | 63 ++---
1 file changed, 44 insertions(+), 19
* Always build the DTB to improve testing coverage
* Added the SPI controller and flash to the DTS as the binding for
the SPI controller has been accepted in the SPI tree
Alban Bedel (12):
devicetree: Add bindings for the SoC of the ATH79 family
MIPS: ath79: Add basic device tree
Add the bare minimum to load a device tree.
Signed-off-by: Alban Bedel al...@free.fr
---
v3: * Removed the empty Builtin devicetree menu
---
arch/mips/Kconfig | 1 +
arch/mips/ath79/machtypes.h | 1 +
arch/mips/ath79/setup.c | 27 ++-
3 files changed, 28
The DDR controller of the ARxxx and AR9xxx families provides an
interface to flush the FIFO between various devices and the DDR.
This is mainly used by the IRQ controller to flush the FIFO before
running the interrupt handler of such devices.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fix
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fixed the node names to respect ePAPR
* Removed the unneeded @0 on the node name
---
.../interrupt-controller/qca,ath79-cpu-intc.txt| 44 ++
1 file changed, 44 insertions(+)
create mode 100644
Documentation
Signed-off-by: Alban Bedel al...@free.fr
---
.../devicetree/bindings/mips/ath79-soc.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ath79-soc.txt
diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fixed the node names to respect ePAPR
* Fixed the missing 's' in 'fallbacks' and the 'clocks' property
v3: * Fix the compatible string for qca9550
---
.../devicetree/bindings/clock/qca,ath79-pll.txt| 33 ++
1 file
Add OF support for the CPU and MISC interrupt controllers of most
supported ATH79 devices.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/ath79/irq.c | 87 ++-
1 file changed, 86 insertions(+), 1 deletion(-)
diff --git a/arch/mips/ath79
Signed-off-by: Alban Bedel al...@free.fr
---
v3: * Put the new entry at the right place
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fixed the node names to respect ePAPR
---
.../interrupt-controller/qca,ath79-misc-intc.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc
Replace the simple GPIO chip registration by a platform driver
and make ath79_gpio_init() just register the device.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Added an 'ngpios' property instead of the many matches
* Use a platform data struct to store the device config on
non-DT
Allow using the SoC clocks in the device tree.
---
v3: * Fix the compatible string for qca9550
---
arch/mips/ath79/clock.c | 63 ++---
1 file changed, 44 insertions(+), 19 deletions(-)
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
These bindings support the GPIO controllers found on the Qualcomm
Atheros AR7xxx/AR9XXX SoC.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Add the ngpios property to have fewer fallbacks and simpler code
v3: * Fix missing 's' typo
* Fix the example to be valid with the binding
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fixed the node names to respect ePAPR
* Removed the unneeded @0 on the node name
---
.../interrupt-controller/qca,ath79-cpu-intc.txt| 44 ++
1 file changed, 44 insertions(+)
create mode 100644
Documentation
The DDR controller of the ARxxx and AR9xxx families provides an
interface to flush the FIFO between various devices and the DDR.
This is mainly used by the IRQ controller to flush the FIFO before
running the interrupt handler of such devices.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fix
to use ePAPR names
* Fixed the qca9550 compatible string in the PLL bindings and driver
* Fixed the example in the GPIO controller binding
* Moved the new vendor entry to the correct place
Alban Bedel (12):
devicetree: Add bindings for the SoC of the ATH79 family
MIPS: ath79: Add
Add the bare minimum to load a device tree.
Signed-off-by: Alban Bedel al...@free.fr
---
v3: * Removed the empty Builtin devicetree menu
---
arch/mips/Kconfig | 1 +
arch/mips/ath79/machtypes.h | 1 +
arch/mips/ath79/setup.c | 27 ++-
3 files changed, 28
On Mon, 20 Apr 2015 11:50:56 +0200
Paul Bolle pebo...@tiscali.nl wrote:
On Sat, 2015-04-18 at 18:31 +0200, Alban wrote:
On Sat, 18 Apr 2015 09:05:52 +0200
Paul Bolle pebo...@tiscali.nl wrote:
On Fri, 2015-04-17 at 16:24 +0200, Alban Bedel wrote:
--- a/arch/mips/ath79/Kconfig
Signed-off-by: Alban Bedel al...@free.fr
---
.../devicetree/bindings/mips/ath79-soc.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ath79-soc.txt
diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt
The internal chip select CS0 wasn't initialized properly to work with
CS HIGH chips.
Signed-off-by: Alban Bedel al...@free.fr
---
drivers/spi/spi-ath79.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index b37bedd..bf1f9b3 100644
Signed-off-by: Alban Bedel al...@free.fr
---
.../devicetree/bindings/spi/spi-ath79.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-ath79.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-ath79.txt
Clocks should be prepared and unprepared, fix this by using
clk_prepare_enable() and clk_disable_unprepare() instead of
clk_enable() and clk_disable().
Signed-off-by: Alban Bedel al...@free.fr
---
drivers/spi/spi-ath79.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Add a DTS for TL-WR1043ND version 1 and allow to have it built in the
kernel to circumvent the broken u-boot found on these boards.
Currently only the UART, LEDs and buttons are supported.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Rebased for the new vendor directory structure
Set the OF node of the spi controller and use the generic GPIO based
chip select instead of the custom controller data. As the controller
data isn't used by any board just drop it.
Signed-off-by: Alban Bedel al...@free.fr
---
.../mips/include/asm/mach-ath79/ath79_spi_platform.h | 4
the platform is moved to the generic clock framework.
Finally the last patch is to ensure that CS_HIGH chips using CS0 get the
proper CS level before the first transfer.
Alban
Alban Bedel (4):
devicetree: add binding documentation for the AR7100 SPI controller
spi: spi-ath79: Add device tree support
On Sat, 18 Apr 2015 13:33:20 -0700
Florian Fainelli f.faine...@gmail.com wrote:
Le 17/04/2015 07:24, Alban Bedel a écrit :
This series add OF bindings and code support for the interrupt
controllers, clocks and GPIOs. However it was only tested on a
TL-WR1043ND with an AR9132, others SoCs
Add the bare minimum to load a device tree.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/Kconfig | 1 +
arch/mips/ath79/Kconfig | 10 ++
arch/mips/ath79/machtypes.h | 1 +
arch/mips/ath79/setup.c | 27 ++-
4 files changed, 38
The DDR controller of the ARxxx and AR9xxx famillies provides an
interface to flush the FIFO between various devices and the DDR.
This is mainly used by the IRQ controller to flush the FIFO before
running the interrupt handler of such devices.
Signed-off-by: Alban Bedel al...@free.fr
---
v2
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fixed the node names to respect ePAPR
---
.../interrupt-controller/qca,ath79-misc-intc.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fixed the node names to respect ePAPR
* Fixed the missing 's' in 'fallbacks' and the 'clocks' property
---
.../devicetree/bindings/clock/qca,ath79-pll.txt| 33 ++
1 file changed, 33 insertions(+)
create mode 100644
Add OF support for the CPU and MISC interrupt controllers of most
supported ATH79 devices.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/ath79/irq.c | 87 ++-
1 file changed, 86 insertions(+), 1 deletion(-)
diff --git a/arch/mips/ath79
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Fixed the node names to respect ePAPR
* Removed the unneeded @0 on the node name
---
.../interrupt-controller/qca,ath79-cpu-intc.txt| 44 ++
1 file changed, 44 insertions(+)
create mode 100644
Documentation
Signed-off-by: Alban Bedel al...@free.fr
---
.../devicetree/bindings/mips/ath79-soc.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ath79-soc.txt
diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt
overkill.
* Moved the patch to use the common clk API to the bug fix serie to keep
this one cleaner.
Alban Bedel (12):
devicetree: Add bindings for the SoC of the ATH79 familly
MIPS: ath79: Add basic device tree support
devicetree: Add bindings for the ATH79 DDR controllers
devicetree
These bindings support the GPIO controllers found on the Qualcomm
Atheros AR7xxx/AR9XXX SoC.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Add the ngpios property to have fewer fallbacks and simpler code
---
.../devicetree/bindings/gpio/gpio-ath79.txt| 38 ++
1
Allow using the SoC clocks in the device tree.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/ath79/clock.c | 63 ++---
1 file changed, 44 insertions(+), 19 deletions(-)
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index
Replace the simple GPIO chip registration by a platform driver
and make ath79_gpio_init() just register the device.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Added an 'ngpios' property instead of the many matches
* Use a platform data struct to store the device config on
non-DT
Signed-off-by: Alban Bedel al...@free.fr
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index b13aa55..9e965b6 100644
Add a DTS for TL-WR1043ND version 1 and allow to have it built in the
kernel to circumvent the broken u-boot found on these boards.
Currently only the UART, LEDs and buttons are supported.
Signed-off-by: Alban Bedel al...@free.fr
---
v2: * Rebased for the new vendor directory structure
A basic dtsi for the AR9132 with support for the DDR controller, CPU
and MISC interrupt controller, GPIO controller, the UART and the
watchdog.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/boot/dts/ar9132.dtsi | 119 +
1 file changed, 119
Signed-off-by: Alban Bedel al...@free.fr
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index b13aa55..9e965b6 100644
Add a DTS for TL-WR1043ND version 1 and allow to have it built in the
kernel to circumvent the broken u-boot found on these boards.
Currently only the UART, LEDs and buttons are supported.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/ath79/Kconfig | 5 ++
arch
On Fri, 17 Apr 2015 16:53:31 +0200
Arnd Bergmann a...@arndb.de wrote:
On Friday 17 April 2015 16:24:26 Alban Bedel wrote:
Replace the simple GPIO chip registration by a platform driver
and make ath79_gpio_init() just register the device.
Signed-off-by: Alban Bedel al...@free.fr
On Sat, 18 Apr 2015 09:05:52 +0200
Paul Bolle pebo...@tiscali.nl wrote:
On Fri, 2015-04-17 at 16:24 +0200, Alban Bedel wrote:
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
+choice
+ prompt Builtin devicetree selection
+ default DTB_ATH79_NONE
+ help
Signed-off-by: Alban Bedel al...@free.fr
---
.../interrupt-controller/qca,ath79-cpu-intc.txt| 45 ++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt
diff --git
a/Documentation/devicetree
Signed-off-by: Alban Bedel al...@free.fr
---
.../interrupt-controller/qca,ath79-misc-intc.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
diff --git
a/Documentation/devicetree
These bindings support the GPIO controllers found on the Qualcomm
Atheros AR7xxx/AR9XXX SoC.
Signed-off-by: Alban Bedel al...@free.fr
---
.../devicetree/bindings/gpio/gpio-ath79.txt| 40 ++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree
Signed-off-by: Alban Bedel al...@free.fr
---
.../devicetree/bindings/clock/qca,ath79-pll.txt| 33 ++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
diff --git a/Documentation/devicetree/bindings/clock/qca
This series add OF bindings and code support for the interrupt
controllers, clocks and GPIOs. However it was only tested on a
TL-WR1043ND with an AR9132, others SoCs are untested, and a few are
not supported at all.
Most code changes base on the previous bug fix series:
[PATH] MIPS: ath79:
Add OF support for the CPU and MISC interrupt controllers of most
supported ATH79 devices.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/ath79/irq.c | 87 ++-
1 file changed, 86 insertions(+), 1 deletion(-)
diff --git a/arch/mips/ath79
Replace the simple GPIO chip registration by a platform driver
and make ath79_gpio_init() just register the device.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/ath79/dev-common.c | 13
arch/mips/ath79/gpio.c | 73 +---
2 files
Allow using the SoC clocks in the device tree.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/ath79/clock.c | 63 ++---
1 file changed, 44 insertions(+), 19 deletions(-)
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index
Add the bare minimum to load a device tree.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/Kconfig | 1 +
arch/mips/ath79/Kconfig | 10 ++
arch/mips/ath79/machtypes.h | 1 +
arch/mips/ath79/setup.c | 27 ++-
4 files changed, 38
The DDR controller of the ARxxx and AR9xxx famillies provides an
interface to flush the FIFO between various devices and the DDR.
This is mainly used by the IRQ controller to flush the FIFO before
running the interrupt handler of such devices.
Signed-off-by: Alban Bedel al...@free.fr
Signed-off-by: Alban Bedel al...@free.fr
---
.../devicetree/bindings/mips/ath79-soc.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ath79-soc.txt
diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt
Make the code simpler and open the way for device tree clocks.
Signed-off-by: Alban Bedel al...@free.fr
---
arch/mips/Kconfig | 1 +
arch/mips/ath79/clock.c | 29 ++---
2 files changed, 3 insertions(+), 27 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
.../bindings/regulator/constrained-supply.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/constrained-supply.txt
diff --git a/Documentation
This driver allow using simple driver that expect a single regulator
on hardware that need to enable several regulators. Optionally the
driver can enforce the enable and disable order to provide a simple
power sequencing.
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
drivers
This driver is meant for devices that are supplied by a settable
regulator but that don't set their supply voltage explicitly.
With this reglator those simple driver can just get and enable the
regulator and they will get the correct voltage.
Signed-off-by: Alban Bedel alban.be...@avionic
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
.../devicetree/bindings/regulator/group.txt| 26 ++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/regulator/group.txt
diff --git a/Documentation/devicetree/bindings
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
.../devicetree/bindings/gpio/gpio-level-shifter.txt | 15 +++
1 file changed, 15 insertions(+)
create mode 100644
Documentation/devicetree/bindings/gpio/gpio-level-shifter.txt
diff --git a/Documentation/devicetree
This driver support setting the level shifter direction and/or enable
as needed.
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
drivers/gpio/Kconfig | 6 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-level-shifter.c | 248
On Mon, 24 Nov 2014 15:15:27 +
Mark Brown broo...@kernel.org wrote:
On Mon, Nov 24, 2014 at 02:02:00PM +0100, Alban Bedel wrote:
+Constrained Supply Regulator
+
+This binding allow creating a virtual regulator that constrain its
+supply to provides the requested voltage
On Mon, 24 Nov 2014 15:24:33 +
Mark Brown broo...@kernel.org wrote:
On Mon, Nov 24, 2014 at 02:02:02PM +0100, Alban Bedel wrote:
+This binding allow creating a group of regulators for use with simple
+drivers that only expect a single power supply. Additionally it is
+possible
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