for transactions to/from peripheral devices.
The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig| 10 +
drivers/dma/Makefile
On Tue, Feb 03, 2015 at 02:17:57PM +0200, Ivan T. Ivanov wrote:
Following set of patches add initial DT support for PMIC devices
found on recent Quqalcomm chipsets. Details for SPMI bus and PMIC arbiter
could be found here [1].
Looks fine.
Reviewed-by: Andy Gross agr...@codeaurora.org
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8660.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot
on the GSBI port configuration.
Changes since v2:
- Use cell-index instead of alias to denote GSBI instance
Changes since v1:
- Fixed various review comments
Andy Gross (6):
soc: qcom: gsbi: Add support for ADM CRCI muxing
mfd: qcom,tcsr: Add device tree binding for TCSR
ARM: DT: apq8064: Add
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot
This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device. The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings
This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients. The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.
Signed-off-by: Andy Gross agr...@codeaurora.org
svarba...@mm-sol.com
Reviewed-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Looks good.
Reviewed-by: Andy Gross agr...@codeaurora.org
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8660.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch
This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients. The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.
Signed-off-by: Andy Gross agr...@codeaurora.org
This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device. The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm
on the GSBI port configuration.
Changes since v1:
- Fixed various review comments
Andy Gross (6):
soc: qcom: gsbi: Add support for ADM CRCI muxing
mfd: qcom,tcsr: Add device tree binding for TCSR
ARM: DT: apq8064: Add TCSR support
ARM: DT: ipq8064: Add TCSR support
ARM: DT: msm8660: Add TCSR
On Tue, Jan 27, 2015 at 07:11:50PM -0800, Bjorn Andersson wrote:
On Tue 27 Jan 14:10 PST 2015, Andy Gross wrote:
This solution looks good, just some style things.
diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
[..]
+#define MAX_GSBI 12
+
+#define
On Wed, Jan 28, 2015 at 11:05:50AM +0200, Stanimir Varbanov wrote:
snip
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 7bd2c94..32f20be 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -4,6 +4,7 @@
config QCOM_GSBI
tristate
On Tue, Jan 20, 2015 at 11:17:56AM +0200, Stanimir Varbanov wrote:
snip
+ MSM_MUX_blsp1_spi,
+ MSM_MUX_blsp2_spi,
+ MSM_MUX_blsp3_spi,
The above three need to be renamed to blsp_spiX_csX to denote which SPI and chip
select they modify.
+ MSM_MUX_blsp_i2c1,
+
On Wed, Jan 28, 2015 at 06:11:50PM -0800, Stephen Boyd wrote:
snip
Required properties:
-- compatible: must contain qcom,gsbi-v1.0.0 for APQ8064/IPQ8064
+- compatible: Should contain:
+ qcom,gsbi-ipq8064 for IPQ8064
+ qcom,gsbi-apq8064 for APQ8064
+
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8660.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git
This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients. The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.
Signed-off-by: Andy Gross agr...@codeaurora.org
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git
on the GSBI port configuration.
Andy Gross (6):
soc: qcom: gsbi: Add support for ADM CRCI muxing
mfd: qcom,tcsr: Add device tree binding for TCSR
ARM: DT: apq8064: Add TCSR support
ARM: DT: ipq8064: Add TCSR support
ARM: DT: msm8660: Add TCSR support
ARM: DT: msm8960: Add TCSR support
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20 +---
1 file changed, 17 insertions(+), 3 deletions
This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device. The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 +---
1 file changed, 17 insertions(+), 3 deletions
On Thu, Jan 22, 2015 at 10:59:14AM -0800, Jack Pham wrote:
Hi Andy,
On Fri, Sep 12, 2014 at 02:28:08PM -0500, Andy Gross wrote:
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
some
Qualcomm platforms. This driver uses the generic PHY framework
On Fri, Jan 09, 2015 at 01:06:56AM +0100, Arnd Bergmann wrote:
On Thursday 08 January 2015 16:52:56 Andy Gross wrote:
This patch adds support for the TCSR (Top Control and Status Register) IP
block
that is present in the Qualcomm IPQ8064, APQ8064, and some later processors.
This block
On Thu, Jan 08, 2015 at 03:39:44PM -0800, Stephen Boyd wrote:
On 01/08/2015 02:52 PM, Andy Gross wrote:
+
+static struct platform_driver qcom_tcsr_driver = {
+ .driver = {
+ .name = tcsr,
+ .owner = THIS_MODULE,
This is done
controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/soc/qcom/Kconfig |7
drivers/soc/qcom/Makefile|1 +
drivers/soc/qcom/qcom_tcsr.c | 83 ++
include/soc/qcom/qcom_tcsr.h | 21 +++
4 files changed, 112
configuration settings for the USB
PHY selection and ADM DMA CRCI muxing.
Andy Gross (2):
soc: qcom: Add TCSR driver
soc: qcom: Add device tree binding for TCSR
.../devicetree/bindings/soc/qcom/qcom,tcsr.txt | 33
drivers/soc/qcom/Kconfig |7
Add device tree binding support for the QCOM TCSR driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/soc/qcom/qcom,tcsr.txt | 33 +++
include/dt-bindings/soc/qcom,tcsr.h| 34
2 files changed, 67
These patches add multiple copy support for functions which require additional
mux configurations on specific Qualcomm processor pincontrol blocks. Functions
which may have multiple copies are slimbus, mi2s, pdm, pcie, and GSBI.
Andy Gross (4):
pinctrl: qcom: Add multiple copy base support
Qualcomm pinctrl devices support functions that can be routed to multiple pins.
In some cases, there are additional mux registers that must be set for the pins
to work correctly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/pinctrl/qcom/pinctrl-msm.c | 10 ++
drivers
This patch adds multiple copy support for functions that can be mapped to more
than one pin and that also require an additional mux configuration setting to
work properly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../bindings/pinctrl/qcom,msm8960-pinctrl.txt | 19
This patch adds multiple copy support for functions that can be mapped to more
than one pin and that also require an additional mux configuration setting to
work properly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../bindings/pinctrl/qcom,ipq8064-pinctrl.txt | 16 +-
drivers
This patch adds multiple copy support for functions that can be mapped to more
than one pin and that also require an additional mux configuration setting to
work properly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../bindings/pinctrl/qcom,apq8064-pinctrl.txt |3 +-
drivers
On Wed, Oct 01, 2014 at 01:52:31PM +0530, Pramod Gurav wrote:
Andy,
With your change dmaengine: qcom_bam_dma: Add v1.3.0 driver support
and enabling qcom_bam_dma driver i was seeing some crashes in the kernel
on IFC6410. But after reverting you change and applying these changes
from Vinod I
On Mon, Sep 29, 2014 at 10:03:07AM +0530, Archit Taneja wrote:
The BAM DMA IP comes in different versions. The register offset layout varies
among these versions. The layouts depend on which generation/family of SoCs
they
belong to.
The current SoCs(like 8084, 8074) have a layout where the
snip
+ break;
+ default:
+ achan-slave.src_maxburst = 0;
+ achan-slave.dst_maxburst = 0;
Why clear these for error cases
With the return I shouldn't need to. I'll fix this.
+ ret = -EINVAL;
+
, looks good.
Reviewed-by: Andy Gross agr...@codeaurora.org
--
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
--
To unsubscribe from this list: send the line unsubscribe devicetree
On Tue, Sep 16, 2014 at 11:27:52AM -0700, Jack Pham wrote:
Hi Andy,
On Fri, Sep 12, 2014 at 02:28:08PM -0500, Andy Gross wrote:
+static int qcom_dwc3_hs_phy_init(struct qcom_dwc3_usb_phy *phy_dwc3)
+{
+ u32 val;
+
+ /*
+* HSPHY Initialization: Enable UTMI clock, select
On Tue, Aug 26, 2014 at 05:00:45PM +0530, Kiran Padwal wrote:
This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
It also adds necessary DT support for i2c eeprom which is present on
IFC6410.
Tested on IFC6410 board.
Looks fine
Signed-off-by: Kiran Padwal
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Andy
-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/phy/qcom-dwc3-usb-phy.txt | 39
.../devicetree/bindings/usb/qcom,dwc3.txt | 66
2 files changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3
On Fri, Sep 12, 2014 at 12:47:04PM -0500, Felipe Balbi wrote:
Hi,
On Fri, Sep 12, 2014 at 12:29:45PM -0500, Andy Gross wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP
On Fri, Sep 12, 2014 at 12:50:23PM -0500, Josh Cartwright wrote:
Hey Andy-
Mostly cosmetic things below:
On Fri, Sep 12, 2014 at 12:29:46PM -0500, Andy Gross wrote:
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
some
Qualcomm platforms. This driver uses
in 'gdsc' requlator name.
Andy Gross (1):
phy: Add Qualcomm DWC3 HS/SS PHY driver
Ivan T. Ivanov (2):
usb: dwc3: qcom: Add device tree binding
usb: dwc3: Add Qualcomm DWC3 glue layer driver
.../devicetree/bindings/phy/qcom-dwc3-usb-phy.txt | 39 ++
.../devicetree/bindings/usb/qcom,dwc3.txt
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Andy
-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/phy/qcom-dwc3-usb-phy.txt | 39
.../devicetree/bindings/usb/qcom,dwc3.txt | 66
2 files changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile
will only support slave DMA operations
between system memory and peripherals. Flow control via the CRCI (client rate
control interface) is supported and can be configured via device tree
configuration. Flow control usage is required for some peripheral devices.
Andy Gross (2):
dmaengine: Add QCOM
Add device tree binding support for the QCOM ADM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
Documentation/devicetree/bindings/dma/qcom_adm.txt | 62
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
for transactions to/from peripheral devices.
The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig| 10 +
drivers/dma/Makefile
On Tue, Aug 26, 2014 at 03:45:54PM +0300, Georgi Djakov wrote:
This patchset adds pinctrl support for the Qualcomm APQ8084 platform.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Looks good. I'll try to test this tomorrow, but for now
Reviewed-by: Andy Gross agr...@codeaurora.org
On Tue, Aug 26, 2014 at 03:45:55PM +0300, Georgi Djakov wrote:
Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin
controller inside the APQ8084.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Looks fine.
Reviewed-by: Andy Gross agr...@codeaurora.org
--
sent
On Tue, Aug 19, 2014 at 09:39:30PM -0700, Bjorn Andersson wrote:
On Tue 19 Aug 10:22 PDT 2014, Georgi Djakov wrote:
This patch adds support for the TLMM (Top-Level Mode Mux) block found
in the APQ8084 platform.
[...]
+
+#define NUM_GPIO_PINGROUPS 143
+
I think this looks good
On Tue, Aug 19, 2014 at 08:22:14PM +0300, Georgi Djakov wrote:
This patch adds support for the TLMM (Top-Level Mode Mux) block found
in the APQ8084 platform.
Comment in-line
snip
+ PINCTRL_PIN(134, GPIO_134),
+ PINCTRL_PIN(135, GPIO_135),
+ PINCTRL_PIN(136, GPIO_136),
+
(client rate
control interface) is supported and can be configured via device tree
configuration. Flow control usage is required for some peripheral devices.
Andy Gross (2):
dmaengine: Add QCOM ADM DMA driver
dmaengine: qcom_adm: Add device tree binding
Documentation/devicetree/bindings/dma
for transactions to/from peripheral devices.
The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig| 10 +
drivers/dma/Makefile
Add device tree binding support for the QCOM ADM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
Documentation/devicetree/bindings/dma/qcom_adm.txt | 60
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
On Tue, Jun 10, 2014 at 11:25:23AM -0700, Bjorn Andersson wrote:
In general, it all looks good. I only have 2 areas of concern. The first is a
nit and it has to do with alternate pins for functions. There really isn't a
need for a separate function name. That would only be required if the
mode setting for the ports and keep the children
from accessing the GSBI directly.
Changes from v1:
- Add dt-bindings file containing definitions for MUX values
- Fix code comments
- Removed unnecessary code
Andy Gross (4):
soc: Placeholder files for drivers/soc
soc: qcom
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.
Signed-off-by: Andy Gross agr
Add device tree binding support for the QCOM GSBI driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 78
include/dt-bindings/soc/qcom,gsbi.h| 26 +++
2 files changed, 104 insertions
On Mon, Apr 21, 2014 at 09:48:16AM -0400, Christopher Covington wrote:
snip
In that thread, Olof wrote, The code [going into drivers/soc] isn't the pure
drivers. Those we find homes for.
Right. I see this as glue for the most part. You could argue it's a small
pinctrl, but this doesn't
On Mon, Apr 21, 2014 at 11:54:00AM -0500, Josh Cartwright wrote:
snip
+
+struct gsbi_dev {
+ struct device *dev;
+ void __iomem*base;
You don't really need these.
Old habits die hard. I'll remove.
snip
+ if (of_property_read_u32(node, qcom,mode, mode)) {
+
Add device tree binding support for the QCOM GSBI driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 78
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.
Signed-off-by: Andy Gross agr
Add placeholder Kconfig and linkage for driver/soc.
The first patch set that implemented this was authored by Santosh Shilimkar:
https://lkml.org/lkml/2014/2/28/567
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/Kconfig |2 ++
drivers/Makefile|4
drivers/soc
On Fri, Apr 18, 2014 at 02:01:19AM +0300, Stanimir Vabanov wrote:
snip
static const struct of_device_id bam_of_match[] = {
+ { .compatible = qcom,bam-v1.3.0, },
{ .compatible = qcom,bam-v1.4.0, },
you could use the of_device_id::data field to switch between different
Add the device tree binding support for the v1.3.0 version of the QCOM BAM DMA
driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree
different offsets and multipliers that are
specific to that version of the IP block.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add v1.3.0 driver support
dmaengine: qcom_bam_dma: Add binding for v1.3.0
.../devicetree/bindings/dma/qcom_bam_dma.txt |4 +-
drivers/dma/qcom_bam_dma.c
registers changed
as well.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/qcom_bam_dma.c | 177
1 file changed, 114 insertions(+), 63 deletions(-)
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
index 82c9231..02f7fef
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm IPQ8064 platform.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/pinctrl/Kconfig |8 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-ipq8064.c | 653
ARCH_QCOM
platforms. This allows for selection of pinctrl support via a make menuconfig.
Andy Gross (3):
pinctrl: qcom: Add definitions for IPQ8064
dt: Document Qualcomm IPQ8064 pinctrl binding
ARM: qcom: Select PINCTRL by default for ARCH_QCOM
.../bindings/pinctrl/qcom,ipq8064
Add missing PINCTRL selection. This enables selection of pinctrollers for
Qualcomm processors.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/mach-qcom/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the
IPQ8064.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../bindings/pinctrl/qcom,ipq8064-pinctrl.txt | 95
1 file changed, 95 insertions(+)
create mode 100644
Documentation/devicetree
supports FIFO mode (for low bandwidth applications) and block mode (interrupt
generated for each block-size data transfer).
snip
Looks good.
Reviewed-by: Andy Gross agr...@codeaurora.org
--
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
On Sat, Mar 08, 2014 at 12:29:49AM +0200, Stanimir Vabanov wrote:
+#define BAM_IRQ_SRCS_EE(pipe) (0x0800 + ((pipe) * 0x80))
+#define BAM_IRQ_SRCS_MSK_EE(pipe) (0x0804 + ((pipe) * 0x80))
s/pipe/ee ?
Ah good catch. I'll fix that.
+struct bam_chan {
+ struct
On Mon, Mar 03, 2014 at 09:38:03AM +, Shevchenko, Andriy wrote:
snip
+ if (IS_ERR(bdev-bamclk))
+ return PTR_ERR(bdev-bamclk);
+
+ ret = clk_prepare_enable(bdev-bamclk);
+ if (ret) {
+ dev_err(bdev-dev, failed to prepare/enable clock\n);
+
in favor of standard types.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add device tree binding
dmaengine: add Qualcomm BAM dma driver
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41 +
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
On Wed, Feb 26, 2014 at 06:51:55PM +0200, Stanimir Varbanov wrote:
+ /* read revision and configuration information */
+ val = readl_relaxed(bdev-regs + BAM_REVISION) NUM_EES_MASK;
+
The ees shit is not zero and you got wrong ee. Could you add the line
below or something similar:
On Tue, Feb 25, 2014 at 08:07:13AM -0800, Bjorn Andersson wrote:
[snip]
The v2 model will get BAM (DMAEngine) support soon, v1 uses an
older DMA core. So there's a difference. I'm not aware what differences
there are between 2.1.1 and 2.2.1.
Difference between 2.1.1 and 2.2.1:
- high speed
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add device tree binding
dmaengine: add Qualcomm BAM dma driver
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
On Fri, Feb 21, 2014 at 09:26:57AM +, Mark Rutland wrote:
On Fri, Feb 21, 2014 at 06:43:04AM +, Andy Gross wrote:
Add device tree binding support for the QCOM BAM DMA driver.
[snip]
+Required properties:
+- compatible: Must be qcom,bam-v1.4.0 for MSM8974 V1
On Fri, Feb 21, 2014 at 09:33:52AM +, Mark Rutland wrote:
On Fri, Feb 21, 2014 at 06:43:05AM +, Andy Gross wrote:
[snip]
+ bdev-bamclk = devm_clk_get(bdev-dev, bam_clk);
The binding document should describe the bam_clk string in the
clock-names description.
OK
On Fri, Feb 21, 2014 at 05:36:47PM +, Mark Rutland wrote:
[snip]
Yes only a single interrupt. I can remove the s.
Please don't, the interrupts proeprty is standard and shouldn't change.
I was only asking to ensure that all interrupts were described in the
binding, which they are.
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
and returns residuals
- Removed proprietary slave config. Removed associated include file.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 48
1 file changed, 48 insertions(+)
create mode 100644
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