t for
> > > Xilinx NWL PCIe Host Controller
> > >
> > > [+cc Marc for irq_dispose_mapping() question]
> > >
> > > On Thu, Dec 10, 2015 at 02:10:34PM +, Bharat Kumar Gogada wrote:
> > > I'm trying to figure out what the difference is between th
Xilinx NWL PCIe Host Controller
> >
> > [+cc Marc for irq_dispose_mapping() question]
> >
> > On Thu, Dec 10, 2015 at 02:10:34PM +, Bharat Kumar Gogada wrote:
> > I'm trying to figure out what the difference is between these two
> > checks and why you have both
> Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
> > +
> It's a bit sloppy here to return 0, 1, or -EINVAL from a function declared to
> return "bool". A bool function should return "true" or "false".
>
> I think the best thing is to split this
> Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> [+cc Marc for irq_dispose_mapping() question]
>
> On Thu, Dec 10, 2015 at 02:10:34PM +0000, Bharat Kumar Gogada wrote:
> I'm trying to figure out what the difference
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes for v11:
-> Changed data types of bridge, pcie con
> Subject: Re: [PATCH v10] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> On Friday 27 November 2015 20:32:03 Bharat Kumar Gogada wrote:
> > + do {
> > + err = nwl_pcie_link_up(pcie, PHY_RDY_LINKUP);
> >
> Subject: Re: [PATCH v10] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> On 27/11/15 15:02, Bharat Kumar Gogada wrote:
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > Signed-off-by: Bharat Kumar Gogada <bh
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes for v10:
-> Changed MSI address to PCIe contro
> Subject: Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> On Wed, 25 Nov 2015 05:40:49 +0000
> Bharat Kumar Gogada <bharat.kumar.gog...@xilinx.com> wrote:
>
> > > On Thu, 19 Nov 2015 11:05:23 +0530
> >
> On Thu, 19 Nov 2015 11:05:23 +0530
> Bharat Kumar Gogada <bharat.kumar.gog...@xilinx.com> wrote:
>
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
> > Signed-off
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes for v9:
- Modified logic in nwl_irq_domain_alloc to
>
> On Tue, 17 Nov 2015 04:59:39 +0000
> Bharat Kumar Gogada <bharat.kumar.gog...@xilinx.com> wrote:
>
> > > On 11/16/2015 7:14 AM, Marc Zyngier wrote:
> > > > On 11/11/15 06:33, Bharat Kumar Gogada wrote:
> > > >> Addi
> Subject: Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
>
>
> On 11/17/2015 5:55 AM, Marc Zyngier wrote:
> > On 17/11/15 13:27, Bharat Kumar Gogada wrote:
> >>>
> >>> On Tue, 17 Nov 2015 04:59:39 +
> On Wed, Nov 11, 2015 at 12:03:39PM +0530, Bharat Kumar Gogada wrote:
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
> > Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.c
> On 11/16/2015 7:14 AM, Marc Zyngier wrote:
> > On 11/11/15 06:33, Bharat Kumar Gogada wrote:
> >> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >>
> >> Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
> >> Sign
> On 11/10/2015 10:33 PM, Bharat Kumar Gogada wrote:
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
> > Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
> > ---
> On Wed, 11 Nov 2015 12:03:39 +0530
> Bharat Kumar Gogada <bharat.kumar.gog...@xilinx.com> wrote:
>
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
> > Signed-off
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
---
Added logic to allocate contiguous hwirq in nwl_irq_domain_alloc function.
Moved MSI functionality
>
> >> Also, you still lack support for MSI-X (which would come for free...).
> >
> > We don't support MSI-X in root port mode.
>
> I don't believe you. If you support single MSI, you support MSI-X (because
> that's mostly a property of the endpoint).
In our architecture specification MSI-X is
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
---
Removed msi_controller and added irq_domian for MSI domain hierarchy.
Modified code for filling MSI addre
> > Without #ifdefs if we compile driver for legacy, MSI structures will not be
> available and we get compile time error.
>
> Sorry for nitpicking but at least can we use elegant version of #ifdefs .i.e.
> #if
> IS_ENABLED() here ?
>
Since IS_ENABLED() is checked at runtime, compile time error
> > +static struct msi_domain_info nwl_msi_domain_info = {
> > + .flags = (MSI_FLAG_USE_DEF_DOM_OPS |
> MSI_FLAG_USE_DEF_CHIP_OPS |
> > + MSI_FLAG_MULTI_PCI_MSI),
>
> If you're supporting multi-MSI, how do you ensure that all hwirqs are
> contiguous as required by the spec? Clearly,
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
---
Changes for v6:
Removed repetitive code for msi handlers.
Corrected typo mistakes in device tree d
> On Mon, Oct 26, 2015 at 08:26:26PM +0530, Bharat Kumar Gogada wrote:
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> > +
> > + while ((status = nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO)) !=
> 0) {
> > +
> > + device_type = "pci";
> > + interrupt-parent = <>;
> > + interrupts = < 0 118 4
> > + 0 116 4
> > + 0 115 4 // MSI_1 [63...32]
> > + 0 114 4 >; // MSI_0 [31...0]
>
> Better write these as tuples:
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
---
Corrected device tree node name.
Made tuples for interrupts, interrupt-map, reg properties.
Adde
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
---
Added MSI domain implementation for handling MSI interrupts
Added implementation for chained irq handlers
> On 09/10/15 06:11, Bharat Kumar Gogada wrote:
> >>>> +struct nwl_msi { /* struct nwl_msi - MSI information
> >> */
> >>>> + struct msi_controller chip; /* chip: MSI controller */
> >>>
> >>>> We're moving
> Hi Bharat,
>> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > +/* SSPL ERROR */
> > +#define SLVERR 0x02
> > +#define DECERR 0x03
> > +
> > +struct nwl_msi { /* struct nwl_msi - MSI
On 06/10/15 17:27, Bharat Kumar Gogada wrote:
> Subject: Re: [PATCH v3] PCI: Xilinx-NWL-PCIe: Added support for Xilinx
> NWL PCIe Host Controller
[...]
>> +struct nwl_msi {/* struct nwl_msi - MSI information */
>> +struct msi_controller chip; /* ch
> >> +struct nwl_msi { /* struct nwl_msi - MSI information
> */
> >> + struct msi_controller chip; /* chip: MSI controller */
> >
> >> We're moving away from msi_controller altogether, as the kernel now
> >> has all the necessary infrastructure to do this properly.
> >
> >
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
---
Added interrupt-map, interrupt-map-mask properties
---
.../devicetree/bindings/pci/xilinx-nwl-pcie.t
Subject: Re: [PATCH v3] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe
Host Controller
Hi Bharat,
On 06/10/15 16:44, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com&g
On Thursday 01 October 2015 14:29:21 Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
> ---
> Removed un
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com>
---
Removed unneccessary comments
Modified setup_sspl implementation
Added more details in binding D
Ping!
-Original Message-
From: Bharat Kumar Gogada [mailto:bharat.kumar.gog...@xilinx.com]
Sent: Thursday, August 27, 2015 5:14 PM
To: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; Michal Simek; Soren
Brinkmann; bhelg
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada bhara...@xilinx.com
Signed-off-by: Ravi Kiran Gummaluri rgum...@xilinx.com
---
.../devicetree/bindings/pci/xilinx-nwl-pcie.txt| 39 +
drivers/pci/host/Kconfig |9
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