From: Carlo Caione <ca...@endlessm.com>
Add support for the ARM TWD Timer and Watchdog to the Amlogic Meson8b
device tree.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/boot/dts/meson8b.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/
On Wed, Dec 2, 2015 at 4:30 PM, Rob Herring <r...@kernel.org> wrote:
> On Tue, Dec 01, 2015 at 05:24:21PM +0100, Carlo Caione wrote:
>> From: Carlo Caione <ca...@endlessm.com>
>>
>> Extend the pinctrl binding documentation with the support for external
>
From: Carlo Caione <ca...@endlessm.com>
This adds the necessary SMP-operations and startup code to use the
additional cores on the Amlogic Meson8b SoCs.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/Makefile | 1 +
arch/arm/mach-meson/Kconfig | 1
From: Carlo Caione <ca...@endlessm.com>
Add nodes for: SCU, PMU and SRAM. Set also the enable-method for SMP
bringup.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/boot/dts/meson8b.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/a
From: Carlo Caione <ca...@endlessm.com>
The clock controller on Amlogic Meson8b SoCs has been extended with a
reset controller used to reset the CPU cores. It is used during SMP
bringup.
With this patch we extend the clock controller documentation.
Signed-off-by: Carlo Caio
From: Carlo Caione <ca...@endlessm.com>
With this patch we add documentation for:
* power-management-unit: the PMU is used to bring up the cores during
SMP operations
* sram: among other things the sram is used to store the first code
executed by the core when it is powered up
* cpu-
From: Carlo Caione <ca...@endlessm.com>
This patch extends the L2 cache controller node for Amlogic Meson8b
SoCs with some missing parameters.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/boot/dts/meson8b.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/a
From: Carlo Caione <ca...@endlessm.com>
In the Amlogic Meson8b SoC we need to soft reset the CPU cores during
the boot to enable the SMP support. With this patch we extend the clock
controller adding a small reset controller in charge of resetting the
cores.
Signed-off-by: Carlo Caio
From: Carlo Caione <ca...@endlessm.com>
Extend the CPU nodes to use the reset controller.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/boot/dts/meson8b.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/
From: Carlo Caione <ca...@endlessm.com>
This patchset adds SMP support for Amlogic Meson8b SoCs.
Patch 1 fix some paramater for L2 cache needed for SMP.
Patches 2-4 add a small reset controller used to reset the CPU cores at boot.
Patches 5-7 deal with the SMP code itself.
Changelo
On Tue, Dec 1, 2015 at 8:16 PM, Marc Zyngier <marc.zyng...@arm.com> wrote:
> On 01/12/15 16:24, Carlo Caione wrote:
>> From: Carlo Caione <ca...@endlessm.com>
>> +static int meson_irq_domain_alloc(struct irq_domain *domain, unsigned int
>> irq,
>> +
On lun, nov 23, 2015 at 05:47:20 -0600, Rob Herring wrote:
> On Mon, Nov 23, 2015 at 11:16:55AM +0100, Carlo Caione wrote:
> > From: Carlo Caione <ca...@endlessm.com>
> >
> > Extend the pinctrl binding documentation with the support for external
> > GPIO interrup
From: Carlo Caione <ca...@endlessm.com>
On Meson8 and Meson8b SoCs there are 8 independent filtered GPIO
interrupt modules that can be programmed to use any of the GPIOs in the
chip as an interrupt source.
For each GPIO IRQ we have:
GPIOs --> [mux]--> [polarity]--> [filter]-
From: Carlo Caione <ca...@endlessm.com>
meson_get_domain_and_bank() and meson_map_resource() are not static
anymore.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
drivers/pinctrl/meson/pinctrl-meson.c | 10 +-
drivers/pinctrl/meson/pinctrl-meson.h | 7 +++
2 f
From: Carlo Caione <ca...@endlessm.com>
of_irq_find_parent was made static since it had no users outside of
of_irq.c. Export it again since we are going to use it again.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
drivers/of/irq.c | 3 ++-
include/linux/of_irq.h |
From: Carlo Caione <ca...@endlessm.com>
This patch extends the pinctrl SoC specific data adding two new
information: IRQ register and last pin number in the SoC.
These two numbers are used in the GPIO IRQ controller.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
drivers/p
From: Carlo Caione <ca...@endlessm.com>
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/boot/dts/meson8b.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index ee352bf..dd7ccd3 100644
--- a/a
From: Carlo Caione <ca...@endlessm.com>
Extend the pinctrl binding documentation with the support for external
GPIO interrupts.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
Signed-off-by: Beniamino Galvani <b.galv...@gmail.com>
---
Documentation/devicetree/bindings/pinctrl
From: Carlo Caione <ca...@endlessm.com>
In Meson SoCs we have 8 independent GPIO interrupts that can be programmed to
use any of the GPIOs in the chip as interrupt source.
These GPIOs are managed by GIC but they can be conditioned (and enabled) by
some registers external to the GIC.
On Tue, Nov 24, 2015 at 10:04 AM, Carlo Caione <ca...@caione.org> wrote:
> On Tue, Nov 24, 2015 at 9:28 AM, Marc Zyngier <marc.zyng...@arm.com> wrote:
>> [...]
>>
>>> + for (i = 0; i < pc->num_gic_irqs; i++) {
>
On Thu, Nov 26, 2015 at 5:27 PM, Marc Zyngier <marc.zyng...@arm.com> wrote:
> On Tue, 24 Nov 2015 10:04:50 +0100
> Carlo Caione <ca...@caione.org> wrote:
>
>> On Tue, Nov 24, 2015 at 9:28 AM, Marc Zyngier <marc.zyng...@arm.com> wrote:
>> > On Mon, 23 Nov
On Tue, Nov 24, 2015 at 9:28 AM, Marc Zyngier <marc.zyng...@arm.com> wrote:
> On Mon, 23 Nov 2015 11:16:54 +0100
> Carlo Caione <ca...@caione.org> wrote:
>
>> From: Carlo Caione <ca...@endlessm.com>
>>
>> On Meson8 and Meson8b SoCs there are 8 i
From: Carlo Caione <ca...@endlessm.com>
Export of_phandle_args_to_fwspec with a new compliant name.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
include/linux/of_irq.h | 2 ++
kernel/irq/irqdomain.c | 5 +++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/i
From: Carlo Caione <ca...@endlessm.com>
On Meson8 and Meson8b SoCs there are 8 independent filtered GPIO
interrupt modules that can be programmed to use any of the GPIOs in the
chip as an interrupt source.
For each GPIO IRQ we have:
GPIOs --> [mux]--> [polarity]--> [filter]-
From: Carlo Caione <ca...@endlessm.com>
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/boot/dts/meson8b.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index ee352bf..3c0ae45 100644
--- a/a
From: Carlo Caione <ca...@endlessm.com>
Extend the pinctrl binding documentation with the support for external
GPIO interrupts.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
Signed-off-by: Beniamino Galvani <b.galv...@gmail.com>
---
Documentation/devicetree/bindings/pinctrl
From: Carlo Caione <ca...@endlessm.com>
In Meson SoCs we have 8 independent GPIO interrupts that can be programmed to
use any of the GPIOs in the chip as interrupt source.
These GPIOs are managed by GIC but they can be conditioned (and enabled) by
some registers external to the GIC.
From: Carlo Caione <ca...@endlessm.com>
of_irq_find_parent was made static since it had no users outside of
of_irq.c. Export it again since we are going to use it again.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
drivers/of/irq.c | 2 +-
include/linux/of_irq.h |
From: Carlo Caione <ca...@endlessm.com>
This patch extends the L2 cache controller node for Amlogic Meson8b
SoCs with some missing parameters.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/boot/dts/meson8b.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/a
From: Carlo Caione <ca...@endlessm.com>
The clock controller on Amlogic Meson8b SoCs has been extended with a
reset controller used to reset the CPU cores. It is used during SMP
bringup.
With this patch we extend the clock controller documentation.
Signed-off-by: Carlo Caio
From: Carlo Caione <ca...@endlessm.com>
This patchset adds SMP support for Amlogic Meson8b SoCs.
Patch 1 fix some paramater for L2 cache needed for SMP.
Patches 2-4 add a small reset controller used to reset the CPU cores at boot.
Patches 5-7 deal with the SMP code itself.
Carlo Cai
From: Carlo Caione <ca...@endlessm.com>
In the Amlogic Meson8b SoC we need to soft reset the CPU cores during
the boot to enable the SMP support. With this patch we extend the clock
controller adding a small reset controller in charge of resetting the
cores.
Signed-off-by: Carlo Caio
From: Carlo Caione <ca...@endlessm.com>
Add nodes for: SCU, PMU and SRAM. Set also the enable-method for SMP
bringup.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/boot/dts/meson8b.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/a
From: Carlo Caione <ca...@endlessm.com>
This adds the necessary SMP-operations and startup code to use the
additional cores on the Amlogic Meson8b SoCs.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/mach-meson/Kconfig | 1 +
arch/arm/mach-meson/Makefile | 1
From: Carlo Caione <ca...@endlessm.com>
Extend the CPU nodes to use the reset controller.
Signed-off-by: Carlo Caione <ca...@endlessm.com>
---
arch/arm/boot/dts/meson8b.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/
From: Carlo Caione <ca...@endlessm.com>
With this patch we add documentation for:
* power-management-unit: the PMU is used to bring up the cores during
SMP operations
* sram: among other things the sram is used to store the first code
executed by the core when it is powered up
* cpu-
to you on Oct 12.
I was waiting for a resubmission without the added copyright but I'll
modify it myself and I'll push a PR.
Cheers,
--
Carlo Caione
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s
> +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
> @@ -1,6 +1,8 @@
> /*
> * Copyright 2015 Endless Mobile, Inc.
> * Author: Carlo Caione <ca...@endlessm.com>
> + * Copyright 2015 Codethink Ltd.
> + * Author: Edward Cragg <edward.cr...@codethink.co.uk>
Usually we do no
anymore)
Acked-by: Carlo Caione ca...@caione.org
--
Carlo Caione
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diff --git a/MAINTAINERS b/MAINTAINERS
index 0662378..f1bc045 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -850,6 +850,7 @@ ARM/Amlogic MesonX SoC support
M: Carlo Caione ca...@caione.org
L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
S: Maintained
+F
;
+};
--
1.9.1
Tested-by: Carlo Caione ca...@caione.org
Thanks,
--
Carlo Caione
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don't take DTS patches. They should go via arm-soc. Please say
so if there are reasons I should take it.
I'll take them.
--
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The board DTS is missing the machine compatible.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/meson6-atv1200.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts
b/arch/arm/boot/dts/meson6-atv1200.dts
index dc2541f
On lun, ott 20, 2014 at 05:40:11 +0200, Philipp Zabel wrote:
Am Montag, den 20.10.2014, 13:19 +0200 schrieb Carlo Caione:
Hi Philipp,
from the documentation and the sources I have, it seems that in the register
together with the bits for resetting the ICs there are also bits for turning
This patch adds support for the reset controller found on the Amlogic
MesonX SoCs. For several devices in the AO (Always-On) power domain, it
is possible to reset them by programming a specific bit in a register.
Signed-off-by: Carlo Caione ca...@caione.org
---
Hi Philipp,
from
by Amlogic it
seems that at least two IPs use this register for reset: RTC and UART. Since I
need it to reset the RTC, I wrote this small driver.
v3:
* few changes at comments
* removed register offset
v2:
* removed useless comment
* added platform_get_drvdata
* removed owner field
Carlo Caione
Add the node for the reset controller in the DTSI.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/meson.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..1ca864e 100644
--- a/arch/arm/boot
Signed-off-by: Carlo Caione ca...@caione.org
---
.../bindings/reset/amlogic,meson6-rst-mgr-ao.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/amlogic,meson6-rst-mgr-ao.txt
diff --git
a/Documentation/devicetree
On Mon, Oct 20, 2014 at 01:19:42PM +0200, Carlo Caione wrote:
Apparently several IPs found in the MesonX SoCs can be reset by programming a
specific bit in a register in the so called AO (Always-On) domain. From the
documentation released by Amlogic under NDA it is not clear which devices can
On Wed, Oct 15, 2014 at 12:36 AM, Philipp Zabel p...@pengutronix.de wrote:
Hi Carlo,
Hi Philipp,
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2014 Carlo Caione ca...@caione.org
+ *
+ * based on
+ * Steffen Trumtrar Reset Controller driver
That doesn't sound right. Do you mean socfpga-reset?
Yes
by Amlogic it
seems that at least two IPs use this register for reset: RTC and UART. Since I
need it to reset the RTC, I wrote this small driver.
v2:
* removed useless comment
* added platform_get_drvdata
* removed owner field
Carlo Caione (3):
ARM: meson: reset: Add reset controller for MesonX
Signed-off-by: Carlo Caione ca...@caione.org
---
.../bindings/reset/amlogic,meson6-rst-mgr-ao.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/amlogic,meson6-rst-mgr-ao.txt
diff --git
a/Documentation/devicetree
Add the node for the reset controller in the DTSI.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/meson.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..1ca864e 100644
--- a/arch/arm/boot
This patch adds support for the reset controller found on the Amlogic
MesonX SoCs. For several devices in the AO (Always-On) power domain, it
is possible to reset them by programming a specific bit in a register.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers/reset/Makefile | 1
On Mon, Oct 13, 2014 at 12:13 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Sun, Oct 12, 2014 at 08:20:24PM +0100, Carlo Caione wrote:
Fix the compatible for the UART to make it consistent with the other
compatibles for Meson6 and Meson8 and to avoid problems when the
meson8b
Signed-off-by: Carlo Caione ca...@caione.org
---
.../bindings/reset/amlogic,meson6-rst-mgr-ao.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/amlogic,meson6-rst-mgr-ao.txt
diff --git
a/Documentation/devicetree
This patch adds support for the reset controller found on the Amlogic
MesonX SoCs. For several devices in the AO (Always-On) power domain, it
is possible to reset them by programming a specific bit in a register.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers/reset/Makefile | 1
Add the node for the reset controller in the DTSI.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/meson.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..1ca864e 100644
--- a/arch/arm/boot
by Amlogic it
seems that at least two IPs use this register for reset: RTC and UART. Since I
need it to reset the RTC, I wrote this small driver.
Carlo Caione (3):
ARM: meson: reset: Add reset controller for MesonX SoCs
ARM: meson: DTSI: Enable reset controller
ARM: meson: docs: Add docs
= THIS_MODULE,
I believe you can drop the owner field.
I will.
Thank you for your review,
--
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Fix the compatible for the UART to make it consistent with the other
compatibles for Meson6 and Meson8 and to avoid problems when the
meson8b will be introduced with a different UART driver.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/meson.dtsi| 8
drivers
On Sun, Oct 5, 2014 at 11:59 PM, Beniamino Galvani b.galv...@gmail.com wrote:
Hi,
this patchset introduces support for Amlogic Meson8, which is a family
of quad-core Cortex-A9 SoCs used in tablets and set-top boxes.
For the whole patchset
Acked-by: Carlo Caione ca...@caione.org
--
Carlo
to MACH_MESON?
I would still leave two different MACH_ for meson6 and meson8 since the
two architectures aren't _so_ similar.
thanks,
--
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On Thu, Sep 11, 2014 at 11:25 PM, Greg KH gre...@linuxfoundation.org wrote:
On Thu, Sep 11, 2014 at 10:11:34PM +0200, Carlo Caione wrote:
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
which cannot
Signed-off-by: Carlo Caione ca...@caione.org
---
.../devicetree/bindings/timer/amlogic,meson6-timer.txt | 16
1 file changed, 16 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
diff --git a/Documentation/devicetree/bindings
: deleted useless compatibles and .init_machine
* DTS: addressed several issues
* defconfigs: deleted meson_defconfig
* documentation: split documentation patch and added bindings documentation
Carlo Caione (9):
ARM: meson: debug: add debug UART for earlyprintk support
ARM: meson: documentation: add
This patch updates the multi_v7_defconfig with the CONFIG_* needed by
the just added Meson anch. It also adds a new defconfig specifically for
the Meson SoCs.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git
Signed-off-by: Carlo Caione ca...@caione.org
---
.../devicetree/bindings/serial/amlogic,meson-uart.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
diff --git a/Documentation/devicetree/bindings
Add vendor prefixes and basic documentation for MesonX SoCs bindings
Signed-off-by: Carlo Caione ca...@caione.org
---
Documentation/devicetree/bindings/arm/amlogic.txt | 8
Documentation/devicetree/bindings/arm/geniatech.txt | 5 +
Documentation/devicetree/bindings/vendor
Add the UART definitions needed to support earlyprintk for MesonX SoCs
on UARTAO.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/Kconfig.debug | 14 --
arch/arm/include/debug/meson.S | 35 +++
2 files changed, 47 insertions(+), 2
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
which cannot be powered off.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers/tty/serial/Kconfig | 18 ++
drivers/tty/serial/Makefile
This patch adds the basic machine file for the MesonX SoCs. Only Meson6
is populated.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/Kconfig | 2 ++
arch/arm/Makefile| 1 +
arch/arm/mach-meson/Kconfig | 13 +
arch/arm/mach-meson/Makefile | 1
Meson6 SoCs are equipped with 5 32-bit timers, called TIMER_A, TIMER_B,
TIMER_C, TIMER_D and TIMER_E.
The driver is providing clocksource support for the 32-bit counter using
TIMER_E. Clockevents are also supported using TIMER_A.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers
@@
+/*
+ * Copyright 2014 Carlo Caione ca...@caione.org
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version
On dom, ago 17, 2014 at 12:49:49 +0200, Carlo Caione wrote:
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
which cannot be powered off.
Signed-off-by: Carlo Caione ca...@caione.org
---
Ping
On sab, set 06, 2014 at 11:38:34 -0700, Greg KH wrote:
On Sat, Sep 06, 2014 at 08:28:04PM +0200, Carlo Caione wrote:
On dom, ago 17, 2014 at 12:49:49 +0200, Carlo Caione wrote:
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B
On Sun, Aug 17, 2014 at 12:49:49PM +0200, Carlo Caione wrote:
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
which cannot be powered off.
Signed-off-by: Carlo Caione ca...@caione.org
---
cut
Hi
On lun, ago 18, 2014 at 05:27:26 +0100, Mark Rutland wrote:
On Sun, Aug 17, 2014 at 11:49:50AM +0100, Carlo Caione wrote:
+enum {
+ A = 0,
+ B,
+ C,
+ D,
+};
That's a very terse set of enum names. I would recomment something a
little longer.
Any reason for missing E
On Mon, Aug 18, 2014 at 05:17:44PM +0100, Mark Rutland wrote:
On Sun, Aug 17, 2014 at 11:49:52AM +0100, Carlo Caione wrote:
cut
+ soc@c810 {
What's the unit-address for? This node doesn't have a reg or compatible.
I used it to indicate the starting address of the memory mapped
such empty machines?
I can get rid of the .init_machine but what about the .dt_compat field?
Thanks,
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Carlo Caione
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On Mon, Aug 18, 2014 at 12:31:22PM +0200, Matthias Brugger wrote:
On 17/08/14 12:49, Carlo Caione wrote:
This patch updates the multi_v7_defconfig with the CONFIG_* needed by
the just added Meson anch. It also adds a new defconfig specifically for
the Meson SoCs.
Signed-off-by: Carlo
On Mon, Aug 18, 2014 at 12:36:47PM +0200, Matthias Brugger wrote:
On 17/08/14 12:49, Carlo Caione wrote:
New UART and timer bindings are documented. A new vendor is added to the
vendors list.
Signed-off-by: Carlo Caione ca...@caione.org
---
.../devicetree/bindings/serial/amlogic
On Mon, Aug 18, 2014 at 01:59:38PM +0200, Matthias Brugger wrote:
On 17/08/14 12:49, Carlo Caione wrote:
+enum {
+A = 0,
+B,
+C,
+D,
+};
You are just using timer A, so this enum is unnecessary. Please use
a define instead. Also it would be better, if the define would
code released at:
http://openlinux.amlogic.com:8000/download/
Carlo Caione (7):
ARM: meson: debug: add debug UART for earlyprintk support
ARM: meson: serial: add MesonX SoC on-chip uart driver
ARM: meson6: clocksource: add Meson6 timer support
ARM: meson: add basic support for MesonX SoCs
New UART and timer bindings are documented. A new vendor is added to the
vendors list.
Signed-off-by: Carlo Caione ca...@caione.org
---
.../devicetree/bindings/serial/amlogic,meson-uart.txt | 17 +
.../devicetree/bindings/timer/amlogic,meson6-timer.txt | 16
This patch updates the multi_v7_defconfig with the CONFIG_* needed by
the just added Meson anch. It also adds a new defconfig specifically for
the Meson SoCs.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/configs/meson_defconfig| 99 +
arch/arm
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
which cannot be powered off.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers/tty/serial/Kconfig | 18 ++
drivers/tty/serial/Makefile
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/Kconfig | 2 ++
arch/arm/Makefile| 1 +
arch/arm/mach-meson/Kconfig | 13 +
arch/arm/mach-meson/Makefile | 1 +
arch/arm/mach-meson/meson.c | 36
5 files changed
Meson6 SoCs are equipped with 5 32-bit timers, called TIMER_A, TIMER_B,
TIMER_C, TIMER_D and TIMER_E.
The driver is providing clocksource support for the 32-bit counter using
TIMER_E. Clockevents are also supported using TIMER_A.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers
Add the UART definitions needed to support earlyprintk for MesonX SoCs
on UARTAO.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/Kconfig.debug | 14 --
arch/arm/include/debug/meson.S | 35 +++
2 files changed, 47 insertions(+), 2
@@
+/*
+ * Copyright 2014 Carlo Caione ca...@caione.org
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version
for noticing.
I will fix it in v2.
Thank you,
--
Carlo Caione
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Meson6 and Meson8. If this is confirmed in v2 I can make a
generic clocksource/clockevents driver for both the architectures.
Thanks,
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Carlo Caione
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of this?
If it's easier for you to keep the syscon at the moment for whateever
driver you're working on before submitting it, I'm fine with it, but
I'm not going to merge it right now either.
It's fine with me.
Thank you for your review,
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On Wed, May 7, 2014 at 5:25 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, May 06, 2014 at 10:03:19AM +0200, Carlo Caione wrote:
On Tue, May 6, 2014 at 8:36 AM, Chen-Yu Tsai w...@csie.org wrote:
Hi,
Hi,
On Tue, May 6, 2014 at 6:55 AM, Maxime Ripard
maxime.rip...@free
On Tue, May 6, 2014 at 8:36 AM, Chen-Yu Tsai w...@csie.org wrote:
Hi,
Hi,
On Tue, May 6, 2014 at 6:55 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, May 04, 2014 at 04:02:38PM +0200, Carlo Caione wrote:
The so called system controller in Allwinner A20 and A31 SoCs
around :)
Thanks,
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Carlo Caione
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Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/configs/sunxi_defconfig| 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index d4e8a47..d04fef5 100644
--- a/arch
the proper nodes in the DTS files and enable the syscon
in the defconfig files.
Even though the system controller includes also register for managing the
NMI controller, these register are not mapped in the syscon since they
are directly used and mapped by the NMI controller itself.
Carlo Caione (2
This patch adds the proper nodes in the DTSI files for Allwinner
A20 and A31.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 5 +
arch/arm/boot/dts/sun7i-a20.dtsi | 5 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
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