On Fri, Nov 20, 2015 at 3:47 AM, Jassi Brar wrote:
> On Mon, Nov 9, 2015 at 11:35 PM, Duc Dang wrote:
>> X-Gene mailbox controller provides 8 mailbox channels, with
>> each channel has a dedicated interrupt line.
>>
>> [dhdang: rebase over 4.3-rc5, some minor changes
On Mon, Nov 9, 2015 at 10:05 AM, Duc Dang wrote:
> APM X-Gene SoC has a mailbox controller that provides
> communication mechanism for X-Gene Arm64 cores to communicate
> with X-Gene SoC's Cortex M3 (SLIMpro) processor.
>
> X-Gene mailbox controller provides 8 mailbox c
On Tue, Nov 10, 2015 at 6:15 AM, Rob Herring wrote:
> On Mon, Nov 09, 2015 at 10:05:44AM -0800, Duc Dang wrote:
>> This adds the APM X-Gene SLIMpro mailbox device tree
>> node documentation.
>>
>> [dhdang: rebase over 4.3-rc5]
>> Signed-off-by: Fen
This adds the APM X-Gene SLIMpro mailbox device tree
node documentation.
[dhdang: rebase over 4.3-rc5]
Signed-off-by: Feng Kan
Signed-off-by: Duc Dang
---
.../bindings/mailbox/xgene-slimpro-mailbox.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
X-Gene mailbox controller provides 8 mailbox channels, with
each channel has a dedicated interrupt line.
[dhdang: rebase over 4.3-rc5, some minor changes to
address comment in v2 patch set]
Signed-off-by: Feng Kan
Signed-off-by: Duc Dang
---
drivers/mailbox/Kconfig | 9
APM X-Gene SoC has a mailbox controller that provides
communication mechanism for X-Gene Arm64 cores to communicate
with X-Gene SoC's Cortex M3 (SLIMpro) processor.
X-Gene mailbox controller provides 8 mailbox channels, with
each channel has a dedicated interrupt line.
Changes since v2:
-
Mailbox device tree node for APM X-Gene platform.
[dhdang: rebase over 4.3-rc5]
Signed-off-by: Feng Kan
Signed-off-by: Duc Dang
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64
On Sun, Jul 26, 2015 at 11:37 AM, Olof Johansson wrote:
>
> On Sat, Jul 25, 2015 at 11:34:42AM -0700, Duc Dang wrote:
> > Hi Olof,
> >
> > We are debating whether we should setup a company server (where we can
> > have full control about storage, user permissions
On Sun, Jul 26, 2015 at 11:37 AM, Olof Johansson wrote:
> On Sat, Jul 25, 2015 at 11:34:42AM -0700, Duc Dang wrote:
>> Hi Olof,
>>
>> We are debating whether we should setup a company server (where we can
>> have full control about storage, user permissions, backup, ...
l requests are convenient for us, but if it's just a patch or two,
>>> sending them directly in email is fine as well.
>>
>> If there is an chance in pulling this power off/reset patches for
>> 4.2-rc4, can you pull in as patches? Otherwise, we will go the GIT
>>
On Tue, Jul 21, 2015 at 9:14 AM, Bjorn Helgaas wrote:
> On Thu, Jul 09, 2015 at 02:20:10PM -0700, Duc Dang wrote:
>> This patch set adds 1 large (up to 64GB) memory window for each PCIe
>> controller nodes in X-Gene device tree and fix PCIe controller driver
>> to handle m
On Thu, Jul 9, 2015 at 4:47 AM, Arnd Bergmann wrote:
>
> On Monday 06 July 2015 16:28:43 Duc Dang wrote:
> > On Tue, Jun 30, 2015 at 11:22 AM, Duc Dang wrote:
> > > This patch set adds 1 large (up to 64GB) memory window for each PCIe
> > > controller nodes in X
X-Gene PCIe controller has registers to support multiple memory ranges.
This patch implement addtional register configuration required for the
driver to support 1 additional huge 64-bit prefetch memory window.
Signed-off-by: Duc Dang
Signed-off-by: Tanmay Inamdar
---
drivers/pci/host/pci
This patch adds 1 additional window with large size (up to 64GB) for
X-Gene PCIe nodes to support devices that require huge BAR.
Each X-Gene PCIe node now will have 2 memory windows:1 non-prefetchable
32-bit window and 1 prefetchable 64-bit window.
Signed-off-by: Duc Dang
Signed-off-by: Tanmay
This patch set adds 1 large (up to 64GB) memory window for each PCIe
controller nodes in X-Gene device tree and fix PCIe controller driver
to handle multiple memory ranges correctly. These changes are required
to support PCIe devices that have huge BAR.
v3 changes:
1. Explicitly mention in
On Tue, Jun 30, 2015 at 11:22 AM, Duc Dang wrote:
> This patch set adds 1 large (up to 64GB) memory window for each PCIe
> controller nodes in X-Gene device tree and fix PCIe controller driver
> to handle multiple memory ranges correctly. These changes are required
> to support PCIe
X-Gene PCIe controller has registers to support multiple memory ranges.
This patch implement addtional register configuration required for the
driver to support 1 additional huge 64-bit prefetch memory window.
Signed-off-by: Duc Dang
Signed-off-by: Tanmay Inamdar
---
drivers/pci/host/pci
This patch set adds 1 large (up to 64GB) memory window for each PCIe
controller nodes in X-Gene device tree and fix PCIe controller driver
to handle multiple memory ranges correctly. These changes are required
to support PCIe devices that has huge BAR.
v2 changes:
1. Separate device-tree c
This patch adds 1 additional window with large size (up to 64GB) for
X-Gene PCIe nodes to support devices that require huge BAR.
Signed-off-by: Duc Dang
Signed-off-by: Tanmay Inamdar
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 23 ++-
1 file changed, 14 insertions(+), 9
On Fri, Jun 26, 2015 at 1:35 PM, Arnd Bergmann wrote:
> On Friday 26 June 2015 11:56:47 Duc Dang wrote:
>> Hi Arnd,
>>
>> On Fri, Jun 26, 2015 at 12:59 AM, Arnd Bergmann wrote:
>> > On Thursday 25 June 2015 18:05:56 Duc Dang wrote:
>> >> X-Gene PCIe co
Hi Arnd,
On Fri, Jun 26, 2015 at 12:59 AM, Arnd Bergmann wrote:
> On Thursday 25 June 2015 18:05:56 Duc Dang wrote:
>> X-Gene PCIe controllers support huge outbound BARs (with size upto
>> 64GB). This patch configures additional 1 outbound BAR for X-Gene
>> PCIe controllers
On Fri, Jun 26, 2015 at 7:26 AM, Bjorn Helgaas wrote:
> Hi Duc,
>
> On Thu, Jun 25, 2015 at 8:05 PM, Duc Dang wrote:
>> X-Gene PCIe controllers support huge outbound BARs (with size upto
>> 64GB). This patch configures additional 1 outbound BAR for X-Gene
>> PCIe c
X-Gene PCIe controllers support huge outbound BARs (with size upto
64GB). This patch configures additional 1 outbound BAR for X-Gene
PCIe controllers with size larger than 4GB. This is required to
support devices that request huge outbound memory (nVidia K40 as an
example)
Signed-off-by: Duc Dang
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