[PATCH v4 2/4] drivers: clk: st: PLL rate change implementation for DVFS

Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by: Pankaj Dev <pankaj@st.com> Signed-off-by: Gabriel Fernandez <gabri

Re: [PATCH v3 2/4] drivers: clk: st: PLL rate change implementation for DVFS

Hi Stephen, No there is no reason. I will fix it. Thanks for review. Best regards Gabriel On 6 October 2015 at 20:06, Stephen Boyd <sb...@codeaurora.org> wrote: > On 10/05, Gabriel Fernandez wrote: >> @@ -452,7 +651,7 @@ static const struct clk_ops st_pll1200c32_ops = { >&g

[PATCH v4 1/4] drivers: clk: st: Support for enable/disable in Clockgen PLLs

The patch adds support for enable/disable of the Clockgen PLLs. clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs. Signed-off-by: Pankaj Dev <pankaj@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org> --- drivers/clk/st/clkge

[PATCH v4 4/4] ARM: STi: DT: Add support for stih418 A9 pll

Add support for new PLL-type for stih418 A9-PLL. Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org> --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/s

[PATCH v5 0/3] PCI: st: provide support for dw pcie

on designware PCIe driver. Gabriel Fernandez (3): ARM: STi: Kconfig update for PCIe support PCI: st: Add Device Tree bindings for sti pcie PCI: st: Provide support for the sti PCIe controller Documentation/devicetree/bindings/pci/st-pcie.txt | 56 +++ MAINTAINERS

[PATCH v5 1/3] ARM: STi: Kconfig update for PCIe support

Update Kconfig: - MIGHT_HAVE_PCI - PCI_DOMAINS Signed-off-by: Fabrice Gasnier --- arch/arm/mach-sti/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 125865d..5f99e93 100644 ---

[PATCH v5 3/3] PCI: st: Provide support for the sti PCIe controller

sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier <fabrice.gasn...@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org> Reviewed-by: Pratyush Anand <pratyush.an...@gmail.com> --- MAINTAINERS | 1 + driver

[PATCH v5 2/3] PCI: st: Add Device Tree bindings for sti pcie

sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier <fabrice.gasn...@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org> --- Documentation/devicetree/bindings/pci/st-pcie.txt | 56 +++ 1 file changed, 5

[PATCH v3 3/4] drivers: clk: st: Correct the pll-type for A9 for stih418

Add support for new PLL-type for stih418 A9-PLL. Currently the 407_A9_PLL type being used, it is corrected with this patch 4600c28 PLL allows to reach higher frequencies so its programming algorithm is extended. Signed-off-by: Pankaj Dev <pankaj@st.com> Signed-off-by: Gabriel Fer

[PATCH v3 0/4] ST PLL improvement

' Gabriel Fernandez (4): drivers: clk: st: Support for enable/disable in Clockgen PLLs drivers: clk: st: PLL rate change implementation for DVFS drivers: clk: st: Correct the pll-type for A9 for stih418 ARM: STi: DT: Add support for stih418 A9 pll .../devicetree/bindings/clock/st/st,clkgen

[PATCH v3 1/4] drivers: clk: st: Support for enable/disable in Clockgen PLLs

The patch adds support for enable/disable of the Clockgen PLLs. clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs. Signed-off-by: Pankaj Dev <pankaj@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org> --- drivers/clk/st/clkge

[PATCH v3 2/4] drivers: clk: st: PLL rate change implementation for DVFS

Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by: Pankaj Dev <pankaj@st.com> Signed-off-by: Gabriel Fernandez <gabri

[PATCH v3 4/4] ARM: STi: DT: Add support for stih418 A9 pll

Add support for new PLL-type for stih418 A9-PLL. Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org> --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/s

Re: [PATCH v4 2/4] PCI: st: Add Device Tree bindings for sti pcie

Hi Rob, Thanks for the review. Best regards Gabriel On 28 August 2015 at 02:06, Rob Herring <robherri...@gmail.com> wrote: > On Thu, Aug 27, 2015 at 7:34 AM, Gabriel Fernandez > <gabriel.fernan...@linaro.org> wrote: >> sti pcie is built around a Synopsis Designware P

Re: [PATCH v4 3/4] PCI: st: Provide support for the sti PCIe controller

Hi Pratyush, Thanks for the review. Best regards Gabriel On 27 August 2015 at 19:31, Pratyush Anand <pratyush.an...@gmail.com> wrote: > Hi Gabriel, > > Looks good to me. > > On Thu, Aug 27, 2015 at 6:04 PM, Gabriel Fernandez > <gabriel.fernan...@linaro.org> wrot

Re: [PATCH v4 0/4] PCI: st: provide support for dw pcie

No problem Thanks Gabriel On 17 September 2015 at 16:59, Bjorn Helgaas <bhelg...@google.com> wrote: > Hi Gabriel, > > On Thu, Aug 27, 2015 at 02:34:13PM +0200, Gabriel Fernandez wrote: >> >> This patchset is based on v4.2-rc1 and is based on >> [PATCH v8 0/6]

[RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2

_cx_x") Gabriel Fernandez (2): dt-bindings: Fix tipo in st,clkgen-pll documentation drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++-- drivers/clk/st/clkgen-fsyn.c

[PATCH 1/2] dt-bindings: Fix tipo in st,clkgen-pll documentation

replace "sst,plls-c32-cx_x" by "st,plls-c32-cx_x" Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org> --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devic

[PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

Use a generic name for this kind of PLL Correction in dts files are already done here: commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x") Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org> --- drivers/clk/st/cl

[PATCH v4 3/4] PCI: st: Provide support for the sti PCIe controller

sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 583

[PATCH v4 4/4] MAINTAINERS: Add pci-st.c to ARCH/STI architecture

This patch adds the pci-st.c pci driver found on STMicroelectronics SoC's into the STI arch section of the maintainers file. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8133cef

Re: [PATCH v8 3/6] PCI: designware: Add ARM64 support

Hi Zhou, You can add my Tested-by: Gabriel Fernandez gabriel.fernan...@st.com I tested your patchset with a STMicroelectronics PCIe controller. This controller is based on designware PCIe driver and works on ARM32. Please find my patchset here: http://www.spinics.net/lists/kernel/msg2064266

[PATCH v4 2/4] PCI: st: Add Device Tree bindings for sti pcie

sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- Documentation/devicetree/bindings/pci/st-pcie.txt | 53 +++ 1 file changed, 53 insertions(+) create

[PATCH v4 1/4] ARM: STi: Kconfig update for PCIe support

Update Kconfig: - MIGHT_HAVE_PCI - PCI_DOMAINS Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com --- arch/arm/mach-sti/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 125865d..5f99e93 100644 ---

[PATCH v4 0/4] PCI: st: provide support for dw pcie

a STMicroelectronics PCIe controller. It's based on designware PCIe driver. Gabriel Fernandez (4): ARM: STi: Kconfig update for PCIe support PCI: st: Add Device Tree bindings for sti pcie PCI: st: Provide support for the sti PCIe controller MAINTAINERS: Add pci-st.c to ARCH/STI architecture

[PATCH v2] ARM: DT: STi: STiH418: Fix mmc0 clock configuration

This patch configure correctly the MMC-0 clock for STiH418 platform. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org Acked-by: Maxime Coquelin maxime.coque...@st.com --- arch/arm/boot/dts/stih418.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts

[PATCH v2 3/4] drivers: clk: st: Correct the pll-type for A9 for stih418

Add support for new PLL-type for stih418 A9-PLL. Currently the 407_A9_PLL type being used, it is corrected with this patch 4600c28 PLL allows to reach higher frequencies so its programming algorithm is extended. Signed-off-by: Pankaj Dev pankaj@st.com Signed-off-by: Gabriel Fernandez

[PATCH v2 2/4] drivers: clk: st: PLL rate change implementation for DVFS

Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by: Pankaj Dev pankaj@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan

[PATCH v2 4/4] ARM: STi: DT: Add support for stih418 A9 pll

Add support for new PLL-type for stih418 A9-PLL. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi

[PATCH v2 1/4] drivers: clk: st: Support for enable/disable in Clockgen PLLs

The patch adds support for enable/disable of the Clockgen PLLs. clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs. Signed-off-by: Pankaj Dev pankaj@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clkgen-pll.c | 92

[PATCH v2 0/4] ST PLL improvement

Changes in v2: - Add const for st_pll4600c28_418_a9 structure - Use readl_relaxed_poll_timeout macro instead Jiffies - Add patch to enable stih418 A9 pll via DT. This patchset is based on '[PATCH 0/2] ST PLL fixes for 4.3' Gabriel Fernandez (4): drivers: clk: st: Support for enable/disable

[PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

Use a generic name for this kind of PLL Correction in dts files are already done here: commit 5eb26c605909 (ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x) Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clkgen-fsyn.c | 8 drivers

[PATCH 1/2] dt-bindings: Fix tipo in st,clkgen-pll documentation

replace sst,plls-c32-cx_x by st,plls-c32-cx_x Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/st/st

[PATCH 0/2] ST PLL fixes for 4.3

Should be apply with commit 5eb26c605909 (ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x) to avoid broken compatibility. Gabriel Fernandez (2): dt-bindings: Fix tipo in st,clkgen-pll documentation drivers: clk: st: Rename st_pll3200c32_407_c0_x

Re: [PATCH v3 0/5] PCI: st: provide support for dw pcie

] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05) if you want ? Best Regards Gabriel. On 14 August 2015 at 16:53, Bjorn Helgaas bhelg...@google.com wrote: On Fri, Apr 10, 2015 at 11:12:43AM +0200, Gabriel FERNANDEZ wrote: Changes in v3: - Remove power management functions

[PATCH 0/3] ST PLL improvement

This patchset adds: * Enable/Disable support for Clockgen PLLs. * A new a9 pll for stih418 platform. * PLL rate change implementation for DVFS Gabriel Fernandez (3): drivers: clk: st: Support for enable/disable in Clockgen PLLs drivers: clk: st: PLL rate change implementation for DVFS

[PATCH 3/3] drivers: clk: st: Correct the pll-type for A9 for stih418

Add support for new PLL-type for stih418 A9-PLL. Currently the 407_A9_PLL type being used, it is corrected with this patch 4600c28 PLL allows to reach higher frequencies so its programming algorithm is extended. Signed-off-by: Pankaj Dev pankaj@st.com Signed-off-by: Gabriel Fernandez

[PATCH 2/3] drivers: clk: st: PLL rate change implementation for DVFS

Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by: Pankaj Dev pankaj@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan

[PATCH 1/3] drivers: clk: st: Support for enable/disable in Clockgen PLLs

The patch adds support for enable/disable of the Clockgen PLLs clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs + __enable Signed-off-by: Pankaj Dev pankaj@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clkgen-pll.c | 93

[PATCH v2 1/9] drivers: clk: st: Incorrect register offset used for lock_status

Incorrect register offset used for sthi407 clockgenC Signed-off-by: Pankaj Dev pankaj@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clkgen-fsyn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/st/clkgen-fsyn.c b

Re: [PATCH 8/9] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

. On 2 July 2015 at 18:59, Stephen Boyd sb...@codeaurora.org wrote: On 06/23, Gabriel Fernandez wrote: Use a generic name for this kind of PLL Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org Is this just a cleanup/nicety? I could take this patch but patch 9 needs to go through

Re: [PATCH 1/9] drivers: clk: st: Incorrect clocks status

Hi Stephen, Can you drop also this patch because it's concerns an old platform and there no values to make more changes. BR Gabriel. On 25 June 2015 at 10:41, Gabriel Fernandez gabriel.fernan...@linaro.org wrote: Hi Stephen, Thanks for reviewing On 24 June 2015 at 22:02, Stephen Boyd sb

Re: [PATCH 1/9] drivers: clk: st: Incorrect clocks status

Hi Stephen, Thanks for reviewing On 24 June 2015 at 22:02, Stephen Boyd sb...@codeaurora.org wrote: On 06/23/2015 07:09 AM, Gabriel Fernandez wrote: In the clk_summary output, the h/w status of DivMux is incorrect (Parent and Enable status), since the clk_mux_ops.get_parent() returns

[PATCH 8/9] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

Use a generic name for this kind of PLL Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clkgen-fsyn.c | 8 drivers/clk/st/clkgen-pll.c | 12 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/st/clkgen-fsyn.c b

[PATCH 7/9] drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks

This patch fixes the mux bit-setting for ClockgenA9. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clkgen-mux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c index 3919a67..ecb492e

[PATCH 4/9] drivers: clk: st: Fix FSYN channel values

This patch fixes the value for disabling the FSYN channel clock. The 'is_enabled' returned value is also fixed. Signed-off-by: Pankaj Dev pankaj@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clkgen-fsyn.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH 5/9] drivers: clk: st: Fix flexgen lock init

[c0632984] (start_kernel+0x20c/0x2e8) [c0632984] (start_kernel+0x20c/0x2e8) from [40008074] (0x40008074) Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clk-flexgen.c | 2 ++ 1 file changed, 2 insertions(+) diff

[PATCH 1/9] drivers: clk: st: Incorrect clocks status

In the clk_summary output, the h/w status of DivMux is incorrect (Parent and Enable status), since the clk_mux_ops.get_parent() returns -ERRCODE when clock is OFF. Signed-off-by: Pankaj Dev pankaj@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clkgen

[PATCH 0/9] clk: ST clock fixes

This first patch-set contains various clock fixes for ST SoC. Gabriel Fernandez (7): drivers: clk: st: Incorrect clocks status drivers: clk: st: Incorrect register offset used for lock_status drivers: clk: st: Remove unused code drivers: clk: st: Fix FSYN channel values drivers: clk: st

[PATCH 3/9] drivers: clk: st: Remove unused code

Remove this duplicated code due to a bad copy / paste. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/clk/st/clkgen-fsyn.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c index e6d7073..e7e6782 100644

[PATCH 9/9] ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

Use a generic name for this kind of PLL Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++-- arch/arm/boot/dts/stih407-clock.dtsi | 4 ++-- arch/arm/boot/dts/stih410-clock.dtsi

Re: [PATCH v3 3/5] PCI: st: Provide support for the sti PCIe controller

Hi Thanks for reviewing. On 11 April 2015 at 16:55, Arnd Bergmann a...@arndb.de wrote: On Saturday 11 April 2015 12:17:57 Paul Bolle wrote: Something I didn't spot in my first look at this patch. On Fri, 2015-04-10 at 11:12 +0200, Gabriel FERNANDEZ wrote: --- a/drivers/pci/host/Kconfig

Re: [STLinux Kernel] [PATCH 0/4] clk: Provide support for always-on clocks

Hi Peter, Lee, With these series as they are, we need 'clk_ignore_unused' on sthi407-b2120.dts and stih418-b2199.dts. We have to modificate stih407-clock.dtsi and stih418-clock.dtsi in same way. BR Gabriel On 2 April 2015 at 10:12, Peter Griffin peter.grif...@linaro.org wrote: Hi Lee, On

Re: [PATCH v2 3/5] PCI: st: Provide support for the sti PCIe controller

Hi Bjorn, pci-st.c driver could be modular with modification of pcie-designware core driver. But as Fabrice said it should be another patchset. What do you prefer ? drop all the module related macros as mentioned by Paul ? or keep macros like other vendors do ? Thanks Gabriel On 18 March

Re: [PATCH v2 3/5] PCI: st: Provide support for the sti PCIe controller

Hi Kishon, I tested with my internal 3.10 ST Kernel but not on the 4.0. I think i'll implement it when i'm able to test it fully. Thanks On 17 March 2015 at 11:35, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, On Monday 16 March 2015 07:50 PM, Gabriel FERNANDEZ wrote: sti pcie is built

Re: [PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie

Hi Liviu, You're right, i removed configuration space from the ranges. Thanks for reviewing. Gabriel On 17 March 2015 at 12:42, Liviu Dudau liviu.du...@arm.com wrote: Hi Gabriel, On Mon, Mar 16, 2015 at 02:20:32PM +, Gabriel FERNANDEZ wrote: sti pcie is built around a Synopsis

Re: [PATCH v2 3/5] PCI: st: Provide support for the sti PCIe controller

Thanks Paul for reviewing. I'll check to be modular. BR Gabriel On 16 March 2015 at 16:11, Paul Bolle pebo...@tiscali.nl wrote: On Mon, 2015-03-16 at 15:20 +0100, Gabriel FERNANDEZ wrote: --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig +config PCI_ST + bool ST PCIe

Re: [PATCH v2 4/5] PCI: designware: Add disable IO support

Hi Arnd, Ok i will try the same way that pci-versatile.c Thanks. Gabriel On 16 March 2015 at 21:00, Arnd Bergmann a...@arndb.de wrote: On Monday 16 March 2015 13:00:51 Kumar Gala wrote: On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ gabriel.fernan...@st.com wrote: ST sti SoCs PCIe IPs

Re: [PATCH v2 4/5] PCI: designware: Add disable IO support

Hi Srinivas, Yes, you are right. Nevertheless i'll try the Kumar and Arnd 's request to not use DT to do that. BR Gabriel On 16 March 2015 at 18:53, Srinivas Kandagatla srinivas.kandaga...@linaro.org wrote: On 16/03/15 14:20, Gabriel FERNANDEZ wrote: - bus-range: PCI bus numbers

[PATCH v2 5/5] MAINTAINERS: Add pci-st.c to ARCH/STI architecture

This patch adds the pci-st.c pci driver found on STMicroelectronics SoC's into the STI arch section of the maintainers file. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index a0dadde

[PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie

sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- Documentation/devicetree/bindings/pci/st-pcie.txt | 54 +++ 1 file changed, 54 insertions(+) create

[PATCH v2 3/5] PCI: st: Provide support for the sti PCIe controller

sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 617

[PATCH v2 1/5] ARM: STi: Kconfig update for PCIe support

Update Kconfig: - MIGHT_HAVE_PCI - PCI_DOMAINS Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com --- arch/arm/mach-sti/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 3b1ac46..7f9b432 100644 ---

[PATCH v2 0/5] PCI: st: provide support for dw pcie

the st_pcie_abort_handler() function because abort handling is masked during boot. This patch-set introduces a STMicroelectronics PCIe controller. It's based on designware PCIe driver. Gabriel Fernandez (5): ARM: STi: Kconfig update for PCIe support PCI: st: Add Device Tree bindings for sti

[PATCH v2 4/5] PCI: designware: Add disable IO support

fabrice.gasn...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- .../devicetree/bindings/pci/designware-pcie.txt| 2 ++ drivers/pci/host/pcie-designware.c | 24 -- drivers/pci/host/pcie-designware.h | 1 + 3 files changed

Re: [PATCH 5/5] PCI: st: disable IO support

Hi, Yes, we don't really care about this corner case. Thanks for your reviewing. BR Gabriel On 17 December 2014 at 15:01, One Thousand Gnomes gno...@lxorguk.ukuu.org.uk wrote: On Wed, 17 Dec 2014 11:34:46 +0100 Gabriel FERNANDEZ gabriel.fernan...@st.com wrote: sti SoCs PCIe IPs are built

Re: [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller

On 19 January 2015 at 14:49, Arnd Bergmann a...@arndb.de wrote: On Monday 19 January 2015 13:37:33 Gabriel Fernandez wrote: On 17 December 2014 at 23:14, Arnd Bergmann a...@arndb.de wrote: On Wednesday 17 December 2014 11:34:44 Gabriel FERNANDEZ wrote: +/* + * On ARM platforms, we

Re: [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller

Hi Bjorn Helgaas, On 12 January 2015 at 19:43, Bjorn Helgaas bhelg...@google.com wrote: On Wed, Dec 17, 2014 at 11:34:44AM +0100, Gabriel FERNANDEZ wrote: sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel

Re: [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller

Hi Jingoo, Thanks for reviewing On 18 December 2014 at 07:03, Jingoo Han jg1@samsung.com wrote: On Wednesday, December 17, 2014 7:35 PM, Gabriel FERNANDEZ wrote: sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off

Re: [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller

Hi Arnd, On 17 December 2014 at 23:14, Arnd Bergmann a...@arndb.de wrote: On Wednesday 17 December 2014 11:34:44 Gabriel FERNANDEZ wrote: sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel Fernandez

Re: [PATCH 4/5] PCI: designware: Add setup bus-related to pcie_host_ops

Hi Arnd, Jingoo, On 18 December 2014 at 05:58, Jingoo Han jg1@samsung.com wrote: On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote: On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote: ST sti SoCs PCIe IPs are built around DesignWare IP Core. But in these SoCs PCIe

Re: [PATCH 2/5] PCI: st: Add Device Tree bindings for sti pcie

Hi Arnd, Thanks for reviewing On 17 December 2014 at 23:01, Arnd Bergmann a...@arndb.de wrote: On Wednesday 17 December 2014 11:34:43 Gabriel FERNANDEZ wrote: sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel

[PATCH 2/2] ARM: DT: STiH410: Add DRM dt nodes

This patch adds the DRM/KMS dt nodes. Signed-off-by: Benjamin Gaignard benjamin.gaign...@linaro.org Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- arch/arm/boot/dts/stih410.dtsi | 138 + 1 file changed, 138 insertions(+) diff --git

[PATCH 1/2] ARM: DT: STiH407: Add DRM dt nodes

This patch adds the DRM/KMS dt nodes. This node can't be in stih407-family.dtsi file because in the future we will integrate a new stih418-b2199 board. It's a stih407 family board with different drm/kms dt nodes. That is why i created the stih407.dtsi file. Signed-off-by: Gabriel Fernandez

[PATCH 0/2] Enable DRM/KMS support for STiH407 and STiH410 boards

This patch-set Enable DRM/KMS support for STiH407-b2120 and STiH410-b2120 boards. This patch-set replace the previous one (PATCH 0/2] Enable DRM/KMS support for STiH407 Family boards) Gabriel Fernandez (2): ARM: DT: STiH407: Add DRM dt nodes ARM: DT: STiH410: Add DRM dt nodes arch/arm

[PATCH 1/3] phy: miphy28lp: Pass sysconfig register offsets via syscfg dt property.

aligns us to how other platforms such as keystone and bcm7445 pass there syscon offsets via DT. I have updated the miphy28lp phy driver same way as Peter's implementation. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- .../devicetree/bindings/phy/phy-miphy28lp.txt | 43

[PATCH 0/2] Enable DRM/KMS support for STiH407 Family boards

This patch-set Enable DRM/KMS support for STiH407 Family boards. Gabriel Fernandez (2): ARM: DT: STiH407: Add DRM dt nodes ARM: DT: STiH407: Specify default clocks for HDMI devices arch/arm/boot/dts/stih407-family.dtsi | 139 ++ arch/arm/boot/dts/stihxxx

[PATCH 2/2] ARM: DT: STiH407: Specify default clocks for HDMI devices

Specify default clocks for HDMI devices to ensure a maximum of compatible frequencies. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- arch/arm/boot/dts/stih407-family.dtsi | 35 +++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot

[PATCH 1/2] ARM: DT: STiH407: Add DRM dt nodes

This patch adds the DRM/KMS dt notes. Signed-off-by: Benjamin Gaignard benjamin.gaign...@linaro.org Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- arch/arm/boot/dts/stih407-family.dtsi | 104 ++ arch/arm/boot/dts/stihxxx-b2120.dtsi | 2 +- 2

[PATCH 4/5] PCI: designware: Add setup bus-related to pcie_host_ops

ST sti SoCs PCIe IPs are built around DesignWare IP Core. But in these SoCs PCIe IP doesn't support IO. To support this, add setup_bus() to pcie_host_ops. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/pci/host

[PATCH 0/5] PCI: st: provide support for dw pcie

This patch-set introduces a STMicroelectronics PCIe controler. It's based on designware PCIe driver. Gabriel Fernandez (5): ARM: STi: Kconfig update for PCIe support PCI: st: Add Device Tree bindings for sti pcie PCI: st: Provide support for the sti PCIe controller PCI: designware: Add

[PATCH 5/5] PCI: st: disable IO support

sti SoCs PCIe IPs are built around DesignWare IP Core. But in these SoCs, PCIe IP doesn't support IO. By default, when no IO space is provided, a default one is assigned. Add an empty IO resource to the bus, and disable IO by default. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com ---

[PATCH 3/5] PCI: st: Provide support for the sti PCIe controller

sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-st.c | 713

[PATCH 1/5] ARM: STi: Kconfig update for PCIe support

Update Kconfig: - MIGHT_HAVE_PCI - PCI_DOMAINS Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com --- arch/arm/mach-sti/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 8825bc9..d1e563c 100644 ---

[PATCH 2/5] PCI: st: Add Device Tree bindings for sti pcie

sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- Documentation/devicetree/bindings/pci/st-pcie.txt | 53 +++ 1 file changed, 53 insertions(+) create

Re: [PATCH v4 2/8] phy: miphy28lp: Add PHY header file for DT x Driver defines

Hi Kishon, Sure, I'll update my patch set and sent to you soon as possible. Best Regards Gabriel On 4 November 2014 10:25, Kishon Vijay Abraham I kis...@ti.com wrote: Hi Gabriel, On Wednesday 22 October 2014 12:44 PM, Gabriel FERNANDEZ wrote: This provides the shared header file which

[PATCH v5 0/8] phy: miphy28lp: Introduce support for MiPHY28lp

of this series is to add the support of MiPHY28lp Generic PHY. I tried to be as close as possible to the MiPHY365x Lee Jones proposal. Best Regards Gabriel. Gabriel Fernandez (8): phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp phy: miphy28lp: Add PHY header file for DT x Driver

[PATCH v5 2/8] phy: miphy28lp: Add PHY header file for DT x Driver defines

This provides the shared header file which will be reference from both PHY driver and its associated Device Tree node(s). Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- include/dt-bindings/phy/phy.h | 18 ++ 1 file changed, 18 insertions(+) create mode 100644

[PATCH v5 6/8] phy: miphy28lp: Add SSC support for PCIE

clock. Signed-off-by: Harsh Gupta harsh.gu...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/phy/phy-miphy28lp.c | 44 1 file changed, 44 insertions(+) diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy

[PATCH v5 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp

The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue alexandre.tor...@st.com Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- .../devicetree/bindings/phy/phy

[PATCH v5 5/8] phy: miphy28lp: Add SSC support for SATA

This patch to tune on/off the ssc on miphy sata setup. User can now enable ssc via dt blob, it is useful to reduce effects of EMI. Signed-off-by: Giuseppe Condorelli giuseppe.condore...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- .../devicetree/bindings/phy/phy

[PATCH v5 3/8] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY

The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue alexandre.tor...@st.com Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/phy/Kconfig

[PATCH v5 7/8] phy: miphy28lp: Tune tx impedance across Soc cuts

This patch to compensate tx impedance (Sata, PCIe) depending on Soc cuts the kernel is built for. Signed-off-by: Giuseppe Condorelli giuseppe.condore...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- Documentation/devicetree/bindings/phy/phy-miphy28lp.txt | 1

[PATCH v5 4/8] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp

The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or USB3 devices. The two first ports can be use for either; both SATA, both PCIe or one of each in any configuration. The Third port is only for USB3. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- arch/arm/boot

[PATCH v5 8/8] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe USB3) PHY

Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index f1dc7fc..d5c2ff1 100644 --- a/arch/arm/configs

[PATCH v4 0/8] phy: miphy28lp: Introduce support for MiPHY28lp

tried to be as close as possible to the MiPHY365x Lee Jones proposal. Best Regards Gabriel. Gabriel Fernandez (8): phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp phy: miphy28lp: Add PHY header file for DT x Driver defines phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY

[PATCH v4 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp

The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue alexandre.tor...@st.com Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- .../devicetree/bindings/phy/phy

[PATCH v4 6/8] phy: miphy28lp: Add SSC support for PCIE

clock. Signed-off-by: Harsh Gupta harsh.gu...@st.com Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- drivers/phy/phy-miphy28lp.c | 44 1 file changed, 44 insertions(+) diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy

[PATCH v4 4/8] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp

The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or USB3 devices. The two first ports can be use for either; both SATA, both PCIe or one of each in any configuration. The Third port is only for USB3. Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- arch/arm/boot

[PATCH v4 8/8] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe USB3) PHY

Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 491b7d5..b86dc6d 100644 --- a/arch/arm/configs

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