On 12/01/2015 05:24 PM, Kapil Hali wrote:
> From: Jon Mason <jonma...@broadcom.com>
>
> Add SMP support for Broadcom's 4708 SoCs.
>
> Signed-off-by: Jon Mason <jonma...@broadcom.com>
> Acked-by: Hauke Mehrtens <ha...@hauke-m.de>
> Tested-by: Hauke M
On 11/20/2015 05:52 AM, Martin Schiller wrote:
> This patch introduces new dedicated "lantiq,pinctrl-" devicetree
> bindings, where is one of "ase", "danube", "xrx100", "xrx200" or
> "xrx300" and marks the "lantiq,pinctrl-xway" and "lantiq,pinctrl-xr9"
> bindings as
> DEPRECATED.
Thanks for
+++--
> 1 file changed, 71 insertions(+), 21 deletions(-)
>
Acked-by: Hauke Mehrtens <ha...@hauke-m.de>
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On 11/07/2015 12:27 AM, Hauke Mehrtens wrote:
> On 11/06/2015 11:54 PM, Jon Mason wrote:
>> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
>>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>>>> From: Jon Mason <jonma...@broadcom.com>
>>>&g
On 11/06/2015 11:54 PM, Jon Mason wrote:
> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>>> From: Jon Mason <jonma...@broadcom.com>
>>>
>>> Add SMP support for Broadcom's 4708 SoC
On 11/06/2015 10:11 PM, Kapil Hali wrote:
> From: Jon Mason <jonma...@broadcom.com>
>
> Add SMP support for Broadcom's 4708 SoCs.
>
> Signed-off-by: Jon Mason <jonma...@broadcom.com>
> Acked-by: Hauke Mehrtens <ha...@hauke-m.de>
> Tested-by: Hauke M
On 11/05/2015 10:34 AM, Russell King - ARM Linux wrote:
> On Thu, Nov 05, 2015 at 12:51:17AM -0500, Kapil Hali wrote:
>> Hi,
>>
>> This series adds SMP support for Broadcom's Northstar Plus SoC.
>>
>> There are similar SMP enablement methods for many ARMv7 bsed SoCs.
>> BCM NSP SoC, has a typical
On 10/28/2015 03:24 PM, Kapil Hali wrote:
>
>
> On 10/16/2015 2:47 AM, Jon Mason wrote:
>> On Thu, Oct 15, 2015 at 11:12:09PM +0200, Hauke Mehrtens wrote:
>>> On 10/15/2015 06:10 PM, Kapil Hali wrote:
>>>>
>>>>
>>>> On 10/15/2015 3:56 A
On 10/15/2015 08:14 PM, Jon Mason wrote:
> ARM: BCM: Add SMP support for Broadcom 4708
>
> Add SMP support for Broadcom's 4708 SoCs.
I tested this and it works on my device, it is also in OpenWrt now:
On 10/13/2015 11:22 PM, Jon Mason wrote:
> Replace current device tree dummy clocks with real clock support for
> Broadcom Northstar SoCs.
>
> Signed-off-by: Jon Mason
The clock-frequency of the uarts should also be replaced with the
correct clock from the clock driver.
on Mason <jonma...@broadcom.com>
Acked-by: Hauke Mehrtens <ha...@hauke-m.de>
> ---
> arch/arm/boot/dts/Makefile | 5 +++-
> arch/arm/boot/dts/bcm94708.dts | 56 +++
> arch/arm/boot/dts/bcm94709.dts | 56 +
On 10/16/2015 12:24 AM, Jon Mason wrote:
> Add the 4708, 4709, and 53012 SoCs to the the documentation for the
> Broadcom Northstar device tree bindings.
>
> Signed-off-by: Jon Mason <jonma...@broadcom.com>
Acked-by: Hauke Mehrtens <ha...@hauke-m.de>
> ---
> Doc
e first string in the list specifies the exact device that the node
represents"
http://devicetree.org/Device_Tree_Usage#Understanding_the_compatible_Property
The exact device here is the board not the SoC.
Hauke
>
> On 15-10-16 02:41 PM, Hauke Mehrtens wrote:
>> On 10/16/2015 12:
On 10/15/2015 06:10 PM, Kapil Hali wrote:
>
>
> On 10/15/2015 3:56 AM, Hauke Mehrtens wrote:
>> On 10/14/2015 07:47 PM, Kapil Hali wrote:
>>> Add SMP support for Broadcom's Northstar Plus SoC,
>>> cpu enable method and pen_release procedures. This
>>>
On 10/15/2015 12:14 AM, Jon Mason wrote:
> Add the 4708, 4709, and 953012k SVKs to the the documentation for the
> Broadcom Northstar device tree bindings.
>
> Signed-off-by: Jon Mason
> ---
> Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++
> 1
On 10/15/2015 11:25 PM, Jon Mason wrote:
> On Thu, Oct 15, 2015 at 10:55:16PM +0200, Hauke Mehrtens wrote:
>> On 10/15/2015 10:40 PM, Hauke Mehrtens wrote:
>>> On 10/15/2015 12:14 AM, Jon Mason wrote:
>>>> Add device tree files for Broadcom Northstar based SVKs.
On 10/15/2015 10:40 PM, Hauke Mehrtens wrote:
> On 10/15/2015 12:14 AM, Jon Mason wrote:
>> Add device tree files for Broadcom Northstar based SVKs. Since the
>> bcm5301x.dtsi already exists, all that is necessary is the dts files to
>> enable the UARTs (and specify the RA
On 10/15/2015 09:48 PM, Jon Mason wrote:
> From: Arnd Bergmann
>
> When CONFIG_CYGNUS is set but CONFIG_COMMON_CLK_IPROC is disabled, the
> following link failures are caused:
>
> drivers/built-in.o: In function `cygnus_armpll_init':
> :(.init.text+0x1d290): undefined reference
On 10/15/2015 12:14 AM, Jon Mason wrote:
> Add device tree files for Broadcom Northstar based SVKs. Since the
> bcm5301x.dtsi already exists, all that is necessary is the dts files to
> enable the UARTs (and specify the RAM size for the 4708/9). With these
> files, the SVKs are able to boot to
On 10/14/2015 07:46 PM, Kapil Hali wrote:
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU pen-release mechanism.
>
> Signed-off-by: Kapil
On 10/14/2015 07:47 PM, Kapil Hali wrote:
> Add SMP support for Broadcom's Northstar Plus SoC,
> cpu enable method and pen_release procedures. This
> changes also consolidates iProc family's - BCM NSP
> and BCM Kona, SMP handling in a common file.
This will probably also work on normal Northstar
On 10/03/2015 12:22 AM, Jon Mason wrote:
> Add device tree files for Broadcom Northstar based SVKs. Since the
> bcm5301x.dtsi already exists, all that is necessary is the dts files to
> enable the UARTs (and specify the RAM size for the 4708/9). With these
> files, the SVKs are able to boot to
On 10/03/2015 12:22 AM, Jon Mason wrote:
> Add the 4708, 4709, and 953012k SVKs to the the documentation for the
> Broadcom Northstar device tree bindings.
>
> Signed-off-by: Jon Mason
> ---
> Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++
> 1
On 05/24/2015 08:38 PM, Hauke Mehrtens wrote:
This moves the linux,part-probe device tree parsing code from
physmap_of.c to mtdpart.c. Now all drivers can use this feature by just
providing a reference to their device tree node in struct
mtd_part_parser_data.
Signed-off-by: Hauke Mehrtens
uses this default match table and populates the bus.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
drivers/of/platform.c | 9 +
include/linux/of_platform.h | 9 +
2 files changed, 18 insertions(+)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index ddf8e42
On 06/28/2015 03:38 AM, Florian Fainelli wrote:
Le 06/27/15 15:08, Rafał Miłecki a écrit :
On 24 June 2015 at 01:51, Florian Fainelli f.faine...@gmail.com wrote:
Enable the use of UART0 by overriding its default status property.
Signed-off-by: Florian Fainelli f.faine...@gmail.com
---
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/02/2015 09:20 AM, Michal Simek wrote:
On 05/15/2015 03:55 PM, Catalin Marinas wrote:
On Fri, May 15, 2015 at 11:10:28AM +0100, Russell King - ARM
Linux wrote:
On Thu, May 07, 2015 at 05:02:57PM +0100, Catalin Marinas
wrote:
On Thu, May 07,
-by: Hauke Mehrtens ha...@hauke-m.de
---
changes since v1:
* remove the arm prefix in prefetch-data and prefetch-instr.
arch/arm/boot/dts/bcm5301x.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 78aec62..589b285 100644
On 05/28/2015 10:21 AM, Arnd Bergmann wrote:
On Wednesday 27 May 2015 23:46:48 Hauke Mehrtens wrote:
On 05/27/2015 09:37 AM, Arnd Bergmann wrote:
On Sunday 24 May 2015 20:32:29 Hauke Mehrtens wrote:
@@ -124,17 +124,7 @@
0x00026000 0 gic GIC_SPI 149
On 05/29/2015 07:52 PM, Florian Fainelli wrote:
On 15/05/15 14:52, Hauke Mehrtens wrote:
These options make it possible to overwrites the data and instruction
prefetching behavior of the arm pl310 cache controller.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
v2: only set prefetch
Will this make it into kernel 4.2 or do I have to do something so that
this will make it into 4.2?
Hauke
On 05/15/2015 11:52 PM, Hauke Mehrtens wrote:
These options make it possible to overwrites the data and instruction
prefetching behavior of the arm pl310 cache controller.
Signed-off
On 05/29/2015 08:35 PM, Florian Fainelli wrote:
On 29/05/15 11:30, Florian Fainelli wrote:
On 29/05/15 11:11, Hauke Mehrtens wrote:
On 05/29/2015 07:52 PM, Florian Fainelli wrote:
On 15/05/15 14:52, Hauke Mehrtens wrote:
These options make it possible to overwrites the data
This adds the NAND flash chip description for a standard chip found
connected to this SoC. This makes use of generic Broadcom NAND driver
with the iProc interface.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
changes since RFC:
* remove linux,part-probe, there are still discussion about
On 05/27/2015 09:37 AM, Arnd Bergmann wrote:
On Sunday 24 May 2015 20:32:29 Hauke Mehrtens wrote:
@@ -124,17 +124,7 @@
0x00026000 0 gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH,
/* Ethernet Controller 3 */
- 0x00027000 0 gic
computersforpe...@gmail.com wrote:
On Sun, May 17, 2015 at 05:41:04PM +0200, Hauke Mehrtens wrote:
This driver registers at the bcma bus and drives the NAND core if it
was found on this bus. The bcma bus with this NAND core is used on the
bcm53xx and bcm47xx Northstar SoC with ARM CPU cores. The memory
On 05/27/2015 02:41 AM, Brian Norris wrote:
On Sun, May 24, 2015 at 08:32:29PM +0200, Hauke Mehrtens wrote:
This adds the NAND flash chip description for a standard chip found
connected to this SoC. This makes use of generic Broadcom NAND driver
with the iProc interface.
Signed-off-by: Hauke
On 05/24/2015 05:11 PM, Paul Burton wrote:
Support the Ingenic JZ4780 SoC using the existing code under
arch/mips/jz4740 now that it has been generalised sufficiently.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala
-by: Hauke Mehrtens ha...@hauke-m.de
---
arch/arm/boot/dts/bcm5301x.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 78aec62..7d1578a 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
On 05/24/2015 08:54 PM, Rafał Miłecki wrote:
On 24 May 2015 at 20:50, Hauke Mehrtens ha...@hauke-m.de wrote:
In the default Broadcom SDK the shared override is activated for this
cache controller, do the same in the upstream code. Data and
instruction prefetching is not activated by default
This moves the linux,part-probe device tree parsing code from
physmap_of.c to mtdpart.c. Now all drivers can use this feature by just
providing a reference to their device tree node in struct
mtd_part_parser_data.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
changes since
v1:
* add
This adds the NAND flash chip description for a standard chip found
connected to this SoC. This makes use of generic Broadcom NAND driver
with the iProc interface.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
This would be the patch when we completely change to device tree only
The driver for the PCIe controller was just added, this adds the
missing definition of the IRQ numbers to device tree. The driver itself
will be automatically detected by bcma.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
arch/arm/boot/dts/bcm5301x.dtsi | 24
1
On 05/20/2015 08:40 PM, Brian Norris wrote:
On Wed, May 20, 2015 at 08:39:06AM +0200, Rafał Miłecki wrote:
On 20 May 2015 at 02:34, Brian Norris computersforpe...@gmail.com wrote:
On Sun, May 17, 2015 at 05:41:04PM +0200, Hauke Mehrtens wrote:
This driver registers at the bcma bus and drives
This adds the NAND flash chip description for a standard chip found
connected to this SoC. The IRQ is fetched from the device tree
definition of the axi bus for this core and the memory ranges are
automatically probed.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
arch/arm/boot/dts/bcm4708
The caller already adds a new line and in the other cases there is no
new line added.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
drivers/mtd/nand/brcmnand/brcmnand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c
b/drivers/mtd
On 12/10/2014 07:46 PM, Florian Fainelli wrote:
2014-12-10 8:46 GMT-08:00 Scott Branden sbran...@broadcom.com:
On 14-12-10 03:31 AM, Arnd Bergmann wrote:
On Tuesday 09 December 2014 16:04:29 Ray Jui wrote:
Add initial version of the Broadcom iProc PCIe driver. This driver
has been tested on
IRQ support for Broadcom's bus-axi driver bcma was merged into John
Linville's wireless tree and will show up in 3.19. This patch makes use
of this feature in the DTS file for the the BCM5301X SoCs. I left the
PCIe controller out, because this still needs some discussion.
Signed-off-by: Hauke
On 09/27/2014 10:05 AM, Rafał Miłecki wrote:
On 27 September 2014 00:03, Arnd Bergmann a...@arndb.de wrote:
On Friday 26 September 2014 16:28:53 Rafał Miłecki wrote:
+The top-level axi bus may contain following children:
+
+- gpio: GPIO chip on the SoC
+
+ Required properties:
+ -
On 09/27/2014 12:37 PM, Rafał Miłecki wrote:
On 27 September 2014 10:33, Hauke Mehrtens ha...@hauke-m.de wrote:
I would make GPIO a subdevive of chipcommon. The chipcommon core has an
own IRQ which is also used for GPIO.
Which ChipCommon do yo mean?
1) chipcommonA (compatible = simple-bus
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
Documentation/devicetree/bindings/bus/bcma.txt | 20 +++
drivers/bcma
On 09/24/2014 11:48 AM, Arnd Bergmann wrote:
On Wednesday 24 September 2014 00:04:18 Hauke Mehrtens wrote:
I assume this should then look somehow like this:
axi@1800 {
compatible = brcm,bus-axi;
reg = 0x1800 0x1000;
ranges = 0x 0x1800 0x0010
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
Documentation/devicetree/bindings/bus/bcma.txt | 20 +++
drivers/bcma
It is not possible to auto detect the irq numbers used by the cores on
an arm SoC. If bcma was registered with device tree it will search for
some device tree nodes with the irq number and add it to the core
configuration.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
Documentation
On 09/22/2014 09:26 AM, Arnd Bergmann wrote:
On Monday 22 September 2014 00:38:27 Hauke Mehrtens wrote:
+
+- reg : iomem address range of chipcommon core
+
+The cores on the AXI bus are automatically detected by bcma with the
+memory ranges they are using and they get registered afterwards
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
Documentation/devicetree/bindings/bus/bcma.txt | 39
It is not possible to auto detect the irq numbers used by the cores on
an arm SoC. If bcma was registered with device tree it will search for
some device tree nodes with the irq number and add it to the core
configuration.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
drivers/bcma/main.c
It is not possible to auto detect the irq numbers used by the cores on
an arm SoC. If bcma was registered with device tree it will search for
some device tree nodes with the irq number and add it to the core
configuration.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
drivers/bcma/main.c
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
Documentation/devicetree/bindings/bus/bcma.txt | 39
drivers
On 09/20/2014 05:40 PM, Varka Bhadram wrote:
On Saturday 20 September 2014 06:32 PM, Hauke Mehrtens wrote:
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores
On 09/18/2014 11:42 AM, Arend van Spriel wrote:
On 09/17/14 17:10, Rafał Miłecki wrote:
On 16 September 2014 23:56, Hauke Mehrtensha...@hauke-m.de wrote:
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
On 09/18/2014 10:03 PM, Rafał Miłecki wrote:
On 16 September 2014 23:56, Hauke Mehrtens ha...@hauke-m.de wrote:
+The cores on the AXI bus are auto detected by bcma. bcma automatically
+detects the cores
I'm far from being an English expert, but above is kind of pleonasm to me ;)
Yes to me
On 09/16/2014 09:58 PM, Jonathan Richardson wrote:
Hi,
This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
On 09/19/2014 12:39 AM, Florian Fainelli wrote:
On 09/18/2014 03:31 PM, Hauke Mehrtens wrote:
On 09/16/2014 09:58 PM, Jonathan Richardson wrote:
Hi,
This patchset contains initial support for Broadcom's Cygnus SoC based on
our
iProc architecture. Initial support is minimal and includes
It is not possible to auto detect the irq numbers used by the cores on
an arm SoC. If bcma was registered with device tree it will search for
some device tree nodes with the irq number and add it to the core
configuration.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
drivers/bcma/main.c
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
Documentation/devicetree/bindings/bus/bcma.txt | 40
On 09/13/2014 06:40 PM, Arend van Spriel wrote:
On 09/13/14 18:02, Hauke Mehrtens wrote:
On 09/13/2014 05:13 PM, Arend van Spriel wrote:
On 09/13/14 15:37, Hauke Mehrtens wrote:
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core
It is not possible to auto detect the irq numbers used by the cores on
an arm SoC. If bcma was registered with device tree it will search for
some device tree nodes with the irq number and add it to the core
configuration.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
drivers/bcma/main.c
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
Documentation/devicetree/bindings/bus/bcma.txt | 41
On 09/13/2014 05:13 PM, Arend van Spriel wrote:
On 09/13/14 15:37, Hauke Mehrtens wrote:
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtensha
On 08/25/2014 09:57 AM, Arnd Bergmann wrote:
On Sunday 24 August 2014 23:24:42 Hauke Mehrtens wrote:
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
Documentation/devicetree/bindings/bus/bcma.txt | 46
is to
make the bcm47xx MIPS SoCs also use this driver some time later.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
.../devicetree/bindings/misc/bcm47xx-sprom.txt | 16 +
drivers/misc/Kconfig | 14 +
drivers/misc/Makefile | 1
not implemented
libphy: bgmac mii bus: probed
b53_common: found switch: BCM53011, rev 2
bgmac bcma0:2: Found PHY addr: 0
bgmac bcma0:2: Support for Roboswitch not implemented
libphy: bgmac mii bus: probed
Hauke Mehrtens (7):
MIPS: BCM47XX: move the nvram header file into common space
bcm47xx-nvram: add
not implemented
libphy: bgmac mii bus: probed
b53_common: found switch: BCM53011, rev 2
bgmac bcma0:2: Found PHY addr: 0
bgmac bcma0:2: Support for Roboswitch not implemented
libphy: bgmac mii bus: probed
Hauke Mehrtens (7):
MIPS: BCM47XX: move the nvram header file into common space
bcm47xx-nvram: add
.
This was copied from arch/mips/bcm47xx/nvram.c and modified to interact
with device tree. My plan is to make the MIPS bcm47xx also use this new
driver some time later.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
.../devicetree/bindings/misc/bcm47xx-nvram.txt | 19 ++
arch/mips/bcm47xx/board.c
It is not possible to auto detect the irq numbers used by the cores on
an arm SoC. If bcma was registered with device tree it will search for
some device tree nodes with the irq number and add it to the core
configuration.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
drivers/bcma/main.c
This patch make it possible to device an sprom provider in device tree
and get the sprom from this driver. Every time there is such a provider
it gets asked for a sprom.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
drivers/bcma/sprom.c | 51
---
arch/arm/boot/dts/bcm4708.dtsi | 58 ++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
index 31141e8..7c240ab 100644
--- a/arch/arm/boot/dts/bcm4708.dtsi
+++
.
This is a preparation for adding a new nvram driver, which can be used
by the ARM SoC and the MIPS SoC code. The device drivers accessing
nvram do not have to care about ARM or MIPS SoC version.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
arch/mips/bcm47xx/board.c
On 03/29/2014 01:29 PM, Alexander Shiyan wrote:
Sat, 29 Mar 2014 12:54:40 +0100 от Rafał Miłecki zaj...@gmail.com:
Hi guys,
I've noticed gpio_wdt was added to the kernel to support some devices
based on devicetree.
We used to have our own (not mainlined) gpio_wdt in OpenWrt project:
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