!(reg & val), 100, 1);
> +}
> +
> +static int mt8173_nor_set_cmd(struct mt8173_nor *mt8173_nor, int addr, int
> len,
> + int op)
> +{
> + writeb(op, mt8173_nor->base + MTK_NOR_PRGDATA5_REG);
> + /* send the address to nor flash
> + * MTK_NOR_PRGDATA5_REG is shifted first
> + * MTK_NOR_PRGDATA0_REG is shifted last
> + */
> + writeb(((addr >> 16) & 0xff), mt8173_nor->base + MTK_NOR_PRGDATA4_REG);
> + writeb(((addr >> 8) & 0xff), mt8173_nor->base + MTK_NOR_PRGDATA3_REG);
> + writeb((addr & 0xff), mt8173_nor->base + MTK_NOR_PRGDATA2_REG);
Why not use some macros to wrap the hardcode such as:
(addr >> 16) & 0xff.
thanks
Huang Shijie
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The old code uses hardcode for the memtimer's interrupt property,
this patch replaces the hardcode with the proper macros.
Signed-off-by: Huang Shijie
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/arm
(4KB)
This patch fixes the wrong memory map sizes for them.
Signed-off-by: Huang Shijie
---
There is something wrong with my email account, so try to send it out again.
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arc
(4KB)
This patch fixes the wrong memory map sizes for them.
Signed-off-by: Huang Shijie
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi
b/arch/arm64/boot/dts/arm/juno-base.dt
On Tue, Dec 02, 2014 at 08:28:10AM +0100, Stefan Roese wrote:
> On 02.12.2014 01:38, Huang Shijie wrote:
> > On Mon, Dec 01, 2014 at 10:58:17AM +0100, Stefan Roese wrote:
> >> On 30.11.2014 16:42, Huang Shijie wrote:
> >>> On Sat, Nov 29, 2014 at 10:53:26PM -0800, Bri
On Mon, Dec 01, 2014 at 10:58:17AM +0100, Stefan Roese wrote:
> On 30.11.2014 16:42, Huang Shijie wrote:
> > On Sat, Nov 29, 2014 at 10:53:26PM -0800, Brian Norris wrote:
> >> On Sat, Nov 29, 2014 at 10:40:50AM +0800, Huang Shijie wrote:
> >>> On Fri, Nov 28, 2014 at
On Sat, Nov 29, 2014 at 10:53:26PM -0800, Brian Norris wrote:
> On Sat, Nov 29, 2014 at 10:40:50AM +0800, Huang Shijie wrote:
> > On Fri, Nov 28, 2014 at 08:01:41AM +0100, Stefan Roese wrote:
> > > On 28.11.2014 02:48, Huang Shijie wrote:
> > > >On Thu, Nov 27, 20
On Fri, Nov 28, 2014 at 08:01:41AM +0100, Stefan Roese wrote:
> On 28.11.2014 02:48, Huang Shijie wrote:
> >On Thu, Nov 27, 2014 at 03:18:49PM +0100, Stefan Roese wrote:
> >>This sentence "We support only one NAND chip now" is not true any more.
> >>Multipl
this single chip.
thanks
Huang Shijie
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parameters defined, including the dummy cycle information. I think it
> might be more sustainable to try to support CFI [2] and SFDP [3] for
> detecting new flash, rather than adding new table entries ad-hoc.
I think different chip vendors may have different format to store the
info, just l
On Tue, Jul 29, 2014 at 10:08:43PM -0700, Brian Norris wrote:
>
> On Mon, Apr 28, 2014 at 11:53:40AM +0800, Huang Shijie wrote:
> > This patch adds the DDR quad read support by the following:
>
> To Mark / linux-spi:
>
> Are DDR modes in the scope of drivers/spi/
On Tue, Apr 29, 2014 at 08:54:24AM +0200, Marek Vasut wrote:
> On Tuesday, April 29, 2014 at 07:18:34 AM, Huang Shijie wrote:
> > For the m25p80.c, @dev stands for a child node for the SPI master,
> > and it points to a spi_device{}. Yes, in this case, the dev->of_node is
>
On Mon, Apr 28, 2014 at 10:23:26PM +0200, Marek Vasut wrote:
> On Monday, April 28, 2014 at 05:53:39 AM, Huang Shijie wrote:
> > We need the SPI NOR child node to store some specific features, such as the
> > dummy cycles for the DDR Quad read.
> >
> > But now, we only
properties.
Signed-off-by: Huang Shijie
---
.../devicetree/bindings/mtd/fsl-quadspi.txt| 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
ind
We need a DT property to store the dummy cycles for DDR Quad read.
This is a common feature for the SPI NOR flash, such as Spansion and Micron
chips.
Add this file to describe this specific SPI NOR flash features which will
be referred by the SPI NOR flash drivers.
Signed-off-by: Huang Shijie
This patch adds the DDR(or DTR) quad read support for the Micron
SPI NOR flash.
Tested with n25q256a.
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-nor/spi-nor.c |5 +
include/linux/mtd/spi-nor.h |1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd
The NOR flash can supports dual/quad/ddr-quad read.
Add more flags for these read transfers.
>From the datasheet, the chip support the 64K sector erase operation.
So remove the SECT_4K for the chip which makes the flash_erase faster.
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-nor/
for Spansion s25fl128s NOR flash.
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-nor/spi-nor.c | 54 +++-
include/linux/mtd/spi-nor.h |8 -
2 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd
mtd_speedtest: finished
=
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-nor/fsl-quadspi.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c
b/drivers/mtd/spi-nor/fsl-quadspi.c
We can get the read/write/erase opcode from the spi nor framework now.
What's more is that we can get the correct dummy cycles.
This patch uses the information stored in the spi_nor{} to remove the
hardcode in the fsl_qspi_init_lut().
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-no
tch set:
For patch 1, please see the old discusstion:
http://lists.infradead.org/pipermail/linux-mtd/2014-April/053370.html
For patch 2, please see the old discusstion:
http://lists.infradead.org/pipermail/linux-mtd/2014-April/053374.html
Huang Shijie (10):
mtd: spi-nor: fi
fsl_quadspi.c.
It is not convenient for us to get come information from the SPI NOR flash.
This patch adds a new field @np to spi_nor{}, it points to the child node for
the SPI NOR flash.
Signed-off-by: Huang Shijie
---
drivers/mtd/devices/m25p80.c |1 +
drivers/mtd/spi-nor/spi-nor.c
ti-block erase speed is 495 KiB/s
mtd_speedtest: finished
=
(5) Conclusion:
The DDR quad read could be 49799 KiB/s.
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-nor/fsl-quadspi.c | 62 +++--
1
For the DDR Quad read, the dummy cycles maybe 3 or 6 which is less then 8.
The dummy cycles is actually 8 for SPI fast/dual/quad read.
This patch makes preparations for the DDR quad read, it fixes the wrong dummy
value for both the spi-nor.c and m25p80.c.
Signed-off-by: Huang Shijie
---
This ia
On Thu, Apr 24, 2014 at 03:41:54PM +0200, Marek Vasut wrote:
> On Thursday, April 24, 2014 at 06:58:40 AM, Huang Shijie wrote:
> > On Wed, Apr 23, 2014 at 09:48:50PM +0200, Marek Vasut wrote:
> > > On Wednesday, April 23, 2014 at 12:16:53 PM, Huang Shijie wrote:
> > > &g
On Thu, Apr 24, 2014 at 03:43:51PM +0200, Marek Vasut wrote:
> On Thursday, April 24, 2014 at 06:53:34 AM, Huang Shijie wrote:
> > On Wed, Apr 23, 2014 at 09:45:57PM +0200, Marek Vasut wrote:
> > > On Wednesday, April 23, 2014 at 12:16:50 PM, Huang Shijie wrote:
> > >
On Wed, Apr 23, 2014 at 09:48:50PM +0200, Marek Vasut wrote:
> On Wednesday, April 23, 2014 at 12:16:53 PM, Huang Shijie wrote:
> > Check the "spi-nor,ddr-quad-read-dummy" DT property to get the
> > dummy cycles for DDR quad read.
> >
> > Signed-off-by: Huang
On Wed, Apr 23, 2014 at 09:45:57PM +0200, Marek Vasut wrote:
> On Wednesday, April 23, 2014 at 12:16:50 PM, Huang Shijie wrote:
> > This patch adds the DDR quad read support by the following:
> >
> > [1] add SPI_NOR_DDR_QUAD read mode.
> >
> >
On Wed, Apr 23, 2014 at 09:41:26PM +0200, Marek Vasut wrote:
> On Wednesday, April 23, 2014 at 12:16:49 PM, Huang Shijie wrote:
> > For the DDR Quad read, the dummy cycles maybe 3 or 6 which is less then 8.
> > The dummy cycles is actually 8 for SPI fast/dual/quad read.
> >
We need a DT property to store the dummy cycles for DDR Quad read.
This is a common feature for the SPI NOR flash, such as Spansion and Micron
chips.
Add this file to describe this specific SPI NOR flash features which will
be referred by the SPI NOR flash drivers.
Signed-off-by: Huang Shijie
We can get the read/write/erase opcode from the spi nor framework now.
What's more is that we can get the correct dummy cycles.
This patch uses the information stored in the spi_nor{} to remove the
hardcode in the fsl_qspi_init_lut().
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-no
sion:
The DDR quad read could be 49799 KiB/s.
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-nor/fsl-quadspi.c | 59 ++--
1 files changed, 55 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c
b/drivers/mtd/spi-nor/fsl-quadspi.c
i
For the DDR Quad read, the dummy cycles maybe 3 or 6 which is less then 8.
The dummy cycles is actually 8 for SPI fast/dual/quad read.
This patch makes preparations for the DDR quad read, it fixes the wrong dummy
value for both the spi-nor.c and m25p80.c.
Signed-off-by: Huang Shijie
Check the "spi-nor,ddr-quad-read-dummy" DT property to get the
dummy cycles for DDR quad read.
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-nor/fsl-quadspi.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c
b/drive
properties.
Signed-off-by: Huang Shijie
---
.../devicetree/bindings/mtd/fsl-quadspi.txt| 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
ind
Spansion NOR.
[3] set the dummy with 8 for DDR quad read.
The m25p80.c can not support the DDR quad read, the SPI NOR controller
can set the dummy value in its driver, such as fsl-quadspi.c.
Test this patch for Spansion s25fl128s NOR flash.
Signed-off-by: Huang Shijie
---
drivers/mtd/spi
-April/053370.html
For patch 2, please see the old discusstion:
http://lists.infradead.org/pipermail/linux-mtd/2014-April/053374.html
Huang Shijie (7):
mtd: spi-nor: fix the wrong dummy value
mtd: spi-nor: add DDR quad read support
Documentation: mtd: add a new document for
I think it only makes sense to move those that depend on the
> same core code (i.e., spi-nor.c), or have a close relation to it (so
> Lee's st_spi_fsm.c is a candidate).
yes, i mean the st_spi_fsm.c and other drivers which will use the
spi-nor core code in the future.
thanks
Huang Shi
On Wed, Apr 09, 2014 at 10:48:37AM -0700, Brian Norris wrote:
> On Mon, Feb 24, 2014 at 06:37:37PM +0800, Huang Shijie wrote:
> > This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor
> > layer.
> ...
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c b
d create a patch or several patches to add the MTD_SPI_NOR
to the defconfigs.
Another method is to select the MTD_SPI_NOR which we enable the MTD.
>
> Also, I think m25p80.c is no longer a "self-contained MTD device driver"
> and should be moved under drivers/mtd/spi-nor/.
If
于 2014年04月09日 11:36, Brian Norris 写道:
For any additional comments/corrections (I have a few), please just
submit patches on top, rather than resending the whole series.
thanks a lot!
i am happy that we can add more features on base of the spi nor framework.
Huang Shijie
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于 2014年03月28日 17:31, Lothar Waßmann 写道:
Hi,
Huang Shijie wrote:
于 2014年03月28日 17:00, Sascha Hauer 写道:
- disables swapping of BB marks in the FCB the ROM won't swap bytes.
We can not disable the swapping in the FCB in the imx28.
The DISBBM bit in the FCB does _NOT_ exit in the imx28&
于 2014年03月28日 17:33, Huang Shijie 写道:
于 2014年03月28日 17:01, Lothar Waßmann 写道:
There is no need for the ROM code to access any other partition than
the bootloader itself. Thus Linux can perfectly well be booted from
Assume the ROM only access the partition which contains the
bootloader, and
the
(but we do not do the swapping to
these pages),
what will happen?
thanks
Huang Shijie
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于 2014年03月28日 17:00, Sascha Hauer 写道:
- disables swapping of BB marks in the FCB the ROM won't swap bytes.
We can not disable the swapping in the FCB in the imx28.
The DISBBM bit in the FCB does _NOT_ exit in the imx28's FCB.
thanks
Huang Shijie
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.
thanks
Huang Shijie
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于 2014年03月27日 20:21, Lothar Waßmann 写道:
I can assure you that the>100.000 i.MX28 based modules, that we sold
up to now boot from NAND just fine without any block mark swapping in
the U-Boot pages.
Our driver should follow the Reference manual, not the product.
thanks
Huang Shijie
--
On Wed, Mar 26, 2014 at 12:55:02PM +0100, Lothar Waßmann wrote:
> Hi,
>
> Huang Shijie wrote:
> > 于 2014年03月26日 16:51, Lothar Waßmann 写道:
> > > I don't see why this should not be supported on i.MX28 (i.MX23 doesn't
> > > do byteswapping anyway,
0 of
metadata area for
every page before programming NAND Flash. ROM when loading firmware,
copies back
the value at metadata[0] to BI offset in page data. The following figure
shows how the
factory bad block marker is preserved."
So please the imx28 should _NOT_ support this feature.
thank
wapping except the imx23.
So, there are some places should be changed with this patch:
[1] the subpage hook,
Please also change the gpmi_ecc_read_subpage() too.
[2] the OOB hook,
Please also change the gpmi_ecc_read_oob().
[3] the markbad hook,
Please also change the gpmi_block_markbad() .
thanks
Huang Shijie
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Our ROM guy had confirmed that the Rom will disable the swapping if we
set the DISBBM bit.
But please do not change any logic for imx23/imx28.
I really do not know what's the benefit we can get from this patch.
Please send the new version about this patch if you want this feature.
th
SBBM bit.
I am not sure if the ROM still do the swapping for the uboot when we set
DISBBM bit.
thanks
Huang Shijie
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于 2014年03月20日 17:21, Lothar Waßmann 写道:
Hi,
Huang Shijie wrote:
于 2014年03月19日 21:23, y...@karo-electronics.de 写道:
configurable via DT. This is required for the Ka-Ro electronics
platforms.
If you disable the swapping, you will disable the NAND boot in actually.
No. All our modules do boot
于 2014年03月19日 21:23, y...@karo-electronics.de 写道:
configurable via DT. This is required for the Ka-Ro electronics
platforms.
If you disable the swapping, you will disable the NAND boot in actually.
do you need the nand boot?
could you please tell me more detail background?
thanks
Huang
On Mon, Feb 24, 2014 at 06:37:34PM +0800, Huang Shijie wrote:
Hi Brian:
Could you please review this patch set? I really hope it can be merged
as soon as possibel. But now, the patch set has stalled for a long time.
Since you have pushed the patches for m25p80.c, i have to rebase this
y not an important issue for me. :)
thanks
Huang Shijie
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f I need to resend the patch set again, i can change to move the
commands to the new header.
thanks
Huang Shijie
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This patch adds the document for the SPI NOR framework.
Signed-off-by: Huang Shijie
---
fix a typo
---
Documentation/mtd/spi-nor.txt | 59 +
1 files changed, 59 insertions(+), 0 deletions(-)
create mode 100644 Documentation/mtd/spi-nor.txt
diff --git
Use the new SPI nor framework, and rewrite the m25p80:
(0) remove all the NOR comands.
(1) change the m25p->command to an array.
(2) implement the necessary hooks, such as m25p80_read/m25p80_write.
Tested with the m25p32.
Signed-off-by: Huang Shijie
---
add back the dependency information
于 2014年02月24日 23:17, Konstantin Tokarev 写道:
should know
sorry for my poor english. thanks a lot.
Huang Shijie
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#bonnie++ -d tmp -u 0 -s 10 -r 5
For ubifs:
-
#flash_eraseall /dev/mtd0
#ubiattach /dev/ubi_ctrl -m 0
#ubimkvol /dev/ubi0 -N test -m
#mount -t ubifs ubi0:test tmp
#bonnie++ -d tmp -u 0 -s 10 -r 5
Signed-off-by: Huang Shijie
---
drivers
Add the spi_nor_match_id() to find the proper spi_device_id with the
NOR flash's name in the spi_nor_ids table.
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-nor/spi-nor.c | 12
include/linux/mtd/spi-nor.h | 12
2 files changed, 24 insertions(+), 0 dele
This patch adds the document for the SPI NOR framework.
Signed-off-by: Huang Shijie
---
Documentation/mtd/spi-nor.txt | 59 +
1 files changed, 59 insertions(+), 0 deletions(-)
create mode 100644 Documentation/mtd/spi-nor.txt
diff --git a/Documentation
Use the new SPI nor framework, and rewrite the m25p80:
(0) remove all the NOR comands.
(1) change the m25p->command to an array.
(2) implement the necessary hooks, such as m25p80_read/m25p80_write.
Tested with the m25p32.
Signed-off-by: Huang Shijie
---
drivers/mtd/devices/m25p80.c | 1
.
@erase: erase a sector of the NOR.
2) Add a new field sst_write_second for the SST NOR write.
Signed-off-by: Huang Shijie
---
include/linux/mtd/spi-nor.h | 110 +++
1 files changed, 110 insertions(+), 0 deletions(-)
diff --git a/include/linux/mtd/spi
This patch adds the binding file for Freescale QuadSPI driver.
Signed-off-by: Huang Shijie
---
.../devicetree/bindings/mtd/fsl-quadspi.txt| 35
1 files changed, 35 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/fsl
SPI NOR chip
New APIs:
spi_nor_scan: used to scan a spi-nor flash.
Signed-off-by: Huang Shijie
---
drivers/mtd/Kconfig |2 +
drivers/mtd/Makefile |1 +
drivers/mtd/spi-nor/Kconfig |6 +
drivers/mtd/spi-nor/Makefile |1 +
drivers/mtd/spi-nor/spi-nor.c
read by
default.
v1 --> v2:
[1] follow Angus's advice, add more hooks and data structrures.
[2] others.
*** BLURB HERE ***
Huang Shijie (8):
mtd: spi-nor: copy the SPI NOR commands to a new header file
mtd: spi-nor: add the basic data structures
m
This patch adds a new header :spi-nor.h,
and copies all the SPI NOR commands and relative macros into this new header.
This hearder can be used by the m25p80.c and other spi-nor controller,
such as Freescale's Quadspi.
Signed-off-by: Huang Shijie
---
include/linux/mtd/spi-nor.h |
rs/spi/spi-foo.c - correct?
Please read the device tree node of your controller, find the code like
...
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p3
oint (2) with all pros-n-cons ?
>
> - A README will helpful to clear all doubts and will ease your implementation
> as well.
> - It will also help in reducing turn-around time to get this framework in
>acceptable state and still keep it generic enough.
>
> You can submi
于 2014年01月17日 16:39, Jagan Teki 写道:
On Fri, Jan 17, 2014 at 12:24 PM, Huang Shijie wrote:
On Fri, Jan 17, 2014 at 12:36:08PM +0530, Jagan Teki wrote:
My basic question is like I have a qspi spi controller in my SOC and I
designed two boards B1 and B2
okay.
B1 with quad spi controller
OR device node in the device tree. In the probe, it will call
the m25p80.c to probe the NOR device.
But if we connect other device to it. you should set another device node for it.
I am not sure if your controller driver can works as the spi-imx.c
thanks
Huang Shijie
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spi controller in my SOC and I
> designed two boards B1 and B2
okay.
> B1 with quad spi controller connected with non-flash as a slave and B2
> with quad spi controller connected
> with quad flash as a slave.
You can use the framework for B2. But for B1, you should not use the fr
于 2014年01月16日 03:15, Jagan Teki 写道:
Hi,
On Wed, Dec 25, 2013 at 11:20 AM, Huang Shijie wrote:
1.) Why add a new framework for SPI NOR?
The SPI-NOR controller such as Freescale's Quadspi controller is working
in a different way from the SPI bus. It should knows the NOR comman
On Mon, Jan 06, 2014 at 02:04:33PM +0800, Shawn Guo wrote:
> On Wed, Dec 25, 2013 at 02:19:27PM +0800, Huang Shijie wrote:
> > This patch uses the IRQ_TYPE_LEVEL_HIGH/IRQ_TYPE_NONE to replace
> > the hardcode.
> >
> > Signed-off-by: Huang Shijie
> > ---
> &g
This patch uses the IRQ_TYPE_LEVEL_HIGH/IRQ_TYPE_NONE to replace
the hardcode.
Signed-off-by: Huang Shijie
---
arch/arm/boot/dts/vf610.dtsi | 37 +++--
1 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot
This patch adds the binding file for Freescale QuadSPI driver.
Signed-off-by: Huang Shijie
---
.../devicetree/bindings/mtd/fsl-quadspi.txt| 26
1 files changed, 26 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/fsl
Add the spi_nor_match_id() to find the proper spi_device_id
in the spi_nor_ids table.
Signed-off-by: Huang Shijie
---
drivers/mtd/spi-nor/spi-nor.c | 12
include/linux/mtd/spi-nor.h | 12
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd
#bonnie++ -d tmp -u 0 -s 10 -r 5
For ubifs:
-
#flash_eraseall /dev/mtd0
#ubiattach /dev/ubi_ctrl -m 0
#ubimkvol /dev/ubi0 -N test -m
#mount -t ubifs ubi0:test tmp
#bonnie++ -d tmp -u 0 -s 10 -r 5
Signed-off-by: Huang Shijie
---
drivers
Use the new SPI nor framework, and rewrite the m25p80:
(0) remove all the NOR comands.
(1) change the m25p->command to an array.
(2) implement the necessary hooks, such as m25p_read/m25p_write.
Tested with the m25p32.
Signed-off-by: Huang Shijie
---
drivers/mtd/devices/Kconfig |
This patch adds a new header :spi-nor.h,
and copies all the SPI NOR commands and relative macros into this new header.
This hearder can be used by the m25p80.c and other spi-nor controller,
such as Freescale's Quadspi.
Signed-off-by: Huang Shijie
---
include/linux/mtd/spi-nor.h |
SPI NOR chip
New APIs:
spi_nor_scan: used to scan a spi-nor flash.
Signed-off-by: Huang Shijie
---
drivers/mtd/Kconfig |2 +
drivers/mtd/Makefile |1 +
drivers/mtd/spi-nor/Kconfig |6 +
drivers/mtd/spi-nor/Makefile |1 +
drivers/mtd/spi-nor/spi-nor.c
[2] add a new "priv" field for spi_nor{}.
[3] add the Freescale Quadspi driver which supports the Quad read by
default.
v1 --> v2:
[1] follow Angus's advice, add more hooks and data structrures.
[2] others.
Huang Shijie (7):
mtd:
.
@erase: erase a sector of the NOR.
2) Add a new field sst_write_second for the SST NOR write.
Signed-off-by: Huang Shijie
---
include/linux/mtd/spi-nor.h | 109 +++
1 files changed, 109 insertions(+), 0 deletions(-)
diff --git a/include/linux/mtd/spi
chips.
>
> Ping? Do you have any comment here? It seems like a more precise DT
sorry, i did not see this email.
> binding could still be useful for GPMI NAND.
agree.
but i suggest add a more common DT for it. I think other drivers may also
use it.
We have "nand-ecc-mode&q
since that is the default
> already in the absence of the keyword. This property is most
> useful to declare yet not enable by default components in .dtsi
> files and to do enable them in individual board files if
> applicable. This aspect need not be shown in the binding example
> of a QSPI controller.
>
> I'd suggest to use symbolic names for the flags in the last
> interrupt specifier cell, as you do for clock items.
I will use the symbolic name if it has.
But if it not have a symbolic name, i have to keep it as it is now.
Thanks
Huang Shijie
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On Thu, Dec 12, 2013 at 01:45:24PM +0530, Sourav Poddar wrote:
> On Thursday 12 December 2013 01:25 PM, Huang Shijie wrote:
> >>
> >>+ if (spi->master->configure_from_slave)
> >>+ m25p80_fill_flash_information(flash);
> >>+
> >You h
SPI-NOR framework?
And i think the enable_mmap/disable_mmap is not needed too.
All the three hooks are used to set the SPI bus controller.
And the SPI-NOR framework only handles the issues between the
SPI bus controller and the SPI-NOR, or the SPI-NOR controller and the
SPI-NOR.
thanks
Huang Shijie
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于 2013年11月07日 18:07, Huang Shijie 写道:
In default way, we use the ecc_strength/ecc_step size calculated by ourselves
and use all the OOB area.
This patch adds a new property : "fsl,use-minimum-ecc"
If we enable it, we will firstly try to use the datasheet's minimum required
ECC
ep size.
Signed-off-by: Huang Shijie
---
v1 -- > v2: rebase this patch on the latest l2-mtd.
v2 -- > v3: change the descriptions.
---
.../devicetree/bindings/mtd/gpmi-nand.txt |8
drivers/mtd/nand/gpmi-nand/gpmi-nand.c |3 +++
2 files changed, 11
software may choose an
implementation-defined ECC scheme.
this description is better then mine.
thanks
Huang Shijie
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于 2013年10月28日 11:05, Huang Shijie 写道:
> In default way, we use the ecc_strength/ecc_step size calculated by ourselves
> and use all the OOB area.
>
> This patch adds a new property : "fsl,use-minimum-ecc"
>
> If we enable it, we will firstly try to use the datash
ep size.
Signed-off-by: Huang Shijie
---
v1 --> v2:
based on David's patch to fix the regression.
---
.../devicetree/bindings/mtd/gpmi-nand.txt |6 ++
drivers/mtd/nand/gpmi-nand/gpmi-nand.c |3 +++
2 files changed, 9 insertions(+), 0 deletions(-)
ength_ds fields in the nand_chip{}).
So we may have free space in the OOB area by using the minimum ECC, and we may
support JFFS2 with some SLC NANDs, such as Micron's SLC NAND.
Signed-off-by: Huang Shijie
---
.../devicetree/bindings/mtd/gpmi-nand.txt |6 ++
drivers/mtd/nand/g
flect your intention of
using the datasheet's minimum required ECC (from ONFI or from the
driver's full ID table)?
yes, it's okay to me.
thanks
Huang Shijie
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ayout" ?
I am not understand "the ECC selection itself".
thanks
Huang Shijie
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AND ecc layout which may has free space in the OOB
(for some SLC nand, we may support the JFFS2 with the new NAND ecc layout).
Signed-off-by: Huang Shijie
---
.../devicetree/bindings/mtd/gpmi-nand.txt |4
drivers/mtd/nand/gpmi-nand/gpmi-nand.c |7 ++-
2 files ch
AND ecc layout which may has free space in the OOB
(for some SLC nand, we may support the JFFS2 with the new NAND ecc layout).
Signed-off-by: Huang Shijie
---
.../devicetree/bindings/mtd/gpmi-nand.txt |4
drivers/mtd/nand/gpmi-nand/gpmi-nand.c |7 ++-
2 files ch
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