Hi Daniel,
On 01/25/2015 05:42 PM, Daniel Lezcano wrote:
The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.
This dri
Hi Chris,
On 11/25/2014 05:37 PM, Chris Zhong wrote:
The maximum cpu frequency of rk3288 can up to 1.8Ghz, but the vdd_cpu need set
to 1.4v. I've tested these patches on rk3288 evb board.
I'm not sure why you need this patch, I think we have a discuss
for the cpu operating point before.
In this
The DCLK_VOP0 will change the parent clock's rate, we don't want
to change the PLLs rate other than npll. So we select the npll
as parent directly.
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rk3
Kever Yang (2):
clk: rockchip: leave npll for VOP0 only
arm: dts: rockchip: select npll as parent of DCLK_VOP0
arch/arm/boot/dts/rk3288.dtsi | 2 ++
drivers/clk/rockchip/clk-rk3288.c | 24
2 files changed, 14 insertions(+), 12 deletions(-)
--
1.9.1
--
To
This patch adds document for how to use the opetion property
assigned-clock-force-rates.
We may use this property to force update a clock setting.
Signed-off-by: Kever Yang
---
Documentation/devicetree/bindings/clock/clock-bindings.txt | 7 +--
1 file changed, 5 insertions(+), 2 deletions
When we assgined a clock rate in dts, we may need to update
the clock setting like PLLs who can get the same output rate with
different parameter even if we don't need to change the rate.
Kever Yang (2):
clk: add property for force to update clock setting
dt-bindings: clk: add documen
it so that we can use in dts.
Signed-off-by: Kever Yang
---
include/dt-bindings/clock/rk3288-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3288-cru.h
b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..3dcc906 100644
--- a/include/dt-bindings/clock
On 11/06/2014 02:22 PM, Caesar Wang wrote:
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power mode.
The RK3288 PMU is dedicated for managing the power ot the whole chip.
Signed-off-by: Jack Dai
Signed-off-by
Hi Caesar,
On 11/06/2014 02:22 PM, Caesar Wang wrote:
Signed-off-by: Jack Dai
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
pls detail the reason why you need to add all the clocks into
power-controller node.
---
Changes in v8:
- DTS go back to v2
Changes in v7: None
Changes
From: Heiko Stuebner
Makes it possible to define a rockchip,pmu phandle in the cpus node directly
referencing the pmu syscon instead of searching for specific compatible.
The old way of finding the pmu stays of course available.
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
This patch add pmu reference and enable-method for smp
Signed-off-by: Kever Yang
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- add this patch
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b
This patch add intmem node des which is needed by platsmp.c
Signed-off-by: Kever Yang
---
Changes in v5: None
Changes in v4:
- remove "rockchip,rk3288-pmu-sram" because we don't use it here
Changes in v3:
- remove 'enable-method' from this patch
- add compitable name
This patch add reset for CPU nodes to use the reset controller.
Signed-off-by: Kever Yang
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b
u-intmem
Changes in v2:
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment
Kever Yang (6):
ARM: rockchip: convert to regmap and use pmu syscon if available
ARM: rock
This patch add pmu reference and enable-method for smp
Signed-off-by: Kever Yang
---
Changes in v4: None
Changes in v3:
- add this patch
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts
k3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment
Kever Yang (6):
ARM: rockchip: convert to regmap and use pmu syscon if available
ARM: rockchip: add option to access the pmu
From: Heiko Stuebner
Makes it possible to define a rockchip,pmu phandle in the cpus node directly
referencing the pmu syscon instead of searching for specific compatible.
The old way of finding the pmu stays of course available.
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
This patch add reset for CPU nodes to use the reset controller.
Signed-off-by: Kever Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts
This patch add intmem node des which is needed by platsmp.c
Signed-off-by: Kever Yang
---
Changes in v4:
- remove "rockchip,rk3288-pmu-sram" because we don't use it here
Changes in v3:
- remove 'enable-method' from this patch
- add compitable name "rockchip,r
This patch add reset for CPU nodes to use the reset controller.
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5e9c56d..291014d 100644
--- a/arch/arm/boot
For the CA12/CA17 MPCore multiprocessor, the active processors might be
stalled when the individual processor is powered down.
For rk3288, we can avoid this prolbem by softreset the processor before
power it down.
Kever Yang (2):
ARM: rockchip: fix up rk3288 smp cpu hotplug
ARM: dts
cpu starup when actived by 'sev'
- adjust the alignment
Kever Yang (6):
ARM: rockchip: convert to regmap and use pmu syscon if available
ARM: dts: rockchip: use the same pmu node name as before
ARM: rockchip: add option to access the pmu via a phandle in
smp_operations
AR
We use the "rockchip,rk3066-pmu" for rk3288 instead of creat
a new one.
Signed-off-by: Kever Yang
---
Changes in v3:
- add this patch in version 3
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/
This patch add pmu reference and enable-method for smp
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
---
Changes in v3:
- add this patch
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm
This patch add intmem node des which is needed by platsmp.c
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
---
Changes in v3:
- remove 'enable-method' from this patch
- add compitable name "rockchip,rk3288-pmu-sram" for pmu-intmem
Changes in v2:
- adjust the align
v2:
- change the PLL setting of 400M to meet the constraints of TRM
- add review and test tag
- add some explanation in commit message
Kever Yang (2):
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
ARM: dts: enable init rate for clock
arch/arm/boot/dts/rk3288.dtsi | 10 ++
requirement from
display system.
The common-clock-framework will help us to select best source for
child clocks after we init the PLLs propriety.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v2:
- add review and test tag
- add some explanation in commit
This patch add init rate for PLLs and some bus clock from dts for rk3288,
add two clock rate of 400M and 500M into rate table for we will use it.
Kever Yang (2):
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
ARM: dts: enable init rate for clock
arch/arm/boot/dts/rk3288.dtsi
We need to initialize PLL rate and some of bus clock rate while
kernel init, for there is no other module will do that.
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts
This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
Reviewed-by: Heiko Stuebner
---
Changes in v3: None
Changes in v2: None
include/dt-bindings/clock/rk3288-cru.h | 38
clock node in PD_VIDEO and
use new defined clock ID
- split out the patch
Kever Yang (3):
clk: rockchip: add some needed clock binding id for rk3288
clk: rockchip: use the clock id for nodes init
clk: rockchip: add clock node in PD_VIDEO
drivers/clk/rockchip/clk-rk3288.c | 88
This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: Kever Yang
Reviewed-by: Heiko Stuebner
---
Changes in v2: None
include/dt-bindings/clock/rk3288-cru.h | 38 +-
1 file changed, 37
This patch add some clock binding id for different modules
that under development and going to send upstream.
This patch also add the clock node in PD_VIDEO.
Changes in v2:
- split into two patches of add clock node in PD_VIDEO and
use new defined clock ID
Kever Yang (3):
clk: rockchip: add
This patch add some clock binding id for different modules
that under development and going to send upstream.
This patch also add the clock node in PD_VIDEO.
Kever Yang (2):
clk: rockchip: add some needed clock binding id for rk3288
clk: rockchip: use the clock id for nodes init
drivers
This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: Kever Yang
---
include/dt-bindings/clock/rk3288-cru.h | 38 +-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/include/dt
Heiko,
On 09/24/2014 01:52 AM, Heiko Stübner wrote:
Am Montag, 22. September 2014, 19:55:16 schrieb jinkun.hong:
From: "jinkun.hong"
Signed-off-by: Jack Dai
Signed-off-by: Wang Caesar
Signed-off-by: jinkun.hong
---
arch/arm/boot/dts/rk3288.dtsi | 45
++
On 09/23/2014 10:55 AM, jinkun.hong wrote:
From: "jinkun.hong"
Any summary for rk3288 power controller?
Maybe you can say something about how rk3288 TRM described this module.
Signed-off-by: Jack Dai
Signed-off-by: Wang Caesar
Signed-off-by: jinkun.hong
---
arch/arm/boot/dts/rk3288.dts
Hi Mark,
Thanks for your comment.
On 09/17/2014 02:54 AM, Mark Rutland wrote:
On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
This add documentation for rk3288 smp dt binding
Signed-off-by: Kever Yang
---
Changes in v2:
- add documentation
Documentation/devicetree
This patch add intmem node des which is needed by platsmp.c
and enable the smp.
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
---
Changes in v2:
- adjust the alignment
arch/arm/boot/dts/rk3288.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm
This add documentation for rk3288 smp dt binding
Signed-off-by: Kever Yang
---
Changes in v2:
- add documentation
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree
instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment
Kever Yang (3):
Documentation: dt-bindings: add dt binding info for rk3288-smp
ARM: rockchip: add basic smp support for rk3288
ARM: dts: add i
rk3288 is dual-core CPU Soc, we need to enable the smp.
This patchset works with either arch-timer use the phisical counter
in kernel or the firmware initialize the arch-timer virtual counter
offset and use virtual counter in kernel.
Kever Yang (2):
ARM: rockchip: add basic smp support for
This patch add intmem node des which is needed by platsmp.c
and enable the smp.
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts
Mark,
Thanks for your reply and advice.
On 08/28/2014 11:11 PM, Mark Rutland wrote:
On Thu, Aug 28, 2014 at 10:17:58AM +0100, Mark Rutland wrote:
Hi Kever,
On Thu, Aug 28, 2014 at 02:40:17AM +0100, Kever Yang wrote:
We need use the hrtimer, which need the arch-timer to be 'always-o
We need use the hrtimer, which need the arch-timer to be 'always-on'
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..698e6ea 100644
--- a/arc
We need use the hrtimer, which need the arch-timer to be 'always-on'
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..698e6ea 100644
--- a/arc
;
+ #dma-cells = <1>;
+ clocks = <&cru ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ };
+ };
+
xin24m: oscillator {
compatible = "f
ARM_GIC
select CACHE_L2X0
select HAVE_ARM_ARCH_TIMER
Tested-by: Kever Yang
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ned int nr_clk);
void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
unsigned int nr_pll, int grf_lock_offset);
+void rockchip_clk_protect_critical(const char *clocks[], int nclocks);
#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
Tested-by: Kever Yang
On 08/09/2014 06:20 AM, Heiko Stübner wrote:
Am Freitag, 8. August 2014, 14:58:11 schrieb Doug Anderson:
Heiko,
On Fri, Aug 1, 2014 at 1:15 AM, Heiko Stübner wrote:
Am Donnerstag, 31. Juli 2014, 17:30:25 schrieb Mike Turquette:
Quoting Heiko Stübner (2014-07-31 16:29:34)
Hi Mike,
Am Donn
Heiko:
On 07/30/2014 03:12 AM, Heiko Stuebner wrote:
This is needed to access the pl330 dma controllers on Rockchip SoCs.
Signed-off-by: Heiko Stuebner
---
arch/arm/mach-rockchip/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockc
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v5:
- change the sort order of dwc2 in rk3288
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang
---
Changes in v5:
- don't enable otg port for evb
Changes in v4: None
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi | 4
1 file chang
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang
Acked-by: Stephen Warren
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps
Doug had post it seprately.
Changes in v3:
- EHCI and HSIC move new for version 3.
- Rebase
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Do
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang
Acked-by: Stephen Warren
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bin
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang
---
Changes in v4: None
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi | 6 ++
1 file changed, 6
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
---
Changes in v4: None
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2: None
arch/arm/boot
,dwc2" bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
usb: dwc2: add compatible data for rockchip soc
ARM: dts: add rk3288 dwc2 controller support
ARM: dts: Enab
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++
1 file changed, 2
hsotg struct
- From Jingoo's suggestion:
change the commit message
- add dr_mode init from Kconfig
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
k3288 bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
Documentation: dt-bindings: add dt binding info for dwc2 dr_mode
usb: dwc2: add 'mode' which based on Kconfig select or dts setting
Document
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang
---
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi |6 ++
1 file changed, 6 insertions(+)
diff
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
---
Changes in v3:
- Moved out of pin control and sort by base address
Changes in v2:
- change the node name from
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang
Acked-by: Stephen Warren
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
Documentation/
From: Doug Anderson
The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: Doug Anderson
Signed-off-by: Kever Yang
---
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 41
t ordering of EHCI and HSIC in rk3288.dtsi
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
usb: dwc2: add compatible data for rockchip soc
ARM: dts: add rk3288 dwc2 controller support
ARM: dts: Enable USB otg and host1(dwc) on rk3288-evb
Documentation/de
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang
Acked-by: Stephen Warren
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
Documentation/
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
---
Changes in v3:
- Moved out of pin control and sort by base address
Changes in v2:
- change the node name from
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang
---
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi |6 ++
1 file changed, 6 insertions(+)
diff
From: Doug Anderson
The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: Doug Anderson
Signed-off-by: Kever Yang
---
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 41
rk3288 bindings.
- add compatible "snps,dwc2" bingding info
- set most parameters as driver auto-detect
- change the node name from 'dwc2' to 'usb'
- evb patch added in version 2
Doug Anderson (1):
ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi
Kever
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang
---
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
Documentation/devicetree/bindings/usb/dwc2.txt |3 +++
1 fi
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang
---
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts
From: Kever Yang
These patches to add support for dwc2 controller found in
Rockchip processors rk3066, rk3188 and rk3288,
and enable dts for rk3288 evb.
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
- set most parameters as driver a
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
---
Changes in v2:
- change the node name from 'dwc2' to 'usb'
arch/arm/boot/dt
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang
---
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree/bindings/usb/dwc2.txt |2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
These two patches enable the dr_mode for the dwc2 usb
controller. These are split from the patch series adding
rk3288 dwc2 support.
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang
---
drivers/usb/dwc2/platform.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/usb/dwc2/platform.c b/drivers
Some devices with A female host port and without use of usb_id pin
will need this for the otg controller works as device role
during firmware period and works as host role in rich os.
Signed-off-by: Kever Yang
---
drivers/usb/dwc2/core.c | 13 +
drivers/usb/dwc2/core.h
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
add dr_mode as optional properties.
Signed-off-by: Kever Yang
---
Documentation/devicetree/bindings/usb/dwc2.txt |5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree
This path is to add the support for dwc2 controller found ind
Rockchip processors rk3066, rk3188 and rk3288
This patch also add dr_mode for dwc2 driver.
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
ARM: dts: add rk3288 dwc2 controller support
usb: dwc2
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