On Saturday, November 14, 2015 at 08:11:25 PM, Fabio Estevam wrote:
> On Wed, Nov 11, 2015 at 10:07 PM, Marek Vasut <ma...@denx.de> wrote:
> > On Wednesday, February 11, 2015 at 11:22:59 AM, Sean Cross wrote:
> >> The Kosagi Novena mainboard contains an i.MX6, along with
rebase and repost this series, but I'd like to know if there
is some feedback which I should address first.
Thanks!
Best regards,
Marek Vasut
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More majordo
'd like to use that for my own
QSPI driver (the Cadence one), so I'd like to check on the status. Are you
still working on this please ?
Thanks!
Best regards,
Marek Vasut
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On Thursday, October 15, 2015 at 04:10:08 PM, Graham Moore wrote:
> On 08/21/2015 04:20 AM, Marek Vasut wrote:
> > From: Graham Moore <grmo...@opensource.altera.com>
> >
> > Add support for the Cadence QSPI controller. This controller is
> > present in the Altera
ill ever be needed, it can be re-added.
Reviewed-by: Marek Vasut <ma...@denx.de>
Best regards,
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'm likely to publish this new series tomorrow after my tests on a Micron
> memory.
Excellent, please keep me on Cc as I'm already warming up my Spansion part ;-)
Best regards,
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On Saturday, September 05, 2015 at 01:45:01 AM, vikas wrote:
> Hi,
>
> On 08/21/2015 02:20 AM, Marek Vasut wrote:
> > From: Graham Moore <grmo...@opensource.altera.com>
> >
> > Add support for the Cadence QSPI controller. This controller is
> > present in
On Monday, August 31, 2015 at 07:30:37 PM, Graham Moore wrote:
> Hi Marek,
Hi Graham,
> Having some compile issues...see below
>
> On 08/21/2015 04:20 AM, Marek Vasut wrote:
> > From: Graham Moore <grmo...@opensource.altera.com>
> >
> > Add sup
On Thursday, August 27, 2015 at 07:44:34 PM, vikas wrote:
Hi,
On 08/21/2015 02:20 AM, Marek Vasut wrote:
From: Graham Moore grmo...@opensource.altera.com
Add binding document for the Cadence QSPI controller.
Signed-off-by: Graham Moore grmo...@opensource.altera.com
Signed-off
On Wednesday, August 26, 2015 at 12:09:50 AM, vikas wrote:
Hi,
On 08/21/2015 02:20 AM, Marek Vasut wrote:
From: Graham Moore grmo...@opensource.altera.com
Add support for the Cadence QSPI controller. This controller is
present in the Altera SoCFPGA SoCs and this driver has been tested
-by: Nicolas Ferre nicolas.fe...@atmel.com
Acked-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
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On Wednesday, August 26, 2015 at 05:47:37 PM, vikas wrote:
Hi,
Hi,
On 08/25/2015 11:19 PM, Marek Vasut wrote:
On Wednesday, August 26, 2015 at 12:09:50 AM, vikas wrote:
Hi,
On 08/21/2015 02:20 AM, Marek Vasut wrote:
From: Graham Moore grmo...@opensource.altera.com
Add support
Vasut ma...@denx.de
Best regards,
Marek Vasut
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On Tuesday, August 25, 2015 at 12:17:37 PM, Cyrille Pitchen wrote:
Hi Marek,
Hi!
Le 24/08/2015 13:03, Marek Vasut a écrit :
On Monday, August 24, 2015 at 12:14:00 PM, Cyrille Pitchen wrote:
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects
On Monday, August 24, 2015 at 02:49:24 PM, Russell King - ARM Linux wrote:
Hi Russell,
On Mon, Aug 24, 2015 at 01:03:51PM +0200, Marek Vasut wrote:
These are functions, not macros :)
btw is there any reason for these ? I'd say, just put the read*() and
write*() functions directly
On Monday, August 24, 2015 at 06:42:46 PM, Cyrille Pitchen wrote:
Hi Marek,
Hi!
[...]
- * Dummy Cycle calculation for different type of read.
- * It can be used to support more commands with
- * different dummy cycle requirements.
- */
-static inline int
On Monday, August 24, 2015 at 07:04:38 PM, Cyrille Pitchen wrote:
Hi Marek,
Hi!
Le 24/08/2015 13:03, Marek Vasut a écrit :
On Monday, August 24, 2015 at 12:14:00 PM, Cyrille Pitchen wrote:
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects
ack has any value in here, feel free to add it, the bindings look
pretty standard anyway:
Acked-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
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and keep on dialoging with the Micron memory.
Signed-off-by: Cyrille Pitchen cyrille.pitc...@atmel.com
Awesome,
Acked-by: Marek Vasut ma...@denx.de
If this could be applied separately (since I want to use the same functionality
for the Cadence QSPI driver), I'd be really happy too :)
Best
On Monday, August 24, 2015 at 12:13:58 PM, Cyrille Pitchen wrote:
The number of dummy cycles used during Fast Read commands can be reduced
to improve transfer performances. Each manufacturer has a dedicated set of
registers to provide the memory with the exact number of dummy cycles it
should
On Monday, August 24, 2015 at 12:14:00 PM, Cyrille Pitchen wrote:
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI
controller.
Signed-off-by: Cyrille Pitchen cyrille.pitc...@atmel.com
Acked-by: Nicolas
From: Graham Moore grmo...@opensource.altera.com
Add support for the Cadence QSPI controller. This controller is
present in the Altera SoCFPGA SoCs and this driver has been tested
on the Cyclone V SoC.
Signed-off-by: Graham Moore grmo...@opensource.altera.com
Signed-off-by: Marek Vasut ma
From: Graham Moore grmo...@opensource.altera.com
Add binding document for the Cadence QSPI controller.
Signed-off-by: Graham Moore grmo...@opensource.altera.com
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Alan Tull at...@opensource.altera.com
Cc: Brian Norris computersforpe...@gmail.com
Cc
On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote:
Hi,
Hi,
On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote:
I'm not very helpful here, so hopefully Viet can be of more use:
Yup :)
On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote:
On Monday
On Thursday, August 20, 2015 at 08:55:05 AM, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to
Altera EPCS and EPCQ flash chips. This patch adds driver
for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
On Thursday, August 20, 2015 at 10:13:30 AM, Nga Chi wrote:
On Thu, Aug 20, 2015 at 4:03 PM, Marek Vasut ma...@denx.de wrote:
On Thursday, August 20, 2015 at 08:55:05 AM, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables
to find out the
solution so that the driver does not need to do any dirty hacking. And
so, this table should still be here even hardware fix will take place
or not.
[...]
Best regards,
Marek Vasut
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On Thursday, August 20, 2015 at 10:06:29 AM, Viet Nga Dao wrote:
On Thu, Aug 20, 2015 at 3:55 PM, Marek Vasut ma...@denx.de wrote:
On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote:
Hi,
Hi,
On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote:
I'm
On Tuesday, August 18, 2015 at 04:34:53 AM, vikas wrote:
Hi Marek,
Hi,
[...]
+#define CQSPI_POLL_IDLE_RETRY 3
+
+#define CQSPI_REG_SRAM_RESV_WORDS 2
+#define CQSPI_REG_SRAM_PARTITION_WR1
remove unused macros.
+#define
On Tuesday, August 18, 2015 at 04:47:35 AM, Brian Norris wrote:
Hi!
[...]
The only bizzare thing is this stuff above ^ . If I want to pass for
example m25p,fast-read to the SPI NOR connected to this controller, I
have to set
Do we really want to extend m25p80 properties like
On Thursday, August 20, 2015 at 10:19:25 PM, Brian Norris wrote:
On Thu, Aug 20, 2015 at 12:06:36PM +0200, Alexander Stein wrote:
On Thursday 20 August 2015 10:03:38, Marek Vasut wrote:
+Example:
+
+ quadspi_controller_0: quadspi@0x180014a0
not come into play.
This is absolutelly not a SPI NOR address.
Best regards,
Marek Vasut
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On Tuesday, August 18, 2015 at 04:35:55 AM, vikas wrote:
Hi Marek,
On 08/13/2015 08:28 PM, Marek Vasut wrote:
From: Graham Moore grmo...@opensource.altera.com
Add binding document for the Cadence QSPI controller.
Signed-off-by: Graham Moore grmo...@opensource.altera.com
Signed
On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote:
I'm not very helpful here, so hopefully Viet can be of more use:
Yup :)
On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote:
On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote:
Also, I cannot find any
, I cannot find any documentation for this IP block even if I search
through
Quartus/QSys, is there any proper documentation available anywhere?
[...]
Best regards,
Marek Vasut
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From: Graham Moore grmo...@opensource.altera.com
Add binding document for the Cadence QSPI controller.
Signed-off-by: Graham Moore grmo...@opensource.altera.com
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Alan Tull at...@opensource.altera.com
Cc: Brian Norris computersforpe...@gmail.com
Cc
From: Graham Moore grmo...@opensource.altera.com
Add support for the Cadence QSPI controller. This controller is
present in the Altera SoCFPGA SoCs and this driver has been tested
on the Cyclone V SoC.
Signed-off-by: Graham Moore grmo...@opensource.altera.com
Signed-off-by: Marek Vasut ma
On Friday, August 14, 2015 at 05:28:12 AM, Marek Vasut wrote:
From: Graham Moore grmo...@opensource.altera.com
Add support for the Cadence QSPI controller. This controller is
present in the Altera SoCFPGA SoCs and this driver has been tested
on the Cyclone V SoC.
Signed-off-by: Graham
100644 Documentation/devicetree/bindings/nvmem/mxs-ocotp.txt
create mode 100644 drivers/nvmem/mxs-ocotp.c
Very nice, other than the comments from Srinivas, you can add my
Reviewed-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
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On Monday, July 27, 2015 at 10:41:37 AM, Cyrille Pitchen wrote:
Hi Marek,
Le 22/07/2015 15:50, Marek Vasut a écrit :
On Wednesday, July 22, 2015 at 03:17:10 PM, Cyrille Pitchen wrote:
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects a NOR
On Wednesday, July 22, 2015 at 06:59:21 PM, Cyrille Pitchen wrote:
Hi Marek,
Le 22/07/2015 15:43, Marek Vasut a écrit :
On Wednesday, July 22, 2015 at 03:17:07 PM, Cyrille Pitchen wrote:
Depending on the SPI clock frequency, the Fast Read op code and the
Single/Dual Data Rate mode
On Wednesday, July 22, 2015 at 06:25:20 PM, Cyrille Pitchen wrote:
Hi Marek,
Le 22/07/2015 15:41, Marek Vasut a écrit :
On Wednesday, July 22, 2015 at 03:17:06 PM, Cyrille Pitchen wrote:
Once the Quad SPI mode has been enabled on a Micron flash memory, this
device expects ALL
a formula would be needed that translates arbitrary
client settings to transfer size limit and there would be need to
somehow get the client settings to the formula in the dmaengine
driver.
Thanks
Michal
Best regards,
Marek Vasut
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On Wednesday, July 22, 2015 at 10:38:14 AM, Michal Suchanek wrote:
On 22 July 2015 at 10:24, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 10:18:04 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:45
On Wednesday, July 22, 2015 at 09:45:27 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:33, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:30:54 AM, Michal Suchanek wrote:
On 22 July 2015 at 06:49, Vinod Koul vinod.k...@intel.com wrote:
On Tue, Jul 21, 2015 at 10:14
On Wednesday, July 22, 2015 at 03:17:10 PM, Cyrille Pitchen wrote:
This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI
controller.
Signed-off-by: Cyrille Pitchen cyrille.pitc...@atmel.com
---
[...]
+/*
*mtd)
{
return mtd-priv;
[...]
Best regards,
Marek Vasut
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how low you can get with the negotiations ? This way, you'd
be able to effectively auto-detect this value at probe-time.
I might be wrong though :)
Best regards,
Marek Vasut
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On Wednesday, July 22, 2015 at 10:18:04 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:45:27 AM, Michal Suchanek wrote:
On 22 July 2015 at 09:33, Marek Vasut ma...@denx.de wrote:
On Wednesday, July 22, 2015 at 09:30
On Monday, July 20, 2015 at 08:37:01 AM, Stefan Wahren wrote:
Hi Marek,
Hi!
Am 20.07.2015 um 00:07 schrieb Marek Vasut:
On Monday, July 20, 2015 at 12:04:56 AM, Stefan Wahren wrote:
This patch series brings read-only support for the On-Chip OTP cells
in the i.MX23 and i.MX28 processor
On Monday, July 20, 2015 at 08:45:21 AM, Stefan Wahren wrote:
Hi Marek,
Hi!
Am 20.07.2015 um 00:12 schrieb Marek Vasut:
On Monday, July 20, 2015 at 12:04:58 AM, Stefan Wahren wrote:
This patch brings read-only support for the On-Chip OTP cells
in the i.MX23 and i.MX28 processor
On Monday, July 20, 2015 at 11:23:39 AM, Cyrille Pitchen wrote:
Hi Marek,
Hi!
Le 16/07/2015 19:44, Marek Vasut a écrit :
On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote:
Hi!
Both the SPI controller and the NOR flash memory need to agree on the
number of dummy
/355652.htm
l
Are you sure you even want this support in kernel ? Isn't it enough to have
this in some manufacturing-time mutated bootloader to program the OTP once
and never touch it again ?
Best regards,
Marek Vasut
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doing any manipulation with the VDDIO
voltage -- or did I miss that? I seem to remember that the VDDIO
had to be lowered to 2.8V before the fuses could be programmed
and restored to 3.3V afterward. See for example recent mainline
u-boot, drivers/misc/mxs_ocotp.c .
Best regards,
Marek Vasut
latency code.
The latency code can be found into the memory datasheet and depends on the
SPI clock frequency, the Fast Read op code and the Single/Dual Data Rate
mode.
Shouldn't you be able to derive the latency code from the above information,
which you already know then ?
Best regards,
Marek
On Thursday, July 16, 2015 at 03:19:35 AM, Brian Norris wrote:
On Wed, Jul 15, 2015 at 07:15:50PM +0200, Marek Vasut wrote:
On Wednesday, July 15, 2015 at 05:59:46 PM, Brian Norris wrote:
1. Fix up the SPI driver so that it knows how to break large SPI
transfers up into smaller segments
On Wednesday, July 15, 2015 at 05:59:46 PM, Brian Norris wrote:
Hi Michal,
Hi all,
On Wed, Jul 15, 2015 at 01:52:27PM +0200, Marek Vasut wrote:
The problem is, if you add a new DT binding, you'd have to support it
forever, no matter how bad idea that binding turned out to be.
Agreed
with a suggested value which can be tuned depending on the system
seems more viable.
The problem is, if you add a new DT binding, you'd have to support it
forever, no matter how bad idea that binding turned out to be.
Best regards,
Marek Vasut
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On Thursday, June 04, 2015 at 05:40:58 PM, Michal Suchanek wrote:
On 4 June 2015 at 17:28, Marek Vasut ma...@denx.de wrote:
On Thursday, June 04, 2015 at 06:54:00 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:40 PM
nonsense.
Best regards,
Marek Vasut
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On Thursday, June 04, 2015 at 06:21:32 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:53, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:39 PM, Michal Suchanek wrote:
Hello,
Hi,
this patch series makes it possible to access the SPI NOR flash in the
Samsung
On Thursday, June 04, 2015 at 06:31:45 AM, Michal Suchanek wrote:
On 4 June 2015 at 01:03, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:41 PM, Michal Suchanek wrote:
On sunxi the SPI controller currently does not have DMA support and
fails any transfer larger than
On Thursday, June 04, 2015 at 06:54:00 AM, Michal Suchanek wrote:
On 4 June 2015 at 00:58, Marek Vasut ma...@denx.de wrote:
On Wednesday, June 03, 2015 at 11:26:40 PM, Michal Suchanek wrote:
On Exynos it is necessary to set SPI controller parameters that apply to
a SPI slave in a DT subnode
. +
Using this option may severely degrade performance and
+ possibly flash memory life when max_tx_len is
smaller than + flash page size (typically 256 bytes)
Will we need similar patch for all other SPI slave drivers, like SPI NAND ?
Best regards,
Marek Vasut
data transfers are less likely
to be affected.
Sounds like the DMA engine driver should be fixed.
Best regards,
Marek Vasut
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On Wednesday, June 03, 2015 at 11:26:42 PM, Michal Suchanek wrote:
The SPI NOR transfers mysteriously fail so add more debug prints about
SPI transactions.
Signed-off-by: Michal Suchanek hramr...@gmail.com
dev_dbg() and friends would certainly be nicer here.
Best regards,
Marek Vasut
. Change this condition to a warning so that flash without
partitions can be accessed on Exynos.
I have to admit the rationale for this patch is not very clear to me, sorry.
Can you please explain this a bit more ?
Best regards,
Marek Vasut
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: mxs: Add iio-hwmon to mx23 soc)
Reviewed-by: Marek Vasut ma...@denx.de
[...]
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do this.)
Yes, the intent is to fix this by adding dma support to the driver,
eventually.
The patch might be still useful for other hardware with developing SPI
support.
Please just fix the controller driver to correctly handle arbitrary transfer
lengths.
Best regards,
Marek Vasut
...@i2se.com
Reviewed-by: Marek Vasut ma...@denx.de
Best regards,
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you encounter another performance regression after upgrading
to a more modern kernel ;-)
Why don't you use the Altera VIP FB on SoCFPGA ?
Best regards,
Marek Vasut
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More
, but it is
different enough to merit its own driver. Also, this driver uses the
generic phy infrastructure.
Hi,
the register set looks very similar to MXS one indeed. How is it different
please ?
The driver looks OK.
Best regards,
Marek Vasut
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On Wednesday, March 11, 2015 at 10:57:25 PM, Brian Norris wrote:
Almost all flash that are compatible with m25p80 support the JEDEC
READ ID opcode (0x95)
On the 2/2 patch, you claim READ ID is 0x9F . You might want to sort
this inconsistency :) Otherwise ...
Reviewed-by: Marek Vasut ma
...@spectrumdigital.se
Makes sense, thanks!
Reviewed-by: Marek Vasut ma...@denx.de
Best regards,
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some kind of a
of_property_read_u32_range() thingie, which would include this kind of range
checking ? Would it be worth implementing such thing ? What do you think
please ?
[...]
Otherwise,
Reviewed-by: Marek Vasut ma...@denx.de
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On Tuesday, December 23, 2014 at 11:45:59 PM, Stefan Wahren wrote:
Hi Marek,
Hi!
Marek Vasut ma...@denx.de hat am 23. Dezember 2014 um 14:37
geschrieben:
On Monday, December 22, 2014 at 01:14:36 PM, Stefan Wahren wrote:
[...]
Very minor coding style flub in this comment above
On Friday, November 07, 2014 at 05:29:33 PM, Janusz Użycki wrote:
W dniu 2014-11-07 o 15:48, Marek Vasut pisze:
On Friday, November 07, 2014 at 02:23:23 PM, Janusz Użycki wrote:
[...]
Hardware RTS/CTS lines can be occupied by RX/TX of other AUART port
in order to obtain as much uarts
regards,
Marek Vasut
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On Friday, November 07, 2014 at 11:04:27 AM, Janusz Użycki wrote:
W dniu 2014-11-07 o 09:03, Marek Vasut pisze:
On Friday, November 07, 2014 at 02:34:31 AM, Huang Shijie wrote:
why change them to gpio?
+CC Alexandre, since he might be interested :-)
Hardware RTS/CTS lines can be occupied
On Friday, November 07, 2014 at 02:23:23 PM, Janusz Użycki wrote:
[...]
Hardware RTS/CTS lines can be occupied by RX/TX of other AUART port
in order to obtain as much uarts as possible using i.mx283.
Therefore gpios can be used for hardware flow control.
Your logic is outright flawed
, spi will use PIO mode. This patch only
validate on i.mx6, not i.mx5, but encourage ones to apply this patch
on i.mx5 since they share the same IP.
Adding Maerk (who I had to add to earlier versions of this patch).
Looks OK to me.
Acked-by: Marek Vasut ma...@denx.de
Thank you!
Best
On Wednesday, July 23, 2014 at 03:57:35 PM, Herbert Xu wrote:
On Sat, May 24, 2014 at 02:00:03PM +0200, Marek Vasut wrote:
+ }
+#endif
+
+#ifdef CONFIG_CRYPTO_DEV_SUNXI_SS_MD5
+ err = crypto_register_shash(sunxi_md5_alg);
Do not use shash for such device. This is clearly
On Wednesday, July 23, 2014 at 04:13:09 PM, Herbert Xu wrote:
On Wed, Jul 23, 2014 at 04:07:20PM +0200, Marek Vasut wrote:
On Wednesday, July 23, 2014 at 03:57:35 PM, Herbert Xu wrote:
On Sat, May 24, 2014 at 02:00:03PM +0200, Marek Vasut wrote:
+ }
+#endif
+
+#ifdef
On Wednesday, July 23, 2014 at 08:52:12 PM, Corentin LABBE wrote:
Le 23/07/2014 17:51, Marek Vasut a écrit :
On Wednesday, July 23, 2014 at 04:13:09 PM, Herbert Xu wrote:
On Wed, Jul 23, 2014 at 04:07:20PM +0200, Marek Vasut wrote:
On Wednesday, July 23, 2014 at 03:57:35 PM, Herbert Xu
compatible with older versions, so this patch adds those
missing versions in c29x device tree.
Signed-off-by: Nitesh Narayan Lal b44...@freescale.com
Signed-off-by: Vakul Garg b16...@freescale.com
Patch applied.
Are you sure DT changes go through linux-crypto tree ?
Best regards,
Marek Vasut
rickard_strandqv...@spectrumdigital.se
Makes perfect sense.
Acked-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
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will consume quite
a
lot of CPU time to do that, can you not implement DMA here ?
[...]
Best regards,
Marek Vasut
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On Sunday, June 22, 2014 at 01:58:38 PM, Corentin LABBE wrote:
Le 14/06/2014 21:01, Marek Vasut a écrit :
On Tuesday, June 10, 2014 at 02:43:15 PM, LABBE Corentin wrote:
Add necessary changes for configuring and compiling the Security System
driver.
Signed-off-by: LABBE Corentin
On Sunday, June 22, 2014 at 02:33:35 PM, Russell King - ARM Linux wrote:
On Sun, Jun 22, 2014 at 02:23:15PM +0200, Marek Vasut wrote:
On Sunday, June 22, 2014 at 01:58:08 PM, Corentin LABBE wrote:
[...]
+ * This program is free software; you can redistribute it and/or
modify
On Tuesday, June 10, 2014 at 02:43:14 PM, LABBE Corentin wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Signed-off-by: LABBE Corentin
+ drivers/crypto/Makefile
| 1 +
2 files changed, 92 insertions(+)
This should be part of 1/4, otherwise 1/4 just adds dead code.
Best regards,
Marek Vasut
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{
compatible = allwinner,sun4i-a10-spi;
reg = 0x01c17000 0x1000;
Best regards,
Marek Vasut
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On Thursday, May 22, 2014 at 05:09:56 PM, LABBE Corentin wrote:
Do I have to repeat myself ? :)
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
drivers/crypto/Kconfig| 49 ++
drivers/crypto/Makefile |1 +
drivers/crypto/sunxi-ss.c | 1476
.
+
Best regards,
Marek Vasut
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drivers/crypto/sunxi-ss/ .
[...]
Best regards,
Marek Vasut
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On Saturday, May 24, 2014 at 09:20:03 PM, Tomasz Figa wrote:
Hi Marek,
On 24.05.2014 13:21, Marek Vasut wrote:
On Thursday, May 22, 2014 at 05:09:54 PM, LABBE Corentin wrote:
Missing commit message. Please fix this and send a V2.
Signed-off-by: LABBE Corentin clabbe.montj
no other source of information about this available (except
directly comparing two datasheets...).
Better get the DT stuff correctly right from the start. That's why I'm asking
what chips contains the IP block, so we can guess the right name.
Best regards,
Marek Vasut
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On Tuesday, May 06, 2014 at 03:33:51 PM, Kishon Vijay Abraham I wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
[...]
+#define to_dra7xx_pcie(x)container_of((x), struct dra7xx_pcie, pp)
+
+static inline
On Tuesday, April 29, 2014 at 07:18:34 AM, Huang Shijie wrote:
On Mon, Apr 28, 2014 at 10:23:26PM +0200, Marek Vasut wrote:
On Monday, April 28, 2014 at 05:53:39 AM, Huang Shijie wrote:
We need the SPI NOR child node to store some specific features, such as
the dummy cycles for the DDR
, and the SPI NOR
framework can parse it out.
Test this patch for Spansion s25fl128s NOR flash.
Signed-off-by: Huang Shijie b32...@freescale.com
Acked-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
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