Re: [PATCH linux-next (v2) 2/2] clk: bcm6345: Add BCM6345 gated clock support

Hi Simon, Quoting Simon Arlott (2015-12-10 13:50:59) > +#define to_clk_bcm6345(_hw) container_of(_hw, struct clk_bcm6345, hw) > + > +static int clk_bcm6345_enable(struct clk_hw *hw) > +{ > + struct clk_bcm6345 *gate = to_clk_bcm6345(hw); > + > + return regmap_write_bits(gate->map,

Re: [PATCH linux-next (v2) 1/2] clk: Add brcm, bcm6345-gate-clk device tree binding

Hi Simon, Quoting Simon Arlott (2015-12-10 13:49:21) > +periph_clk: periph_clk { > + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm6345-gate-clk"; > + regmap = <_cntl>; > + offset = <0x4>; > + > + #clock-cells = <1>; > + clock-indices = > + <1>,

Re: [PATCH v2 1/3] clk: bcm2835: Add bindings for the auxiliary peripheral clock gates.

Hi Arnd, Quoting Arnd Bergmann (2015-12-30 01:29:02) > On Tuesday 29 December 2015 16:15:09 Rob Herring wrote: > > On Mon, Dec 28, 2015 at 4:39 PM, Michael Turquette > > <mturque...@baylibre.com> wrote: > > > Quoting Eric Anholt (2015-12-24 15:45:15) >

Re: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc

Hello Jiancheng Xue, Quoting Jiancheng Xue (2015-12-29 17:43:47) > The CRG(Clock and Reset Generator) block provides clock > and reset signals for other modules in hi3519 soc. > > Signed-off-by: Jiancheng Xue > --- > .../devicetree/bindings/clock/hi3519-crg.txt |

Re: [PATCH 1/5] clk: mediatek: Refine the makefile to support multiple clock drivers

Quoting James Liao (2015-12-29 22:27:41) > Add a Kconfig to define clock configuration for each SoC, and > modify the Makefile to build drivers that only selected in config. > > Signed-off-by: Shunli Wang > Signed-off-by: James Liao Looks

Re: [PATCH 3/5] clk: mediatek: Add MT2701 clock support

Hi James, Quoting James Liao (2015-12-29 22:27:43) > +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init); > +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg", mtk_infrasys_init); > +CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt2701-pericfg", mtk_pericfg_init); >

Re: [PATCH 2/5] clk: mediatek: Add dt-bindings for MT2701 clocks

James, Quoting James Liao (2015-12-29 22:27:42) > From: Shunli Wang > > Add MT2701 clock dt-bindings, include topckgen, apmixedsys, > infracfg, pericfg and subsystem clocks. > > Signed-off-by: Shunli Wang > Signed-off-by: James Liao

Re: [PATCH v2 1/3] clk: bcm2835: Add bindings for the auxiliary peripheral clock gates.

Quoting Eric Anholt (2015-12-24 15:45:15) > Michael Turquette <mturque...@baylibre.com> writes: > > > On Fri, Dec 18, 2015 at 8:19 PM, Rob Herring <r...@kernel.org> wrote: > >> On Tue, Dec 15, 2015 at 03:35:57PM -0800, Eric Anholt wrote: > >>> These wi

Re: [PATCH v2 0/5] clk: lpc32xx: add clock support for NXP LPC32xx

On 12/21, Vladimir Zapolskiy wrote: > Hi Stephen, Michael, > > On 06.12.2015 12:45, Vladimir Zapolskiy wrote: > > This changeset adds common clock framework driver for NXP LPC32xx > > boards. > > > > The change can be applied without any dependencies, LPC32xx device tree > > and mach changes

Re: [PATCH v2 1/3] clk: bcm2835: Add bindings for the auxiliary peripheral clock gates.

he clk driver patch then we can send the binding description through the DT tree and take the header and C file through the clk tree in one patch. Regards, Mike -- Michael Turquette CEO BayLibre - At the Heart of Embedded Linux http://baylibre.com/ -- To unsubscribe from this list: send the l

Re: [PATCH v2 2/3] clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.

const struct of_device_id bcm2835_aux_clk_of_match[] = { > + { .compatible = "brcm,bcm2835-aux", }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, bcm2835_aux_clk_of_match); > + > +static struct platform_driver bcm2835_aux_clk_driver = { > + .driver = {

Re: [PATCH 1/3] dt-bindings: regulator/clock/mfd: Reorganize S2MPS-family bindings

e family), > - split clock block to clock/samsung,s2mps11.txt, > - split regulator block to regulator/samsung,s2mps11.txt. > > Signed-off-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Acked-by: Michael Turquette <mturque...@baylibre.com> > ---

Re: [PATCH v1 2/4] clk: rockchip: set an id for crypto clk

my ack: Acked-by: Michael Turquette <mturque...@baylibre.com> Regards, Mike > --- > drivers/clk/rockchip/clk-rk3288.c | 2 +- > include/dt-bindings/clock/rk3288-cru.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/rockchip/clk

Re: [GIT PULL] On-demand device probing

Quoting Rafael J. Wysocki (2015-10-25 06:54:39) > On Sun, Oct 25, 2015 at 12:06 AM, Mark Brown wrote: > > On Sat, Oct 24, 2015 at 04:17:12PM +0200, Rafael J. Wysocki wrote: > > > >> Well, I'm not quite sure why exactly everyone is so focused on probing > >> here. > > > >

Re: [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent

Quoting Heiko Stübner (2015-10-11 03:43:27) > Hi Sjoerd, > > Am Freitag, 9. Oktober 2015, 13:35:55 schrieb Sjoerd Simons: > > On Thu, 2015-10-08 at 17:10 +0200, Heiko Stuebner wrote: > > > Am Donnerstag, 8. Oktober 2015, 15:31:16 schrieb Sjoerd Simons: > > > > The clock branches leading to

Re: [git pull] clk: shmobile: Add new Renesas CPG/MSSR DT bindings for

Quoting Geert Uytterhoeven (2015-10-20 11:49:58) > Hi Mike, Stephen, > > The following changes since commit 64291f7db5bd8150a74ad2036f1037e6a0428df2: > > Linux 4.2 (2015-08-30 11:34:09 -0700) > > are available in the git repository at: > >

Re: [PATCH v2 3/4] clk: berlin: bg2q: remove CLK_IGNORE_UNUSED flag for sdio clk

Quoting Michael Turquette (2015-10-21 02:30:39) > Quoting Jisheng Zhang (2015-10-20 04:16:46) > > Since we have added the necessary two clks' properties in dts, we can > > remove the "sdio" clk's CLK_IGNORE_UNUSED flag now. > > > > Signed-off-by: Jisheng Zha

Re: [PATCH v2 4/4] clk: berlin: bg2: remove CLK_IGNORE_UNUSED flag for sdio clk

Quoting Jisheng Zhang (2015-10-20 04:16:47) > The clocks' properties have been already properly set, so there's no > need to set this flag for sdio0 and sdio1 clk any more. > > Signed-off-by: Jisheng Zhang Applied to clk-next. Regards, Mike > --- >

Re: [PATCH v2 3/4] clk: berlin: bg2q: remove CLK_IGNORE_UNUSED flag for sdio clk

Quoting Jisheng Zhang (2015-10-20 04:16:46) > Since we have added the necessary two clks' properties in dts, we can > remove the "sdio" clk's CLK_IGNORE_UNUSED flag now. > > Signed-off-by: Jisheng Zhang Applied to clk-next. Regards, Mike > --- > drivers/clk/berlin/bg2q.c

Re: [PATCH v4 1/5] [RFC] clk: shmobile: Add new Renesas CPG/MSSR DT bindings

Hi Geert, Quoting Geert Uytterhoeven (2015-10-16 05:49:16) > On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse > Generator) and MSSR (Module Standby and Software Reset) blocks are > intimately connected, and share the same register block. > > Hence it makes sense to describe

Re: [PATCH 01/10] clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

Quoting Andrzej Hajda (2015-10-20 02:22:32) > HDMI driver must re-parent respective muxes during HDMI-PHY on/off > to HDMI-PHY output clocks. To reference those clocks their > definitions should be added. > > Signed-off-by: Andrzej Hajda > --- >

Re: [PATCH v4 5/5] [RFC] clk: shmobile: r8a7795: Add new CPG/MSSR driver

Hi Geert, Quoting Geert Uytterhoeven (2015-10-16 05:49:20) > +static void __init r8a7795_cpg_mssr_init(struct device_node *np) > +{ > + struct regmap *regmap; > + u32 reg, cpg_mode; > + > + regmap = syscon_regmap_lookup_by_phandle(np, "renesas,modemr"); > + if

Re: [PATCH V3 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree

Quoting Shengjiu Wang (2015-10-10 03:15:06) > Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also > one clock of SPDIF, which is missed before. > > We found an issue that imx can't enter low power mode with spdif > if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because

Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

Quoting Krzysztof Kozlowski (2015-10-15 16:46:27) > On 15.10.2015 19:31, Tomeu Vizoso wrote: > > When the DISP1 power domain is powered off, there's two clocks that need > > to be temporarily reparented to OSC, and back to their original parents > > when the domain is powered on again. > > > > We

Re: [PATCH 5/5] clk: berlin: bg2: remove CLK_IGNORE_UNUSED flag for sdio clk

Quoting Jisheng Zhang (2015-10-11 22:46:36) > The axi clock properties already exists, so there's no need to set this > flag for sdio0 and sdio1 clk any more. > > Signed-off-by: Jisheng Zhang Applied to clk-next. Regards, Mike > --- > drivers/clk/berlin/bg2.c | 4 ++-- >

Re: [PATCH 4/5] clk: berlin: bg2q: remove CLK_IGNORE_UNUSED flag for sdio clk

Quoting Jisheng Zhang (2015-10-11 22:46:35) > Since we have added the necessary axi clk properties in dts, we can > remove the "sdio" clk's CLK_IGNORE_UNUSED flag now. > > Signed-off-by: Jisheng Zhang Applied to clk-next. Regards, Mike > --- > drivers/clk/berlin/bg2q.c |

Re: [RESEND PATCH v16 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs

Quoting Doug Anderson (2015-08-28 14:08:52) Mike, On Fri, Aug 28, 2015 at 1:02 PM, Michael Turquette mturque...@linaro.org wrote: Hi Doug, Quoting Doug Anderson (2015-08-27 19:03:20) Kevin, On Thu, Aug 27, 2015 at 5:24 PM, Kevin Hilman khil...@kernel.org wrote

Re: [RESEND PATCH v16 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs

Hi Doug, Quoting Doug Anderson (2015-08-27 19:03:20) Kevin, On Thu, Aug 27, 2015 at 5:24 PM, Kevin Hilman khil...@kernel.org wrote: That is not really workable: the attach and detach happen in probe/remove path; if you do not have driver for the device you will miss the clocks for it.

Re: [PATCH V1 0/3] fix clock issue for fsl,spdif

Quoting Shengjiu Wang (2015-08-11 02:26:51) fix clock issue for fsl,spdif Shengjiu Wang (3): ARM: imx6q: Add SPDIF_GCLK clock in clock tree ARM: imx6sl: Add SPDIF_GCLK clock in clock tree ARM: imx6sx: Add SPDIF_GCLK clock in clock tree Hello Shengjiu Wang, Please move the dts

Re: [PATCH 3/4 v3][RFC] arm64: renesas: Add initial r8a7795 SoC support

Quoting Geert Uytterhoeven (2015-08-04 05:34:06) On Tue, Aug 4, 2015 at 2:22 PM, Laurent Pinchart laurent.pinch...@ideasonboard.com wrote: On Monday 03 August 2015 01:53:23 Kuninori Morimoto wrote: --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -0,0 +1,93 @@ +/ { +

Re: [RESEND PATCH v5] clk: mediatek: Export CPU mux clocks for CPU frequency control

Quoting Pi-Cheng Chen (2015-08-17 01:56:45) From: pi-cheng.chen pi-cheng.c...@linaro.org This patch adds CPU mux clocks which are used by Mediatek cpufreq driver for intermediate clock source switching. Signed-off-by: Pi-Cheng Chen pi-cheng.c...@linaro.org Reviewed-by: Daniel Kurtz

Re: [RFC PATCH 0/8] clk: qoriq: Move chip-specific knowledge into driver

through the freescale tree? If so feel free to add, Acked-by: Michael Turquette mturque...@baylibre.com Regards, Mike For more detail, see the commit message of patch 4. Scott Wood (8): ARM: dts: ls1021a: Fix clockgen node cpufreq: qoriq: Don't look at clock implementation details

Re: [PATCH 1/2] clk: add lpc18xx creg clk driver

Hi Joachim, Quoting Joachim Eastwood (2015-07-11 14:48:26) +static void __init lpc18xx_creg_clk_init(struct device_node *np) +{ + const char *clk_32khz_parent; + struct regmap *syscon; + + syscon = syscon_node_to_regmap(np-parent); + if (IS_ERR(syscon)) { +

Re: [PATCH 3/3] clk: add bindings for the Ux500 clocks

isn't preferred but I guess we've been supporting it all this time: Acked-by: Michael Turquette mturque...@baylibre.com --- Ulf/Mike: please ACK this patch so I can take it through ARM SoC. --- Documentation/devicetree/bindings/clock/ux500.txt | 64 +++ 1 file changed

Re: [PATCH v12 17/21] h8300: clock driver

Hello Sato-san, Unfortunately this patch did not Cc myself, Stephen Boyd or the linux-...@vger.kernel.org mailing list. As such Stephen and I did not have a chance to review it. Even more unfortunate was that it was ninja merged by maintainers without our ack. :-/ Quoting Yoshinori Sato

Re: [PATCH v7 3/5] clk: Supply the critical clock {init, enable, disable} framework

Hi Lee, + linux-clk ml Quoting Lee Jones (2015-07-22 06:04:13) These new API calls will firstly provide a mechanisms to tag a clock as critical and secondly allow any knowledgeable driver to (un)gate clocks, even if they are marked as critical. Suggested-by: Maxime Ripard

Re: [PATCH v7 3/5] clk: Supply the critical clock {init, enable, disable} framework

Quoting Lee Jones (2015-07-28 06:00:55) On Tue, 28 Jul 2015, Maxime Ripard wrote: On Mon, Jul 27, 2015 at 09:53:38AM +0100, Lee Jones wrote: On Mon, 27 Jul 2015, Maxime Ripard wrote: On Wed, Jul 22, 2015 at 02:04:13PM +0100, Lee Jones wrote: These new API calls will firstly

Re: [PATCH v7 0/5] clk: Provide support for always-on clocks

Quoting Lee Jones (2015-07-22 06:04:10) Lots of platforms contain clocks which if turned off would prove fatal. The only way to recover from these catastrophic failures is to restart the board(s). Now, when a clock provider is registered with the framework it is possible for a list of

Re: [PATCH v7 3/5] clk: Supply the critical clock {init, enable, disable} framework

Quoting Lee Jones (2015-07-27 01:53:38) On Mon, 27 Jul 2015, Maxime Ripard wrote: On Wed, Jul 22, 2015 at 02:04:13PM +0100, Lee Jones wrote: These new API calls will firstly provide a mechanisms to tag a clock as critical and secondly allow any knowledgeable driver to (un)gate clocks,

Re: [PATCH v6 0/3] cpufreq: Use cpufreq-dt driver for Exynos3250

Quoting Kukjin Kim (2015-07-23 21:08:27) On 07/24/15 12:40, Kukjin Kim wrote: On 07/24/15 09:30, Michael Turquette wrote: Quoting Kukjin Kim (2015-07-07 07:43:31) Bartlomiej Zolnierkiewicz wrote: [...] Chanwoo Choi (3): clk: samsung: exynos3250: Add cpu clock configuration

RE: [PATCH v6 0/3] cpufreq: Use cpufreq-dt driver for Exynos3250

Quoting Kukjin Kim (2015-07-07 07:43:31) Bartlomiej Zolnierkiewicz wrote: Hi, Hi, On Thursday, July 02, 2015 09:42:38 AM Chanwoo Choi wrote: This patchset use cpufreq-dt driver to support Exynos3250 cpufreq and tested it on Exynos3250-based Rinato board. Depends on:

Re: [PATCH v2 3/9] arm: twr-k70f120m: clock driver for Kinetis SoC

Quoting Paul Osmialowski (2015-07-04 14:50:03) Hi Arnd, I'm attaching excerpt from Kinetis reference manual that may make situation clearer. Hi Paul, Can you please post the patch in the body of the email instead of an attachment? It makes it easier to review. Another small nitpick is that

Re: [PATCH v5 1/2] dt-bindings: mediatek: Add MT8173 cpufreq driver binding

Quoting Viresh Kumar (2015-07-08 04:19:00) On 01-07-15, 10:16, Pi-Cheng Chen wrote: This patch adds device tree binding document for MT8173 cpufreq driver. Signed-off-by: Pi-Cheng Chen pi-cheng.c...@linaro.org Reviewed-by: Michael Turquette mturque...@baylibre.com --- .../devicetree

Re: [PATCH v6 1/4] dt-bindings: mediatek: Add MT8173 CPU DVFS clock bindings

Quoting Pi-Cheng Chen (2015-07-09 03:27:38) This patch adds the clock and regulator consumer properties part of document for CPU DVFS clocks on Mediatek MT8173 SoC. Signed-off-by: Pi-Cheng Chen pi-cheng.c...@linaro.org Acked-by: Michael Turquette mturque...@baylibre.com Regards, Mike

Re: [PATCH 1/2] dt-bindings: mediatek: Add MT8173 cpufreq driver binding

/bindings/clock/clock-bindings.txt Please add, Reviewed-by: Michael Turquette mturque...@baylibre.com Thanks, Mike +- operating-points: Table of frequencies and voltage CPU could be transitioned into, + Frequency should be in KHz units and voltage should

Re: [PATCH v2 00/14] ARM: shmobile: Add CPG Clock Domains

Quoting Geert Uytterhoeven (2015-06-15 09:15:04) On Thu, May 28, 2015 at 8:53 PM, Geert Uytterhoeven geert+rene...@glider.be wrote: Hi all, This patch series adds Clock Domain support to the Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain,

Re: [PATCH v2 13/14] clk: shmobile: mstp: Consider zb_clk suitable for power management

Quoting Geert Uytterhoeven (2015-05-28 11:53:38) Currently the CPG Clock Domain code looks for MSTP clocks to power manage a device. Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0), the Bus State Controller (BSC) is not power-managed by an MSTP clock, but by a plain CPG

Re: [PATCH v7 5/6] ARM: dts: enable clock support for Broadcom Cygnus

: Acked-by: Michael Turquette mturque...@baylibre.com arm-soc guys, Any chance you can pick this up? Alternatively I can take it through the clk tree with an Ack. Regards, Mike --- arch/arm/boot/dts/bcm-cygnus-clock.dtsi | 89 +-- 1 file changed, 61 insertions

Re: [PATCH 1/2] clk: keystone: add support for post divider register for main pll

Quoting Murali Karicheri (2015-05-29 09:04:12) Main PLL controller has post divider bits in a separate register in pll controller. Use the value from this register instead of fixed divider when available. Signed-off-by: Murali Karicheri m-kariche...@ti.com Applied to clk-next. Regards,

Re: [PATCH v2 4/5] clk: ti: DRA7: Add tbclk data for ehrpwm

Quoting Vignesh R (2015-06-03 04:51:23) tbclk is needed by ehrpwm to generate pwm waveforms. Hence, register the required clock information. Signed-off-by: Vignesh R vigne...@ti.com Looks good to me. Please feel free to add: Acked-by: Michael Turquette mturque...@baylibre.com Regards, Mike

Re: [PATCH v4 3/5] clk: add lpc18xx ccu clk driver

Quoting Joachim Eastwood (2015-05-28 13:31:45) +static struct lpc18xx_clk_branch clk_branches[] = { + {base_apb3_clk, apb3_bus, CLK_APB3_BUS, CCU_BRANCH_IS_BUS}, + {base_apb3_clk, apb3_i2c1, CLK_APB3_I2C1, 0}, + {base_apb3_clk,

Re: [PATCH v4] Add TI CDCE925 I2C controlled clock synthesizer driver

Quoting Mike Looijmans (2015-06-02 22:25:19) This driver supports the TI CDCE925 programmable clock synthesizer. The chip contains two PLLs with spread-spectrum clocking support and five output dividers. The driver only supports the following setup, and uses a fixed setting for the output

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

Quoting Bintian Wang (2015-05-28 19:08:38) Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule

Re: [PATCH v8 2/7] clk: hi6220: Document devicetree bindings for hi6220 clock

Acked-by: Michael Turquette mturque...@linaro.org --- .../devicetree/bindings/clock/hi6220-clock.txt | 34 ++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt diff --git a/Documentation/devicetree/bindings

Re: [PATCH v3 5/6] doc: dt: add documentation for lpc1850-ccu clk driver

Quoting Joachim Eastwood (2015-05-18 15:35:58) Add DT binding documentation for lpc1850-ccu clk driver. Signed-off-by: Joachim Eastwood manab...@gmail.com --- .../devicetree/bindings/clock/lpc1850-ccu.txt | 146 + 1 file changed, 146 insertions(+) create mode

Re: [PATCH v3 4/6] clk: add lpc18xx ccu clk driver

Quoting Michael Turquette (2015-05-27 20:44:24) Hi Joachim, Quoting Joachim Eastwood (2015-05-18 15:35:57) snip +static void lpc18xx_ccu_register_branch_clks(void __iomem *reg_base, +int base_clk_id

Re: [PATCH V4 3/3] OPP: Add 'opp-next' in operating-points-v2 bindings

Quoting Viresh Kumar (2015-04-30 05:08:01) Many platforms require to switch to a intermediate frequency before switching to a final frequency. Or they can switch to only particular OPPs from any OPP. For these add another property in OPP-v2, 'opp-next'. Refer to the bindings for more

Re: [PATCH v6 1/6] clk: iproc: define Broadcom iProc clock binding

Quoting Ray Jui (2015-04-14 12:10:35) Hi Mike, On 4/13/2015 12:40 PM, Ray Jui wrote: Hi Mike, On 4/12/2015 11:02 PM, Michael Turquette wrote: Quoting Ray Jui (2015-04-12 21:08:32) On 4/10/2015 5:12 PM, Michael Turquette wrote: Quoting Ray Jui (2015-03-17 22:45:17) Document

Re: [PATCH v6 1/6] clk: iproc: define Broadcom iProc clock binding

Quoting Ray Jui (2015-04-12 21:08:32) On 4/10/2015 5:12 PM, Michael Turquette wrote: Quoting Ray Jui (2015-03-17 22:45:17) Document the device tree binding for Broadcom iProc architecture based clock controller Signed-off-by: Ray Jui r...@broadcom.com Reviewed-by: Scott Branden

Re: [PATCH v7 4/7] clk: Add clock driver for mb86s7x

Quoting Vincent Yang (2015-03-04 03:04:03) From: Jassi Brar jaswinder.si...@linaro.org The CRG11 clock controller is managed by remote f/w. This driver simply maps Linux CLK ops onto mailbox api. Signed-off-by: Andy Green andy.gr...@linaro.org Signed-off-by: Vincent Yang

Re: [PATCH v5] clk: Add PWM clock driver

Quoting Philipp Zabel (2015-03-12 03:04:17) Am Freitag, den 13.02.2015, 20:18 +0100 schrieb Philipp Zabel: Some board designers, when running out of clock output pads, decide to (mis)use PWM output pads to provide a clock to external components. This driver supports this practice by

Re: [PATCH v6 1/6] clk: iproc: define Broadcom iProc clock binding

Quoting Ray Jui (2015-03-17 22:45:17) Document the device tree binding for Broadcom iProc architecture based clock controller Signed-off-by: Ray Jui r...@broadcom.com Reviewed-by: Scott Branden sbran...@broadcom.com --- .../bindings/clock/brcm,iproc-clocks.txt | 171

Re: [PATCH 3/4] clk: Provide always-on clock support

Quoting Jassi Brar (2015-03-02 02:28:44) On 2 March 2015 at 15:48, Lee Jones lee.jo...@linaro.org wrote: On Mon, 02 Mar 2015, Jassi Brar wrote: On Mon, Mar 2, 2015 at 2:06 PM, Lee Jones lee.jo...@linaro.org wrote: On Sat, 28 Feb 2015, Jassi Brar wrote: On 28 February 2015 at 02:44,

Re: [STLinux Kernel] [PATCH 3/4] clk: Provide always-on clock support

Quoting Lee Jones (2015-03-02 00:16:06) On Sat, 28 Feb 2015, Maxime Coquelin wrote: Hi Lee, On 02/27/2015 10:14 PM, Lee Jones wrote: Lots of platforms contain clocks which if turned off would prove fatal. The only way to recover from these catastrophic failures is to restart the

Re: [PATCH 2/7] clk: Add basic infrastructure for Pistachio clocks

Quoting Andrew Bresticker (2015-03-30 17:15:43) On Mon, Mar 30, 2015 at 4:59 PM, Stephen Boyd sb...@codeaurora.org wrote: On 02/24/15 19:56, Andrew Bresticker wrote: + +void pistachio_clk_force_enable(struct pistachio_clk_provider *p, + unsigned int *clk_ids,

Re: [PATCH/RFC 1/5] clk: shmobile: rcar-gen2: Add CPG Clock Domain support

Quoting Geert Uytterhoeven (2015-03-18 12:46:53) Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system