On Wed, Apr 15, 2015 at 12:47 PM, Michael Welling mwell...@ieee.org wrote:
On Wed, Apr 15, 2015 at 09:43:30PM +0300, Tero Kristo wrote:
On 04/15/2015 05:09 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 09:34:48AM +0300, Tero Kristo wrote:
On 04/15/2015 12:17 AM, Michael Welling wrote:
Quoting Viresh Kumar (2015-03-05 00:59:50)
On 5 March 2015 at 13:12, Sascha Hauer s.ha...@pengutronix.de wrote:
We have clk_set_parent for changing the parent and clk_set_rate to
change the rate. Use the former for changing the parent and the latter
for changing the rate. What you are
Quoting Viresh Kumar (2015-03-05 03:02:06)
On 5 March 2015 at 16:21, Sascha Hauer s.ha...@pengutronix.de wrote:
Given the variance of different SoCs I don't think it makes sense
to try to handle all these cases. Instead the cpufreq-dt driver
should just call clk_set_rate() on the CPU clock
Quoting Ray Jui (2015-03-06 12:07:13)
Hi Mike,
On 3/6/2015 11:55 AM, Mike Turquette wrote:
Quoting Sascha Hauer (2015-02-26 00:43:19)
On Wed, Feb 25, 2015 at 11:42:44PM -0800, Ray Jui wrote:
On 2/25/2015 10:51 PM, Sascha Hauer wrote:
On Wed, Feb 25, 2015 at 10:13:15PM -0800, Ray Jui
Quoting Lee Jones (2015-03-04 04:00:03)
Mike,
Do you want me to resend this set with Robert's Reviewed-by applied,
or are you happy to apply it yourself?
No need for the resend. I am hoping for a final review from a DT human.
This approach looks fine to me. In practice I think it is
Quoting Sascha Hauer (2015-02-26 00:43:19)
On Wed, Feb 25, 2015 at 11:42:44PM -0800, Ray Jui wrote:
On 2/25/2015 10:51 PM, Sascha Hauer wrote:
On Wed, Feb 25, 2015 at 10:13:15PM -0800, Ray Jui wrote:
Hi Sascha,
On 2/25/2015 9:54 PM, Sascha Hauer wrote:
Hi Ray,
On Wed, Feb
Quoting Vincent Yang (2015-02-05 18:10:49)
From: Jassi Brar jaswinder.si...@linaro.org
The CRG11 clock controller is managed by remote f/w.
This driver simply maps Linux CLK ops onto mailbox api.
Signed-off-by: Jassi Brar jaswinder.si...@linaro.org
Signed-off-by: Andy Green
Quoting Vincent Yang (2015-02-05 18:10:49)
+static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct mb86s70_crg11 *crg11 = data;
+ struct clk_init_data init;
+ u32 cntrlr, domain, port;
+ struct crg_clk *crgclk;
+ struct clk *clk;
Quoting Lee Jones (2015-02-25 07:48:08)
On Wed, 25 Feb 2015, Rob Herring wrote:
On Mon, Feb 23, 2015 at 11:23 AM, Mike Turquette mturque...@linaro.org
wrote:
Quoting Lee Jones (2015-02-18 08:15:00)
Much h/w contain clocks which if turned off would prove fatal. The
only way
Quoting Lee Jones (2015-02-18 08:15:00)
Much h/w contain clocks which if turned off would prove fatal. The
only way to recover is to restart the board(s). This driver takes
references to clocks which are required to be always-on in order to
prevent the common clk framework from trying to
Quoting Thomas Petazzoni (2015-02-20 09:04:29)
The Armada 39x, contrary to its predecessor, has a configurable
reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
previous SoCs, it was fixed to 25 Mhz and described directly as such
in the Device Tree.
For Armada 39x, we need to
Quoting Russell King - ARM Linux (2015-02-16 03:27:24)
On Fri, Feb 13, 2015 at 07:57:13PM +0100, Sascha Hauer wrote:
I agree that it's a bit odd, but I think it has to be like this.
Consider that you request a rate of 100Hz, but the clock can only
produce 99.5Hz, so due to rounding
...@samsung.com
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Lee Jones lee.jo...@linaro.org
Cc: Liam Girdwood lgirdw...@gmail.com
Cc: Mark Brown broo...@kernel.org
Cc: Mike Turquette mturque...@linaro.org
Acked-by: Michael Turquette mturque...@linaro.org
Cc: Stephen Boyd sb...@codeaurora.org
Cc
Quoting Ken Westfield (2015-01-22 13:41:22)
On Mon, Jan 19, 2015 at 06:05:27PM -0800, Stephen Boyd wrote:
This patchset adds support for the low power audio subsystem (LPASS)
clock controller hardware. I split out the #define patch for IPQ so that
it can go through the clock tree and the
Quoting Lee Jones (2015-01-26 03:14:00)
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
.../devicetree/bindings/clock/st/st,clk-domain.txt | 34
++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/st/st,clk-domain.txt
Quoting Peter Griffin (2015-01-20 07:32:41)
Debugging eMMC on upstream kernels it has been noticed that when the
targetpack configures MMC0 clock to 200Mhz (required to switch to
HS200) then everything works OK. However if the kernel sets the
clock rate using clk_set_rate, then the eMMC card
Quoting James Liao (2015-01-07 18:55:01)
Hi Matthias,
On Wed, 2015-01-07 at 18:22 +0100, Matthias Brugger wrote:
2015-01-07 4:25 GMT+01:00 James Liao jamesjj.l...@mediatek.com:
+
+static void cg_set_mask(struct mtk_clk_gate *cg, u32 mask)
Please add mtk_ prefix to all functions
Quoting Ulf Hansson (2015-01-15 02:04:04)
On 15 January 2015 at 10:20, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On czw, 2015-01-15 at 09:20 +0100, Ulf Hansson wrote:
+ Mike, Stephen (Clock maintainers)
On 12 January 2015 at 10:23, Krzysztof Kozlowski
k.kozlow...@samsung.com
Quoting Heiko Stübner (2015-01-08 14:30:01)
Hi Kever,
Am Montag, 17. November 2014, 22:55:36 schrieb Kever Yang:
To support all kinds of frequency requirement for HDMI on rk3288,
we need a PLL that can change rate at run time.
There are some discussion before at [0], I think we can
Quoting Sebastian Hesselbarth (2015-01-10 05:08:22)
On 09.01.2015 13:13, Jisheng Zhang wrote:
On Wed, 7 Jan 2015 06:30:55 -0800
Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote:
On 07.01.2015 15:22, Jisheng Zhang wrote:
On Wed, 7 Jan 2015 06:11:58 -0800
Sebastian Hesselbarth
Quoting Max Filippov (2015-01-11 23:20:46)
The driver allows using CDCE706 in its default configuration recorded in
EEPROM and adjusting of synthesized clocks by consumers.
Signed-off-by: Max Filippov jcmvb...@gmail.com
Applied.
Regards,
Mike
---
Changes v1-v2:
- add example usage to
On Thu, Jan 8, 2015 at 11:01 PM, Mike Looijmans mike.looijm...@topic.nl wrote:
Just a ping to inform if you've had had time to look at this?
Its in the queue for review this week. A lot to catch up on after the
holidays. Thanks for the ping.
Regards,
Mike
Mike.
On 12/04/2014 08:26 AM, Mike
Quoting Lee Jones (2014-11-25 07:59:18)
Mark, Mike,
Please merge this into your trees for v3.19.
The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1:
Linux 3.18-rc1 (2014-10-19 18:08:38 -0700)
are available in the git repository at:
Quoting Geert Uytterhoeven (2014-11-20 23:38:26)
Hi Magnus,
On Fri, Nov 21, 2014 at 6:54 AM, Magnus Damm magnus.d...@gmail.com wrote:
From my side this series [PATCH v7 0/2] clk: shmobile: DIV6 clock
variable parent support looks quite finalized. Would it be possible
Does this mean I
private data,
which requires us to change the driver to make the assumption that
there is only once instance of the gatable clock control structure.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Mike Turquette mturque...@linaro.org
Cc: linux-ker...@vger.kernel.org
Quoting Arnd Bergmann (2014-11-24 02:50:28)
On Friday 21 November 2014 20:58:01 Grygorii Strashko wrote:
Hi Kevin,
On 11/21/2014 10:06 AM, Geert Uytterhoeven wrote:
On Fri, Nov 21, 2014 at 2:30 AM, Kevin Hilman khil...@kernel.org wrote:
Geert Uytterhoeven ge...@linux-m68k.org writes:
Quoting Philipp Zabel (2014-11-03 01:31:18)
Some board designers, when running out of clock output pads, decide to
(mis)use PWM output pads to provide a clock to external components.
This driver supports this practice by providing an adapter between the
PWM and clock bindings in the device
Quoting Geert Uytterhoeven (2014-11-10 10:49:34)
Commit 8e33f91a0b84ae19 (clk: shmobile: clk-mstp: change to using
clock-indices) forgot to replace all occurrences of
renesas,clock-indices in the driver-specific binding documentation.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Quoting Scott Branden (2014-10-28 16:15:05)
From: Jonathan Richardson jonat...@broadcom.com
Reviewed-by: Arun Parameswaran apara...@broadcom.com
Tested-by: Jonathan Richardson jonat...@broadcom.com
Reviewed-by: JD (Jiandong) Zheng jdzh...@broadcom.com
Reviewed-by: Ray Jui r...@broadcom.com
Quoting Chanwoo Choi (2014-11-18 00:59:41)
This patch adds the support for S2MPS13 PMIC clock which is same with existing
S2MPS14 RTC IP. But, S2MPS13 uses all of clocks (32khz_{ap|bt|cp}).
Cc: Mike Turquette mturque...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed
Quoting Alexandru M Stan (2014-11-14 16:00:03)
This will be used in a later patch for clock phase tuning.
Suggested-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Alexandru M Stan ams...@chromium.org
---
Changes in v2: None
include/dt-bindings/clock/rk3288-cru.h | 10 ++
1
Quoting Haojian Zhuang (2014-11-04 00:15:55)
On Fri, Oct 31, 2014 at 10:13 AM, Chao Xie chao@marvell.com wrote:
From: Chao Xie chao@marvell.com
The patch set focuses at support device tree for clock.
The first part of the patches
clk: mmp: add prefix mmp for structures
:
A simple-framebuffer node represents a framebuffer setup by
the firmware /
bootloader. Such a framebuffer may have a number of clocks in
use, add a
property to communicate this to the OS.
Signed-off-by: Hans de Goede hdego...@redhat.com
Reviewed-by: Mike Turquette mturque...@linaro.org
Quoting Robert Jarzmik (2014-09-20 09:13:45)
Mike Turquette mturque...@linaro.org writes:
Quoting Arnd Bergmann (2014-08-24 05:08:19)
On Sunday 24 August 2014, Robert Jarzmik wrote:
By default, I'd expect Haojian to pick up the patches and send
us a pull request. He sent an Ack
On Tue, Sep 30, 2014 at 3:02 PM, Robert Jarzmik robert.jarz...@free.fr wrote:
Mike Turquette mturque...@linaro.org writes:
Quoting Robert Jarzmik (2014-09-20 09:13:45)
Hi Robert,
Tomeu's stuff won't go into 3.18. I should have circled back to these
patches when that become apparent
hdego...@redhat.com
Acked-by: Mike Turquette mturque...@linaro.org
or
Reviewed-by: Mike Turquette mturque...@linaro.org
I don't know what is the right thing with these binding definitions...
Also I have one suggestion below:
---
Documentation/devicetree/bindings/video/simple-framebuffer.txt | 3
Quoting Thierry Reding (2014-09-23 01:51:31)
On Wed, Sep 10, 2014 at 10:05:17PM +0200, Janusz Użycki wrote:
Hi,
http://patchwork.ozlabs.org/patch/359069/
https://lkml.org/lkml/2014/6/12/186
Will the patch ever included to linux-next?
I've never seen this patch before. From a
Quoting Thierry Reding (2014-09-23 00:22:05)
On Mon, Sep 22, 2014 at 06:46:52PM +0100, Mark Rutland wrote:
On Fri, Sep 19, 2014 at 08:53:48PM +0100, Sean Paul wrote:
Per NVidia, this clock rate should be around 70MHz in
order to properly sample reads on data lane 0. In order
to achieve
Quoting Maxime Ripard (2014-09-11 13:18:17)
The current phase API doesn't look into the actual hardware to get the phase
value, but will rather get it from a variable only set by the set_phase
function.
This will cause issue when the client driver will never call the set_phase
function,
Quoting Zhangfei Gao (2014-09-21 20:20:12)
v5:
0001:
Suggested by Mike, change to clk_ether_prepare since delay required inside
v4:
Drop ir clock, whose register is not in the same region
v3:
Add patches 3, 4, 5 for clocks of watchdog, ir, and i2c
Patches 1, 2 are same as v2
Patches
Quoting Jyri Sarha (2014-09-11 01:44:24)
On 09/10/2014 01:14 AM, Mike Turquette wrote:
Quoting Jyri Sarha (2014-09-05 05:21:34)
The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added
Quoting Tomi Valkeinen (2014-09-19 06:25:48)
On 19/09/14 16:12, Nishanth Menon wrote:
On 09/19/2014 08:07 AM, Tomi Valkeinen wrote:
On 16/09/14 23:40, Jyri Sarha wrote:
The added ti,gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding
Quoting Mark yao (2014-09-12 04:45:27)
The patch add the rest of the indices of the additional reset
registers from the updated TRM.
Signed-off-by: Mark yao mark@rock-chips.com
Applied to clk-next.
Regards,
Mike
---
include/dt-bindings/clock/rk3288-cru.h | 43
Quoting Kever Yang (2014-09-24 06:36:33)
This patch add some clock binding id for different modules
that under development and going to send upstream.
This patch also add the clock node in PD_VIDEO.
Applied both patches to clk-next and fixed up the comment block locally.
Regards,
Mike
Quoting Kever Yang (2014-09-25 00:48:45)
This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Doug Anderson diand...@chromium.org
Reviewed-by: Heiko Stuebner
Quoting Maxime Ripard (2014-09-13 03:26:03)
On Fri, Sep 12, 2014 at 11:16:26AM +0800, Chen-Yu Tsai wrote:
Hi,
On Fri, Sep 12, 2014 at 5:02 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Sat, Sep 06, 2014 at 06:47:24PM +0800, Chen-Yu Tsai wrote:
This patch
Quoting Maxime Ripard (2014-09-11 13:36:23)
Hi Chen-Yu,
On Sat, Sep 06, 2014 at 06:47:21PM +0800, Chen-Yu Tsai wrote:
Hi everyone,
This series unifies the mux and divider parts of the AHB1 clock found
on sun6i and sun8i, while also adding support for the pre-divider on
the PLL6
Quoting Javier Martinez Canillas (2014-09-07 23:49:28)
Hello Mike,
On Mon, Aug 18, 2014 at 10:32 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
This series add support for the clocks present in the Maxim
77802 Power Managment IC. Previously, the series was part
of a
Quoting Chris Zhong (2014-09-03 18:12:38)
+static int rk808_clkout1_is_prepared(struct clk_hw *hw)
+{
+ return 1;
+}
+
snip
+static const struct clk_ops rk808_clkout1_ops = {
+ .is_prepared = rk808_clkout1_is_prepared,
+ .recalc_rate = rk808_clkout_recalc_rate,
+};
Hi
Quoting Zhangfei Gao (2014-08-25 22:46:07)
+static int clk_ether_enable(struct clk_hw *hw)
+{
+ struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
+ u32 val;
+
+ val = readl_relaxed(clk-ctrl_reg);
+ val |= clk-ctrl_clk_mask | clk-ctrl_rst_mask;
+
Quoting Chao Xie (2014-08-25 21:38:18)
From: Chao Xie chao@marvell.com
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. Some clocks has operations of out of reset and enable.
To enable clock, we need do out of reset and
Quoting Chao Xie (2014-08-25 21:38:14)
From: Chao Xie chao@marvell.com
The register used by clk-frac may be shared with
other clocks.
So it needs to use spin lock to protect the register
access.
Signed-off-by: Chao Xie chao@marvell.com
This patch will break against the latest
Quoting Arnd Bergmann (2014-08-24 05:08:19)
On Sunday 24 August 2014, Robert Jarzmik wrote:
By default, I'd expect Haojian to pick up the patches and send
us a pull request. He sent an Ack, but also didn't make it clear
that we should pick them up.
I was thinking that they would go
Quoting Tero Kristo (2014-08-04 05:36:19)
On 08/04/2014 02:37 PM, Peter Ujfalusi wrote:
On 08/01/2014 04:15 PM, Tero Kristo wrote:
Hi,
This patch adds possibility to register external clocks (outside the main
SoC) on TI boards through device tree. Clock sources as such include for
Quoting Maxime Ripard (2014-08-30 13:03:02)
The current phase API doesn't look into the actual hardware to get the phase
value, but will rather get it from a variable only set by the set_phase
function.
This will cause issue when the client driver will never call the set_phase
function,
Quoting Maxime Ripard (2014-08-30 13:03:09)
The MMC clock we thought we had until now are actually not one but three
different clocks.
The main one is unchanged, and will have three outputs:
- The clock fed into the MMC
- a sample and output clocks, to deal with when should we
Quoting Chris Zhong (2014-09-01 02:46:40)
Signed-off-by: Chris Zhong z...@rock-chips.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
Hello Chris,
Thanks for submitting this patch. Could you fill in a proper changelog?
Also you should
Quoting Ulrich Hecht (2014-08-28 08:11:11)
From: Ulrich Hecht ulrich.he...@gmail.com
Support for setting the parent at initialization time based on the current
hardware configuration in DIV6 clocks with selectable parents as found in
the r8a73a4, r8a7740, sh73a0, and other SoCs.
snip
-
Quoting Tuomas Tynkkynen (2014-08-20 14:04:28)
v4 changes:
DFLL:
- fix wrong register accessors used for the DFLL_OUTPUT_CFG register
- I decided to leave the dfll_i2c_{readl,writel} separate since the
correct barrier function still needs to be called
- fix PMIC I2C
Quoting Stefan Assmann (2014-07-31 05:04:29)
On 31.07.2014 13:05, Mark Brown wrote:
On Thu, Jul 31, 2014 at 11:56:15AM +0200, Stefan Assmann wrote:
On 30.07.2014 19:50, Mark Brown wrote:
On Wed, Jul 30, 2014 at 04:02:29PM +0200, Stefan Assmann wrote:
+static int
Quoting Stefan Assmann (2014-07-31 07:05:43)
On 31.07.2014 14:58, Peter Ujfalusi wrote:
On 07/31/2014 03:54 PM, Stefan Assmann wrote:
Why would you do this? The point of a clock provider is that you can
enable/disable the clock on demand. Here you enable the clock and leave it
enabled for
Quoting Heiko Stuebner (2014-07-29 12:12:05)
The clock-tree contains clocks that should never get disabled automatically.
One example are the base ACLKs, the base supplies for all peripherals.
Therefore add a structure similar to the sunxi clock-tree to protect these
special clocks from
Quoting Tushar Behera (2014-07-10 23:18:54)
On 06/13/2014 02:39 AM, Mike Turquette wrote:
Quoting Tushar Behera (2014-06-12 00:29:23)
On Wed, Jun 11, 2014 at 10:20 PM, Mike Turquette mturque...@linaro.org
wrote:
Quoting Tushar Behera (2014-06-10 22:32:17)
When the output clock of AUDSS
Quoting Stefan Assmann (2014-07-24 08:03:32)
+#define to_twl6030_desc(_hw) container_of(_hw, struct twl6030_desc, hw)
+
+static int twl6030_clk32kg_enable(struct clk_hw *hw)
+{
+ struct twl6030_desc *desc = to_twl6030_desc(hw);
+ int ret;
+
+ ret =
Quoting Gabriel FERNANDEZ (2014-07-15 08:20:22)
+static const char ** __init flexgen_get_parents(struct device_node *np,
+ int *num_parents)
+{
+ const char **parents;
+ int nparents, i;
+
+ nparents =
Quoting Gabriel FERNANDEZ (2014-07-15 08:20:16)
Changes in v3:
- Change commit message
- Remove uncessary (void *) cast
- add a block diagram for flexgen clock binding documentation
Changes in v2:
- use static const for clkgen_pll_data and stm_fs tables (from
Peter Griffin review)
Quoting Doug Anderson (2014-07-24 16:06:34)
+ xin24m: xin24m {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ #clock-cells = 0;
+ };
I'm no expert, but strangely every other .dts seems to have the clocks
under a
Quoting Viresh Kumar (2014-07-24 03:39:31)
On 24 July 2014 07:54, Rob Herring rob.herr...@linaro.org wrote:
A previous approach tried to compare struct clk pointers, which is a bad
idea since those are just cookies and should not be deref'd by drivers.
However a similar approach would be
Quoting Sylwester Nawrocki (2014-07-03 10:25:53)
On 18/06/14 17:29, Sylwester Nawrocki wrote:
This patch adds helper functions to configure clock parents and rates
as specified through 'assigned-clock-parents', 'assigned-clock-rates'
DT properties for a clock provider or clock consumer
77686 PMIC clocks binding
[PATCH v8 08/13] clk: Add driver for Maxim 77802 PMIC clocks
[PATCH v8 09/13] clk: max77802: Add DT binding documentation
For patches 4-9:
Acked-by: Mike Turquette mturque...@linaro.org
Regards,
Mike
[PATCH v8 10/13] rtc: max77686: Allow the max77686 rtc to wakeup
Quoting Viresh Kumar (2014-07-20 05:07:32)
On 19 July 2014 20:54, Santosh Shilimkar santosh.shilim...@ti.com wrote:
Sorry for jumping late
No, you aren't late. Its just 2 days old thread :)
but one of the point I was raising as part of your
other series was to extend the CPU topology
Quoting Tuomas Tynkkynen (2014-07-10 14:42:36)
This series implements the DFLL/CL-DVFS clock source for the fast CPU
cluster on Tegra124, and a cpufreq driver that uses the DFLL for
clocking the CPU. Most of this is based on Paul Walmsley's public patch
set from December 2013, which is
Quoting Haojian Zhuang (2014-07-02 23:14:33)
On Mon, Jun 30, 2014 at 2:32 AM, Robert Jarzmik robert.jarz...@free.fr
wrote:
Add the clock tree description for the PXA27x based boards.
Signed-off-by: Robert Jarzmik robert.jarz...@free.fr
---
arch/arm/boot/dts/pxa27x.dtsi|
Quoting Viresh Kumar (2014-07-02 19:44:04)
On 3 July 2014 06:54, Stephen Boyd sb...@codeaurora.org wrote:
I gave it a spin. It works so you can have my
Tested-by: Stephen Boyd sb...@codeaurora.org
Thanks, all suggested improvements are made and pushed again with
your Tested-by..
I'm
Quoting Javier Martinez Canillas (2014-07-02 03:17:54)
Hello Mike,
On 07/01/2014 07:29 PM, Mike Turquette wrote:
Quoting Javier Martinez Canillas (2014-06-26 11:15:36)
Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the #clock-cells property
Quoting Chen-Yu Tsai (2014-06-26 08:55:38)
Hi everyone,
This is v4 of the sun8i clock series, which adds basic clock
support for the A23 SoC. It is based on my initial sun8i bring
up series [1]. This series was split up from the original A23
series [2]. Yet to come are more clocks, reset
Quoting Yadwinder Singh Brar (2014-06-29 21:01:36)
Hi Javier,
On Thu, Jun 26, 2014 at 11:45 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Maxim Integrated Power Management ICs are very similar with
regard to their clock outputs. Most of the clock drivers for
these
Quoting Javier Martinez Canillas (2014-06-26 11:15:36)
Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the #clock-cells property is
used to specify the number of cells in a clock provider.
But the binding document is not clear enough that it shall
be
Quoting Javier Martinez Canillas (2014-06-26 11:15:35)
This patch adds a dt-binding include for Maxim 77686
PMIC clock IDs that can be to be shared between the
clk-max77686 clock driver and DeviceTree source files.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Quoting Peter Ujfalusi (2014-06-26 23:01:09)
Hi Mike,
This is a resend of the v2 version of the palmas clock driver which seamingly
missed the 3.16 merge window. I have added Nishanth's Reviewed-by tag to the
patches.
Thanks for the resend. Applied to clk-next.
Regards,
Mike
Changes
Quoting Tushar Behera (2014-06-10 22:32:17)
When the output clock of AUDSS mux is disabled, we are getting kernel
oops while doing a clk_get() on other clocks provided by AUDSS. Though
user manual doesn't specify this dependency, we came across this issue
while disabling the parent of AUDSS
Quoting Tomasz Figa (2014-06-05 15:26:31)
On 05.06.2014 22:35, Doug Anderson wrote:
The aclk66_peric clock is a gate clock with a whole bunch of gates
underneath it. This big gate isn't very useful to include in our
clock tree. If any of the children need to be turned on then the big
Quoting Doug Anderson (2014-06-05 13:35:14)
The aclk66_peric clock is a gate clock with a whole bunch of gates
underneath it. This big gate isn't very useful to include in our
clock tree. If any of the children need to be turned on then the big
gate will need to be on anyway. ...and there
breaker.
Reviewed-by: Mike Turquette mturque...@linaro.org
Regards,
Mike
---
Documentation/devicetree/bindings/rtc/haoyu,hym8563.txt | 3 +++
drivers/rtc/rtc-hym8563.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/rtc
as the family
name for ARM, Ltd. boards.
Signed-off-by: Rob Herring r...@kernel.org
Cc: Mike Turquette mturque...@linaro.org
Acked-by: Arnd Bergmann a...@arndb.de
So it's OK to rename the file and add the new stuff in one commit? I
thought there were some guidelines about doing renames separately
Quoting Alex Elder (2014-05-29 09:53:50)
On 05/29/2014 11:35 AM, Mike Turquette wrote:
Quoting Alex Elder (2014-05-29 06:26:15)
On 05/23/2014 07:53 PM, Mike Turquette wrote:
The above seems like a lot effort to go to. Why not skip all of this and
just implement the prerequisite logic
Quoting Nishanth Menon (2014-05-29 16:22:45)
On 05/26/2014 08:07 AM, Thierry Reding wrote:
On Wed, May 14, 2014 at 12:35:18PM -0700, Mike Turquette wrote:
Quoting Thierry Reding (2014-05-14 07:27:40)
[...]
As for shared clocks I'm only aware of one use-case, namely EMC scaling.
Using
On Mon, May 19, 2014 at 6:20 AM, Tero Kristo t-kri...@ti.com wrote:
On 05/05/2014 10:49 AM, Tero Kristo wrote:
On 05/01/2014 10:00 PM, Mike Turquette wrote:
Quoting Tero Kristo (2014-04-29 07:51:14)
On 04/29/2014 05:15 PM, Sourav Poddar wrote:
We need tbclk clock data for the functioning
...@infradead.org
Cc: Mike Turquette mturque...@linaro.org
Cc: Alexandre Belloni alexandre.bell...@free-electrons.com
Cc: Jisheng Zhang jszh...@marvell.com
Cc: devicetree@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
--
1.9.1
Quoting Simon Horman (2014-05-27 18:08:50)
On Tue, May 27, 2014 at 11:31:42AM +0200, Arnd Bergmann wrote:
On Friday 18 April 2014, Simon Horman wrote:
diff --git a/drivers/clk/shmobile/clk-r8a7779.c
b/drivers/clk/shmobile/clk-r8a7779.c
new file mode 100644
index 000..652ecac
Quoting Nishanth Menon (2014-05-15 05:33:13)
On 05/15/2014 07:18 AM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi Nishant,
On Thursday 15 May 2014 05:16
Quoting Tarek Dakhran (2014-05-23 03:35:42)
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
Quick glance over it.
, and synchronization.
Reviewed-by: Arnd Bergmann a...@arndb.de
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Mike Turquette mturque...@linaro.org
Regards,
Mike
---
.../bindings/clock/ti-keystone-pllctrl.txt | 20
1 file changed, 20 insertions
for Versatile.
Signed-off-by: Rob Herring r...@kernel.org
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/versatile/Makefile | 3 +--
drivers/clk/versatile/clk-integrator.c | 35
--
So then this is a good opportunity to rename that file
Quoting Nishanth Menon (2014-05-16 03:45:57)
Hi,
This patch series has been carried over in vendor kernel for quiet
few years now.
Unfortunately, it was very recently re-discovered and upstream kernel
is noticed to be broken for OMAP5 1.5GHz - at least we are operating
DPLL at frequency
Quoting Alex Elder (2014-05-20 05:52:38)
Add a flag that tracks whether a clock has already been initialized.
This will be used by the next patch to avoid initializing a clock
more than once when it's listed as a prerequisite.
Signed-off-by: Alex Elder el...@linaro.org
---
Quoting Alex Elder (2014-05-20 05:52:39)
@@ -743,11 +746,16 @@ struct clk *kona_clk_setup(struct kona_clk *bcm_clk)
clk = clk_register(NULL, bcm_clk-hw);
if (IS_ERR(clk)) {
pr_err(%s: error registering clock %s (%ld)\n, __func__,
-
Quoting Sylwester Nawrocki (2014-04-11 05:25:49)
+==Assigned clock parents and rates==
+
+Some platforms require static initial configuration of parts of the clocks
+controller. Such a configuration can be specified in a clock consumer node
+through clock-parents and clock-rates DT
Quoting Sylwester Nawrocki (2014-05-19 10:22:51)
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt
b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 700e7aa..bee649b 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++
Quoting Sourav Poddar (2014-04-29 01:34:20)
tbclk does not need to be a composite clock, we can simply
use gate clock for this purpose.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Looks good.
Regards,
Mike
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