[PATCH 01/28] serial: earlycon: allow MEM32 I/O for DT earlycon

is enabled, but enabling it everywhere seems like overkill. Thus systems that need this functionality should select CONFIG_LIBFDT for themselves. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- drivers/of/fdt.c | 2 +- drivers/tty/serial/Makefile | 1 + drivers/tty/

[PATCH 02/28] dt-bindings: ascii-lcd: Document a binding for simple ASCII LCDs

Add documentation for a devicetree binding for simple memory-mapped ASCII LCD displays, such as those found on the Imagination Technologies Boston & Malta development boards. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Documentation/devicetree/bindings/ascii-lc

[PATCH 27/28] dt-bindings: mips: img,boston: Document img,boston binding

Add documentation for the simple img,boston devicetree binding & the boot protocol used to pass the devicetree to the kernel. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- Documentation/devicetree/bindings/mips/img/boston.txt | 15 +++ M

[PATCH 28/28] MIPS: Boston board support

hich is connected to an Intel EG20T Platform Controller Hub to provide a base set of peripherals. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- MAINTAINERS| 3 + arch/mips/Kbuild.platforms | 1 + arch/mi

Re: [PATCH v7,3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes

On Fri, Oct 16, 2015 at 11:31:12AM +0100, James Hogan wrote: > > >> + > > >> + { > > >> + status = "okay"; > > >> + > > >> + nand: nand@1 { > > >> + compatible = "ingenic,jz4780-nand"; > > > > > > Isn't the NAND a micron part? This doesn't seem right. Is the device > > > driver

[PATCH 3/3] MIPS: malta: setup RAM regions via DT

rnel command line) then generate the DT memory node using the provided values. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> --- arch/mips/Kconfig | 2 + arch/mips/boot/dts/mti/malta.dts| 4 + arch/mips/include/asm/mach-malta/malt

[PATCH 0/3] Malta DT memory init

This series extracts some parts of my earlier Malta DT conversion patchset which I believe should be good to merge independently from the rest (which require further interrupt work). Paul Burton (3): MIPS: malta: split obj-y entries across lines MIPS: malta: remove fw_memblock_t abstraction

Re: [PATCH v5 36/37] MIPS: ingenic: initial JZ4780 support

On Mon, May 25, 2015 at 01:03:54PM +0200, Hauke Mehrtens wrote: diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c index 1bed3cb..510fc0d 100644 --- a/arch/mips/jz4740/setup.c +++ b/arch/mips/jz4740/setup.c @@ -83,6 +83,9 @@ arch_initcall(populate_machine); const

Re: [PATCH 00/15] MIPS Malta DT Conversion

On Mon, May 25, 2015 at 02:59:31AM -0500, Rob Landley wrote: On Fri, May 22, 2015 at 10:50 AM, Paul Burton paul.bur...@imgtec.com wrote: This series begins converting the MIPS Malta board to use device tree, which is done with a few goals in mind: - To modernise the Malta board support

Re: [PATCH v4 26/37] MIPS,clk: migrate JZ4740 to common clock framework

On Tue, May 12, 2015 at 07:52:04PM -0700, Michael Turquette wrote: Hi Paul, Quoting Paul Burton (2015-04-24 06:17:26) +static void __init jz4740_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(jz4740_cgu_clocks

[PATCH v5 00/37] JZ4780 CI20 support

/mips/jz4740 can be shared. The series applies atop v4.1-rc4. Review appreciated, and hopefully this can make it in for v4.2. Paul Burton (37): devicetree/bindings: add Ingenic Semiconductor vendor prefix devicetree/bindings: add Qi Hardware vendor prefix MIPS: JZ4740: introduce

[PATCH v5 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT

Use the generic irqchip_init function to probe irqchip drivers using DT, and add the appropriate node to the JZ4740 devicetree in place of the call to mips_cpu_irq_init. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH v5 37/37] MIPS: ingenic: initial MIPS Creator CI20 support

Add an initial device tree for the Ingenic JZ4780 based MIPS Creator CI20 board. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mark Rutland mark.rutl...@arm.com Cc

[PATCH v5 33/37] devicetree: document Ingenic SoC UART binding

Add binding documentation for the UARTs found in Ingenic SoCs. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mark Rutland

[PATCH v5 26/37] MIPS,clk: migrate JZ4740 to common clock framework

Migrate the JZ4740 the qi_lb60 board to use common clock framework via the new Ingenic SoC CGU driver. Note that the JZ4740-specific debugfs code is removed since common clock framework provides its own debug capabilities. Signed-off-by: Paul Burton paul.bur...@imgtec.com Co-authored-by: Paul

[PATCH v5 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix

Define a vendor prefix for Ingenic Semiconductor, a vendor of MIPS-based SoCs. Simply use 'ingenic'. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH v5 10/37] devicetree: document Ingenic SoC interrupt controller binding

Add binding documentation for Ingenic SoC interrupt controllers. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Jason Cooper ja...@lakedaemon.net Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen

[PATCH v5 11/37] MIPS: JZ4740: probe interrupt controller via DT

Declare the JZ4740 interrupt controller for probe via DT using the standard irqchip_init function, and make use of that function to probe the controller by adding the appropriate node to the JZ4740 dtsi. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet

[PATCH v5 35/37] MIPS: JZ4740: use Ingenic SoC UART driver

Remove the serial support from arch/mips/jz4740 make use of the new Ingenic SoC UART driver. This is done for both regular early console output. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter

[PATCH v5 02/37] devicetree/bindings: add Qi Hardware vendor prefix

Define a vendor prefix for Qi Hardware, creators of the Ben Nanonote (qi_lb60) among other open devices. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH v5 36/37] MIPS: ingenic: initial JZ4780 support

Support the Ingenic JZ4780 SoC using the existing code under arch/mips/jz4740 now that it has been generalised sufficiently. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen l...@metafoo.de

[PATCH v5 05/37] MIPS: JZ4740: require include DT

Require a DT for JZ4740 based systems, and add a stub one for the qi_lb60 (Ben NanoNote) board. Devices will be migrated to being probed via this DT over time. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc

[PATCH v5 24/37] devicetree: add Ingenic CGU binding documentation

Document the devicetree binding for Ingenic SoC CGUs, and add headers defining the clock specifiers for clocks provided by the JZ4740 JZ4780 CGU blocks. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars

[PATCH v6 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT

Use the generic irqchip_init function to probe irqchip drivers using DT, and add the appropriate node to the JZ4740 devicetree in place of the call to mips_cpu_irq_init. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH 08/15] of_serial: support for UARTs on I/O ports

If the address provided for the UART is of an I/O port rather than a regular memory address, then set the port iotype appropriately and write the address to iobase rather than mapbase. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- drivers/tty/serial/of_serial.c | 7 ++- 1 file

[PATCH 06/15] MIPS: malta: probe interrupt controllers via DT

at compile time. In order to support both cases the malta_dt_shim code is added in order to detect whether a GIC is present, adjusting the DT to route interrupts correctly and nop out the GIC node if no GIC is found. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/Kconfig

[PATCH 03/15] MIPS: malta: basic DT plumbing

Build a DT for the Malta platform into the kernel, load it probe devices from it. The DT is essentially empty at this point, devices will be added in further patches. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/Kconfig | 2 ++ arch/mips/boot/dts/mti

[PATCH 09/15] MIPS: malta: probe UARTs using DT

. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/boot/dts/mti/malta.dts| 51 + arch/mips/configs/malta_defconfig | 1 + arch/mips/configs/malta_kvm_defconfig | 1 + arch/mips/configs/malta_kvm_guest_defconfig | 1 + arch/mips

[PATCH 15/15] MIPS: malta: setup post-I/O hole RAM on non-EVA

without needing to manually specify mem= parameters on the kernel command line. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/mti-malta/malta-dtshim.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/mips/mti-malta/malta-dtshim.c b/arch/mips/mti-malta

[PATCH 14/15] MIPS: malta: setup RAM regions via DT

line) then generate the DT memory node using the provided values. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/boot/dts/mti/malta.dts | 4 ++ arch/mips/mti-malta/malta-dtshim.c | 104 + arch/mips/mti-malta/malta-memory.c | 88

[PATCH 12/15] MIPS: malta: remove fw_memblock_t abstraction

The fw_getmdesc function fw_memblock_t abstraction is only used by Malta, and so far as I can tell serves no purpose beyond making the code less clear than it could be. Remove the useless level of abstraction. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/fw/fw.h

[PATCH 13/15] MIPS: malta: remove nonsense memory limit

are not enabled at once which makes the comment about highmem macros nonsensical. - I can think of no good reason for it, and nor could anyone else I asked. So remove this memsize limit. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/mti-malta/malta-memory.c | 4 1 file

[PATCH 10/15] MIPS: malta: probe RTC via DT

Add the DT node required to probe the RTC, and remove the platform code that was previously doing it. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/boot/dts/mti/malta.dts | 8 arch/mips/mti-malta/malta-platform.c | 20 2 files changed, 8

[PATCH 07/15] MIPS: remove [SR]ocIt(2) IRQ handling code

it. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/msc01_ic.h | 147 arch/mips/kernel/Makefile| 1 - arch/mips/kernel/irq-msc01.c | 159 --- arch/mips/mti-malta/malta-int.c | 53

[PATCH 00/15] MIPS Malta DT Conversion

maintainable kernel through a combination of the above. Paul Burton (15): MIPS: define GCR_GIC_STATUS register fields MIPS: include errno.h for ENODEV in mips-cm.h MIPS: malta: basic DT plumbing MIPS: i8259: DT support irqchip: mips-gic: register IRQ domain with MIPS_GIC_IRQ_BASE

[PATCH 02/15] MIPS: include errno.h for ENODEV in mips-cm.h

A later patch in this series will include mips-cm.h but does not require errno.h. This leads to a build failure with ENODEV undeclared. Include errno.h from mips-cm.h to pull in the appropriate definition and avoid the build failure. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch

[PATCH 01/15] MIPS: define GCR_GIC_STATUS register fields

Add definitions for the GICEX field in the GCR_GIC_STATUS register to mips-cm.h for use in a later patch. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/mips-cm.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips

[PATCH 11/15] MIPS: malta: probe pflash via DT

CONFIG_MTD_PHYSMAP_OF rather than CONFIG_MTD_PHYSMAP in order to preserve their behaviour. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/boot/dts/mti/malta.dts| 25 arch/mips/configs/malta_defconfig | 2 +- arch/mips/configs/malta_kvm_defconfig

[PATCH 04/15] MIPS: i8259: DT support

Support probing the i8259 programmable interrupt controller, as found on the Malta board, and using its interrupts via device tree. Signed-off-by: Paul Burton paul.bur...@imgtec.com --- arch/mips/include/asm/i8259.h | 1 + arch/mips/kernel/i8259.c | 43

[PATCH 05/15] irqchip: mips-gic: register IRQ domain with MIPS_GIC_IRQ_BASE

. This leads to conflicts between the GIC interrupts and other interrupt controllers. TODO: convert Malta ( SEAD3) to drop the hardcoded numbers instead Signed-off-by: Paul Burton paul.bur...@imgtec.com --- drivers/irqchip/irq-mips-gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v4 33/37] devicetree: document Ingenic SoC UART binding

Add binding documentation for the UARTs found in Ingenic SoCs. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mark Rutland

[PATCH v4 02/37] devicetree/bindings: add Qi Hardware vendor prefix

Define a vendor prefix for Qi Hardware, creators of the Ben Nanonote (qi_lb60) among other open devices. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH v4 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix

Define a vendor prefix for Ingenic Semiconductor, a vendor of MIPS-based SoCs. Simply use 'ingenic'. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH v4 11/37] MIPS: JZ4740: probe interrupt controller via DT

Declare the JZ4740 interrupt controller for probe via DT using the standard irqchip_init function, and make use of that function to probe the controller by adding the appropriate node to the JZ4740 dtsi. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet

[PATCH v4 10/37] devicetree: document Ingenic SoC interrupt controller binding

Add binding documentation for Ingenic SoC interrupt controllers. Signed-off-by: Paul Burton paul.bur...@imgtec.com Acked-by: Rob Herring r...@kernel.org Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Jason Cooper ja...@lakedaemon.net Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen

[PATCH v4 05/37] MIPS: JZ4740: require include DT

Require a DT for JZ4740 based systems, and add a stub one for the qi_lb60 (Ben NanoNote) board. Devices will be migrated to being probed via this DT over time. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc

[PATCH v4 24/37] devicetree: add Ingenic CGU binding documentation

Document the devicetree binding for Ingenic SoC CGUs, and add headers defining the clock specifiers for clocks provided by the JZ4740 JZ4780 CGU blocks. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars

[PATCH v4 26/37] MIPS,clk: migrate JZ4740 to common clock framework

Migrate the JZ4740 the qi_lb60 board to use common clock framework via the new Ingenic SoC CGU driver. Note that the JZ4740-specific debugfs code is removed since common clock framework provides its own debug capabilities. Signed-off-by: Paul Burton paul.bur...@imgtec.com Co-authored-by: Paul

[PATCH v4 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT

Use the generic irqchip_init function to probe irqchip drivers using DT, and add the appropriate node to the JZ4740 devicetree in place of the call to mips_cpu_irq_init. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga

[PATCH v4 36/37] MIPS: ingenic: initial JZ4780 support

Support the Ingenic JZ4780 SoC using the existing code under arch/mips/jz4740 now that it has been generalised sufficiently. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen l...@metafoo.de

[PATCH v4 35/37] MIPS: JZ4740: use Ingenic SoC UART driver

Remove the serial support from arch/mips/jz4740 make use of the new Ingenic SoC UART driver. This is done for both regular early console output. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter

[PATCH v4 37/37] MIPS: ingenic: initial MIPS Creator CI20 support

Add an initial device tree for the Ingenic JZ4780 based MIPS Creator CI20 board. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mark Rutland mark.rutl...@arm.com Cc

[PATCH v4 00/37] JZ4780 CI20 support

/mips/jz4740 can be shared. The series applies atop next-20150421. Review appreciated, and hopefully this can make it in for v4.2. Thanks, Paul Paul Burton (37): devicetree/bindings: add Ingenic Semiconductor vendor prefix devicetree/bindings: add Qi Hardware vendor prefix MIPS: JZ4740

[PATCH v3 02/37] devicetree/bindings: add Qi Hardware vendor prefix

Define a vendor prefix for Qi Hardware, creators of the Ben Nanonote (qi_lb60) among other open devices. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: devicetree@vger.kernel.org --- Changes in v3: - New patch. --- Documentation/devicetree/bindings

[PATCH v3 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix

Define a vendor prefix for Ingenic Semiconductor, a vendor of MIPS-based SoCs. Simply use 'ingenic'. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: devicetree@vger.kernel.org --- Changes in v3: - Rebase. Changes in v2: - None. --- Documentation

[PATCH v3 33/37] devicetree: document Ingenic SoC UART binding

Add binding documentation for the UARTs found in Ingenic SoCs. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: devicetree@vger.kernel.org --- Changes in v3: - Merge binding documentation for Ingenic SoCs whose bindings differ only

[PATCH v3 00/37] JZ4780 CI20 support

. - Capitalise JZ in SoC names, where not identifiers in code, to match the way Ingenic write them. - Further clean up the Ingenic SoC interrupt controller driver and move it under drivers/irqchip/. Review appreciated, and hopefully this can make it into v4.2. Thanks, Paul Paul

Re: [PATCH v3 00/37] JZ4780 CI20 support

On Tue, Apr 21, 2015 at 03:46:27PM +0100, Paul Burton wrote: This series introduces initial support for the Ingenic JZ4780 SoC and the Imagination Technologies MIPS Creator CI20 board which is built around it. In the process the existing JZ4740 qi_lb60 code gains initial support for using

[PATCH v3 24/37] devicetree: add Ingenic CGU binding documentation

Document the devicetree binding for Ingenic SoC CGUs, and add headers defining the clock specifiers for clocks provided by the JZ4740 JZ4780 CGU blocks. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mike Turquette mturque...@linaro.org Cc

[PATCH v3 10/37] devicetree: document Ingenic SoC interrupt controller binding

Add binding documentation for Ingenic SoC interrupt controllers. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: devicetree@vger.kernel.org --- Changes in v3: - Merge documentation for various Ingenic SoCs, which only differ by their compatible

[PATCH 01/36] devicetree/bindings: add Ingenic Semiconductor vendor prefix

Simply use 'ingenic'. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: devicetree@vger.kernel.org --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor

[PATCH 07/36] devicetree: document ingenic,jz4740-intc binding

Add binding documentation for the Ingenic jz4740 interrupt controller. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: devicetree@vger.kernel.org --- .../interrupt-controller/ingenic,jz4740-intc.txt | 24 ++ 1 file changed, 24

[PATCH 15/36] devicetree: add ingenic,jz4740-cgu binding documentation

Document the devicetree binding for the Ingenic jz4740 CGU driver. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mike Turquette mturque...@linaro.org Cc: devicetree@vger.kernel.org --- .../bindings/clock/ingenic,jz4740-cgu.txt | 52

[PATCH 24/36] devicetree: document ingenic,jz4740-uart binding

Add binding documentation for Ingenic jz4740 UARTs. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: devicetree@vger.kernel.org --- .../bindings/serial/ingenic,jz4740-uart.txt| 22 ++ 1 file changed, 22 insertions(+) create

[PATCH 29/36] devicetree: add ingenic,jz4780-cgu binding documentation

Document the devictree binding for the Ingenic jz4780 CGU driver. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: Mike Turquette mturque...@linaro.org Cc: devicetree@vger.kernel.org --- .../bindings/clock/ingenic,jz4780-cgu.txt | 52

[PATCH 25/36] devicetree: document ingenic,jz4780-uart binding

Add binding documentation for Ingenic jz4780 UARTs. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: devicetree@vger.kernel.org --- .../bindings/serial/ingenic,jz4780-uart.txt| 22 ++ 1 file changed, 22 insertions(+) create

[PATCH 31/36] devicetree: document ingenic,jz4780-intc binding

Add binding documentation for the Ingenic jz4780 interrupt controller. Signed-off-by: Paul Burton paul.bur...@imgtec.com Cc: Lars-Peter Clausen l...@metafoo.de Cc: devicetree@vger.kernel.org --- .../interrupt-controller/ingenic,jz4780-intc.txt | 24 ++ 1 file changed, 24