Hi Yakir,
Am Donnerstag, den 07.01.2016, 18:15 +0800 schrieb Yakir Yang:
> Hi Philipp,
>
> Thanks for your fast respond :)
>
> On 01/07/2016 06:04 PM, Philipp Zabel wrote:
> > Am Donnerstag, den 07.01.2016, 17:02 +0800 schrieb Yakir Yang:
> >> RK3229 integrate an D
Am Donnerstag, den 07.01.2016, 17:02 +0800 schrieb Yakir Yang:
> RK3229 integrate an DesignedWare HDMI2.0 controller and an INNO HDMI2.0 phy,
> the max output resolution is 4K.
>
> Signed-off-by: Yakir Yang
It sounds like the INNO HDMI2.0 phy is not necessarily specific to
RK3229 but might also
Am Mittwoch, den 30.12.2015, 09:43 +0800 schrieb Jiancheng Xue:
> Add device tree bindings for Hi3519 system controller.
>
> Signed-off-by: Jiancheng Xue
> ---
> Documentation/devicetree/bindings/mfd/hi3519.txt | 14 ++
> 1 file changed, 14 insertions(+)
> create mode 100644 Documen
H Jiancheng,
Am Mittwoch, den 30.12.2015, 09:43 +0800 schrieb Jiancheng Xue:
> The CRG(Clock and Reset Generator) block provides clock
> and reset signals for other modules in hi3519 soc.
>
> Signed-off-by: Jiancheng Xue
> ---
> .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++
>
et controller framework.
>
> Signed-off-by: Shunli Wang
Acked-by: Philipp Zabel
regards
Philipp
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Am Dienstag, den 05.01.2016, 14:30 +0800 schrieb James Liao:
> From: Shunli Wang
>
> Dt-binding file about reset controller is used to provide
> kinds of definition, which is referenced by dts file and
> IC-specified reset controller driver code.
>
> Signed-off-by: Shunli Wang
> ---
> .../dt-b
Hi James,
Am Dienstag, den 05.01.2016, 14:30 +0800 schrieb James Liao:
> From: Shunli Wang
>
> Add MT2701 clock support, include topckgen, apmixedsys,
> infracfg, pericfg and subsystem clocks.
>
> Signed-off-by: Shunli Wang
> Signed-off-by: James Liao
> ---
> drivers/clk/mediatek/Kconfig
Am Samstag, den 19.12.2015, 11:55 +0100 schrieb Hans de Goede:
> On 18-12-15 12:08, Maxime Ripard wrote:
[...]
> > I guess we could also have something like this:
> >
> >* The driver gets the reference to the reset line using
> > reset_control_get or its shared variant.
> >
> > - If y
Am Dienstag, den 29.12.2015, 16:49 +0800 schrieb Yingjoe Chen:
> On Mon, 2015-11-30 at 22:07 +0100, Philipp Zabel wrote:
> > From: Jie Qiu
> >
> > This patch adds drivers for the HDMI bridge connected to the DPI0
> > display subsystem function block, for the HDMI DDC
From: CK Hu
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
Changes since v7:
- Add 26 MHz PLL reference input
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel
Acked-by: James Liao
---
drivers/clk/mediatek/clk-mt8173.c | 5
From: CK Hu
This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
Changes since v7:
- Describe HDMI PHY PLL output in the
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v7:
- Fix mtk_dpi_power_on reference counting
- Make mtk_dpi_power_off return void
---
drivers/gpu/drm/mediatek/Makefile
From: Jie Qiu
This patch adds drivers for the HDMI bridge connected to the DPI0
display subsystem function block, for the HDMI DDC block, and for
the HDMI PHY to support HDMI output.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v7:
- Fill ELD info
- Fix error
: Philipp Zabel
---
Changes since v7:
- Move PANEL and MIPI_DSI config selection to later patches
- Sort object files alphabetically in Makefile
- Drop mtk_crtc->pipe, use drm_crtc_handle_vblank instead
- Move copied event from mtk_crtc_state back to mtk_crtc
- Wait for exclusive fences on incom
setup this HDMI control bit to enable HDMI output in supervisor mode.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 11 +++
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
Changes since v7:
- Select the PANEL and MIPI_DSI
Add an optional ddc-i2c-bus phandle property that points to
an I2C master controller that handles the connector DDC pins.
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/display/connector/hdmi-connector.txt | 1 +
1 file changed, 1 insertion(+)
diff
Add the device tree binding documentation for Mediatek HDMI,
HDMI PHY and HDMI DDC devices.
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Changes since v7:
- Add the HDMI PLL clock output that is fed back into the
TOP clock module.
- Switch the hdmi_sel mux to it in the example
The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m,
but is routed out of the HDMI PHY module.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
b/drivers/clk/mediatek/clk-mt8173.c
This mux is supposed to select a fitting divider after the PLL
is already set to the correct rate.
Signed-off-by: Philipp Zabel
Acked-by: James Liao
---
Changes since v7:
- The hdmi_sel mux is kept to propagate rate changes,
selecting the divider from the driver would only be necessary
splay subsystem related nodes
arm64: dts: mt8173: Add HDMI related nodes
Jie Qiu (3):
drm/mediatek: Add DPI sub driver
drm/mediatek: Add HDMI support
drm/mediatek: enable hdmi output control bit
Philipp Zabel (5):
dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
clk: mediatek: make d
From: CK Hu
Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.
Signed-off-by: CK Hu
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Changes since v7:
- Add 26 MHz PLL reference input clocks and DSI high-speed output clocks
to the MIPI TX D-PHY
Hi Maxime,
Am Mittwoch, den 16.12.2015, 11:29 +0100 schrieb Maxime Ripard:
> On Mon, Dec 14, 2015 at 10:50:55AM +0100, Philipp Zabel wrote:
> > Am Montag, den 14.12.2015, 10:36 +0100 schrieb Maxime Ripard:
> > > Hi,
> > >
> > > On Fri, Dec 11, 2015 at 0
Hi Daniel,
Am Dienstag, den 15.12.2015, 02:57 +0800 schrieb Daniel Kurtz:
> HI Philipp,
>
> This driver is looking really good.
>
> But, still some things to think about (mostly small) inline below...
Most of my answers below seem to be "ok" or some form thereof, but I
have one or two questions
>
> The 2 controllers are supposed to be 100% independent but on the H3
> Allwinner has done something (not documented) which requires one to
> deassert reset on both before you can talk to either one.
... so thank you for the explanation.
Acked-by: Philipp Zabel
regards
Philipp
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Am Montag, den 14.12.2015, 10:36 +0100 schrieb Maxime Ripard:
> Hi,
>
> On Fri, Dec 11, 2015 at 04:41:58PM +0100, Hans de Goede wrote:
> > diff --git a/include/linux/reset.h b/include/linux/reset.h
> > index c4c097d..1cca8ce 100644
> > --- a/include/linux/reset.h
> > +++ b/include/linux/reset.h
>
Hi Hans,
Am Freitag, den 11.12.2015, 19:21 +0100 schrieb Hans de Goede:
[...]
> >> @@ -119,13 +134,55 @@ EXPORT_SYMBOL_GPL(reset_control_assert);
> >> int reset_control_deassert(struct reset_control *rstc)
> >> {
> >
> > Maybe WARN_ON(rstc->line->refcnt > 1) ?
>
> I assume you mean deasser_cn
Hi Matthias,
thanks for your reply. It would be helpful if you could trim the quoted
text a bit when replying to a small part of a huge patch like this.
Am Freitag, den 11.12.2015, 18:10 +0100 schrieb Matthias Brugger:
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm
Hi Hans,
thanks for moving this forward.
Am Freitag, den 11.12.2015, 16:41 +0100 schrieb Hans de Goede:
> Add reset_control_deassert_shared / reset_control_assert_shared
> functions which are intended for use by drivers for hw blocks which
> (may) share a reset line with another driver / hw block
Am Freitag, den 11.12.2015, 16:41 +0100 schrieb Hans de Goede:
> From: Reinder de Haan
>
> At least the EHCI/OHCI found on the Allwinnner H3 SoC needs multiple
> reset lines, the controller will not initialize while the reset for
> its companion is still asserted, which means we need to de-assert
port both cases.
>
> Signed-off-by: Steffen Trumtrar
Reviewed-by: Philipp Zabel
I have a few suggestions:
[...]
> diff --git a/drivers/rtc/rtc-rx6110.c b/drivers/rtc/rtc-rx6110.c
> new file mode 100644
> index ..aa9d89d5d2de
> --- /dev/null
> +++ b/drive
Am Dienstag, den 08.12.2015, 10:54 +0100 schrieb Steffen Trumtrar:
> Add the binding documentation for the Epson RX6110 RTC.
>
> Acked-by: Rob Herring
> Signed-off-by: Steffen Trumtrar
Reviewed-by: Philipp Zabel
although I'd like a small change to be made below:
> --
Am Dienstag, den 08.12.2015, 10:54 +0100 schrieb Steffen Trumtrar:
> Add the binding documentation for the Epson RX6110 RTC.
>
> Acked-by: Rob Herring
> Signed-off-by: Steffen Trumtrar
Reviewed-by: Philipp Zabel
although I'd like a small change to be made below:
> --
Hi Peter,
Am Dienstag, den 08.12.2015, 09:37 +0800 schrieb Peter Chen:
> Add dt-binding documentation for generic onboard USB HUB.
>
> Signed-off-by: Peter Chen
> ---
> .../bindings/usb/generic-onboard-hub.txt | 28
> ++
> 1 file changed, 28 insertions(+)
> creat
Am Freitag, den 04.12.2015, 14:06 +0100 schrieb Markus Pargmann:
> Add a binding for GPIO initialization.
>
> Signed-off-by: Markus Pargmann
Both patches
Reviewed-by: Philipp Zabel
small nitpick:
> ---
> Documentation/devicetree/bindings/gpio/gpio.txt | 34
>
Hi Simon,
Am Mittwoch, den 02.12.2015, 21:03 + schrieb Simon Arlott:
> Add device tree binding for the BCM6345 soft reset controller.
>
> The BCM6345 contains a soft-reset controller activated by setting
> a bit (that must previously have cleared).
>
> Signed-off-by: Simon Arlott
> ---
> Re
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
Changes since v6:
- Added mtk_dsi_poweron/off
From: Daniel Kurtz
This is useful for drivers that want to implement async commits, but
need to wait on per-plane fences.
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/drm_atomic_helper.c | 7 ---
include/drm/drm_atomic_helper.h | 2 ++
2 files changed
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel
Acked-by: James Liao
---
drivers/clk/mediatek/clk-mt8173.c | 5
From: CK Hu
This patch adds an initial DRM driver for the Mediatek MT8173 DISP
subsystem. It currently supports two fixed output streams from the
OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively.
Signed-off-by: CK Hu
Signed-off-by: YT Shen
Signed-off-by: Philipp Zabel
---
Changes since
Wait on the exclusive fence for the incoming framebuffer, using
"wait_for_fences" from drm_atomic_helper.c, which needs to be exported
first.
Signed-off-by: CK Hu
Signed-off-by: YT Shen
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_drm_cr
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v6:
- Added mtk_dpi_power_on/off refcounting and mtk_ddp_component start/stop
callbacks to keep pixel clock enabled until
From: CK Hu
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
TODO:
- The power-domain property should be added
Add an optional ddc-i2c-bus phandle property that points to
an I2C master controller that handles the connector DDC pins.
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/display/connector/hdmi-connector.txt | 1 +
1 file changed, 1 insertion(+)
diff
From: CK Hu
This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 71
From: Jie Qiu
This patch adds drivers for the HDMI bridge connected to the DPI0
display subsystem function block, for the HDMI DDC block, and for
the HDMI PHY to support HDMI output.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v6:
- Removed mtk_hdmi_audio_data / mtk
These muxes are supposed to select a fitting divider after the PLL
is already set to the correct rate.
Signed-off-by: Philipp Zabel
Acked-by: James Liao
---
drivers/clk/mediatek/clk-mt8173.c | 4 ++--
drivers/clk/mediatek/clk-mtk.h| 7 +--
2 files changed, 7 insertions(+), 4 deletions
setup this HDMI control bit to enable HDMI output in supervisor mode.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 11 +++
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu
From: CK Hu
Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.
Signed-off-by: CK Hu
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Changes since v6:
- Clarify single clock in clocks property
- Improve iommus property description
Qiu (3):
drm/mediatek: Add DPI sub driver
drm/mediatek: Add HDMI support
drm/mediatek: enable hdmi output control bit
Philipp Zabel (5):
dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
clk: mediatek: Add
Add the device tree binding documentation for Mediatek HDMI,
HDMI PHY and HDMI DDC devices.
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
.../bindings/display/mediatek/mediatek,hdmi.txt| 142 +
1 file changed, 142 insertions(+)
create mode 100644
Am Dienstag, den 24.11.2015, 11:38 +0100 schrieb Steffen Trumtrar:
> Add the binding documentation for the Epson RX6110 RTC.
>
> Signed-off-by: Steffen Trumtrar
> ---
> I'm not sure what the current policy for such simple SPI bindings is.
> Are they necessary?
Like for i2c there is trivial-devic
Hi Daniel,
Am Donnerstag, den 19.11.2015, 09:40 +0100 schrieb Daniel Vetter:
> On Wed, Nov 18, 2015 at 06:34:08PM +0100, Philipp Zabel wrote:
> > Hi,
> >
> > another update to the MT8173 DRM support patchset. Since the device tree
> > bindings are now in order, I ha
Hi Tomasz,
Am Dienstag, den 24.11.2015, 14:32 +0900 schrieb Tomasz Figa:
> Hi Philipp, CK,
>
> Please see my comments inline.
>
> On Thu, Nov 19, 2015 at 2:34 AM, Philipp Zabel wrote:
[...]
> > +Required properties (all function blocks):
> > +- compatible
Hi Tomasz,
Am Dienstag, den 24.11.2015, 17:27 +0900 schrieb Tomasz Figa:
> Hi Philipp, CK,
>
> Please see my comments inline.
Thank you for your comments.
> On Thu, Nov 19, 2015 at 2:34 AM, Philipp Zabel wrote:
> [snip]
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_
-names: Must include the following entries:
> + - ipg
As long as there is just a single clock input, shouldn't we just remove
the clock-names property?
Otherwise
Acked-by: Philipp Zabel
regards
Philipp
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Am Montag, den 23.11.2015, 16:07 +0100 schrieb Lucas Stach:
> This largely reworks the GPC driver to better accomodate mutiple
accommodate multiple
> power domains. This allows to extend the driver to support more domains
> (like present on i.MX6SX) easily later on.
>
> Compatibility to the old
Am Freitag, den 20.11.2015, 10:10 +0800 schrieb Chen Feng:
> Add reset driver for hi6220-hikey board,this driver supply deassert
> of IP on hi6220 SoC.
>
> Signed-off-by: Chen Feng
Applied all three, thank you.
regards
Philipp
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From: CK Hu
This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 71
These muxes are supposed to select a fitting divider after the PLL
is already set to the correct rate.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 4 ++--
drivers/clk/mediatek/clk-mtk.h| 7 +--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a
river
drm/mediatek: Add HDMI support
drm/mediatek: enable hdmi output control bit
Philipp Zabel (4):
dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
From: CK Hu
Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.
Signed-off-by: CK Hu
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Changes since v5:
- Updated DISP_MUTEX description
- Fixed DSI and DPI documentation path
---
.../bindings
From: Jie Qiu
This patch adds drivers for the HDMI bridge connected to the DPI0
display subsystem function block, for the HDMI DDC block, and for
the HDMI PHY to support HDMI output.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v5:
- Register and unregister hdmi
setup this HDMI control bit to enable HDMI output in supervisor mode.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 11 +++
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu
From: CK Hu
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
TODO:
- The power-domain property should be added
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
Changes since v5:
- Register and unregister drivers in
Add an optional ddc-i2c-bus phandle property that points to
an I2C master controller that handles the connector DDC pins.
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
Changes since v5:
- Rebased onto v4.4-rc1
---
Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 5 +
include/dt
Add the device tree binding documentation for Mediatek HDMI,
HDMI PHY and HDMI DDC devices.
Signed-off-by: Philipp Zabel
Acked-by: Rob Herring
---
.../bindings/display/mediatek/mediatek,hdmi.txt| 142 +
1 file changed, 142 insertions(+)
create mode 100644
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v5:
- Register and unregister drivers in a loop
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek
From: CK Hu
This patch adds an initial DRM driver for the Mediatek MT8173 DISP
subsystem. It currently supports two fixed output streams from the
OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively.
Signed-off-by: CK Hu
Signed-off-by: YT Shen
Signed-off-by: Philipp Zabel
---
Changes since
27;t want to be copied on all of bindings/display/. So I've
> dropped them.
>
> Reported-by: Thierry Reding
> Cc: Thierry Reding
> Cc: Jianwei Wang
> Cc: Alison Wang
> Cc: Philipp Zabel
Acked-by: Philipp Zabel
regards
Philipp
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Am Mittwoch, den 11.11.2015, 20:53 +0800 schrieb Jitao Shi:
> Add documentation for DT properties supported by
> ps8640 DSI-eDP converter.
>
> Signed-off-by: Jitao Shi
> Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
best regards
Philipp
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Am Mittwoch, den 04.11.2015, 21:28 -0600 schrieb Rob Herring:
> On Wed, Nov 04, 2015 at 12:44:58PM +0100, Philipp Zabel wrote:
> > From: CK Hu
> >
> > Add device tree binding documentation for the display subsystem in
> > Mediatek MT8173 SoCs.
> >
> >
Hi Daniel,
Am Donnerstag, den 05.11.2015, 02:49 +0800 schrieb Daniel Kurtz:
> Hi Philipp,
>
> A bunch of review comments inline.
A bunch indeed. Thank you for the feedback.
> On Wed, Nov 4, 2015 at 7:44 PM, Philipp Zabel wrote:
[...]
> > +struct mtk_drm_crtc {
> >
Hi Jitao,
some things I missed before.
Am Montag, den 02.11.2015, 10:09 +0800 schrieb Jitao Shi:
[...]
> +static int ps8640_regr(struct i2c_client *client, u16 i2c_addr,
> +u8 reg, u8 *value)
> +{
> + int ret;
> +
> + client->addr = i2c_addr;
I think i2c_new_dummy sho
From: CK Hu
This patch adds an initial DRM driver for the Mediatek MT8173 DISP
subsystem. It currently supports two fixed output streams from the
OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively.
Signed-off-by: CK Hu
Signed-off-by: YT Shen
Signed-off-by: Philipp Zabel
---
Changes since
From: Jie Qiu
This patch adds drivers for the HDMI bridge connected to the DPI0
display subsystem function block, for the HDMI DDC block, and for
the HDMI PHY to support HDMI output.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v4:
- Always set mode during bridge
From: CK Hu
This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.
Signed-off-by: CK Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
Changes since v4:
- Drop mediatek,cec DT property
- Add
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/Makefile | 4
atek: Add DSI sub driver
arm64: dts: mt8173: Add display subsystem related nodes
arm64: dts: mt8173: Add HDMI related nodes
Jie Qiu (3):
drm/mediatek: Add DPI sub driver
drm/mediatek: Add HDMI support
drm/mediatek: enable hdmi output control bit
Philipp Zabel (4):
dt-bindings: drm/me
These muxes are supposed to select a fitting divider after the PLL
is already set to the correct rate.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 4 ++--
drivers/clk/mediatek/clk-mtk.h| 7 +--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel
---
drivers/clk/mediatek/clk-mt8173.c | 5 +
include/dt
From: CK Hu
Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.
Signed-off-by: CK Hu
Signed-off-by: Philipp Zabel
---
Changes since v4:
- Move device tree binding documentation to
Documentation/devicetree/bindings/display/mediatek
- Clarified display
Add an optional ddc-i2c-bus phandle property that points to
an I2C master controller that handles the connector DDC pins.
Signed-off-by: Philipp Zabel
---
Documentation/devicetree/bindings/video/hdmi-connector.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
Add the device tree binding documentation for Mediatek HDMI,
HDMI PHY and HDMI DDC devices.
Signed-off-by: Philipp Zabel
---
Changes since v4:
- Remove mediatek,cec and ddc-i2c-bus from hdmi node
- Make output port required
- Add mediatek, prefix to phy node current bias
properties
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_dpi.c | 683
drivers/gpu
setup this HDMI control bit to enable HDMI output in supervisor mode.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 11 +++
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu
Hu
Signed-off-by: Cawa Cheng
Signed-off-by: Jie Qiu
Signed-off-by: Daniel Kurtz
Signed-off-by: Philipp Zabel
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 211 +++
1 file changed, 211 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64
Hi Jitao,
Am Montag, den 02.11.2015, 10:09 +0800 schrieb Jitao Shi:
> Add documentation for DT properties supported by
> ps8640 DSI-eDP converter.
>
> Signed-off-by: Jitao Shi
> ---
> .../devicetree/bindings/display/bridge/ps8640.txt | 43
>
> 1 file changed, 43 inserti
Hi Jitao,
a few comments below.
Am Montag, den 02.11.2015, 11:54 +0800 schrieb jitao shi:
[...]
> > +static int ps8640_check_valid_id(struct ps8640 *ps_bridge)
This could be bool and return true/false.
> > +{
> > + struct i2c_client *client = ps_bridge->client;
> > + u8 rev_id_low, rev_id_h
Hi Jitao,
Am Montag, den 02.11.2015, 11:53 +0800 schrieb jitao shi:
[...]
> > +Example:
> > + edp-bridge@18 {
> > + compatible = "parade,ps8640";
> > + reg = <0x18>;
> > + sleep-gpios = <&pio 116 GPIO_ACTIVE_HIGH>;
> > + reset-gpios = <&pio 115 GPIO_ACTIVE
Hi Rob,
thank you for the comments.
Am Freitag, den 23.10.2015, 07:29 -0500 schrieb Rob Herring:
[...]
> > +Mediatek HDMI Encoder
> > +=
> > +
> > +The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
> > +its parallel input.
>
> How do you know whether it
Hi Daniel,
Am Montag, den 19.10.2015, 10:56 +0200 schrieb Daniel Vetter:
> On Fri, Oct 16, 2015 at 10:12:04PM +0200, Philipp Zabel wrote:
> > From: CK Hu
> >
> > This patch adds an initial DRM driver for the Mediatek MT8173 DISP
> > subsystem. It currently supports tw
Hi Daniel,
Am Montag, den 19.10.2015, 10:56 +0200 schrieb Daniel Vetter:
> On Fri, Oct 16, 2015 at 10:12:04PM +0200, Philipp Zabel wrote:
> > From: CK Hu
> >
> > This patch adds an initial DRM driver for the Mediatek MT8173 DISP
> > subsystem. It currently supports tw
Hi Jens,
Am Dienstag, den 27.10.2015, 17:50 +0100 schrieb Jens Kuske:
[...]
> --- a/drivers/reset/reset-sunxi.c
> +++ b/drivers/reset/reset-sunxi.c
> @@ -75,7 +75,9 @@ static struct reset_control_ops sunxi_reset_ops = {
> .deassert = sunxi_reset_deassert,
> };
>
> -static int sunxi_
From: CK Hu
This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.
Signed-off-by: Jitao Shi
Signed-off-by: Philipp Zabel
---
Changes since v3:
- Simplified bind function
- Removed
From: Jie Qiu
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
- Removed unused mtk_dpi_config_bit_swap function
- Enable/disable pixel clock instead of its ancestor PLL
- Instead of manually setting the
From: Daniel Kurtz
This patch adds drivers for the HDMI bridge connected to the DPI0
display subsystem function block, for the HDMI DDC block, and for
the HDMI PHY to support HDMI output.
Signed-off-by: Jie Qiu
Signed-off-by: Philipp Zabel
---
Changes since v3:
- Split CEC register access
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