gt; Without such a fix the PCI device enumeration during kernel boot
> is not reliable, and reading configuration space for particular
> PCI device on the bus returns zero aka no device.
>
> Signed-off-by: Stanimir Varbanov
Acked-by: Pratyush Anand
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On Thu, Dec 17, 2015 at 9:15 PM, Stanimir Varbanov
wrote:
>
> On 12/11/2015 06:05 AM, Pratyush Anand wrote:
> > On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux
> > wrote:
> >
> > [...]
> >
> >>>>>
On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux
wrote:
[...]
>> > > dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>> > > + /*
>> > > + * ensure that the ATU enable has been happaned before accessing
>> > > + * pci configuration/io spaces through dw_pcie_cfg_[
On Tue, Dec 8, 2015 at 2:31 PM, Stanimir Varbanov
wrote:
>
> On 12/03/2015 03:35 PM, Stanimir Varbanov wrote:
> > Add 'write memory' barrier after enable region in PCIE_ATU_CR2
> > register. The barrier is needed to ensure that the region enable
> > request has been reached it's destination at tim
Hi Fu Wei,
On 25/08/2015:01:01:15 AM, fu@linaro.org wrote:
> From: Fu Wei
>
> This patchset:
> (1)Introduce Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt
> for FDT info of SBSA Generic Watchdog, and give two examples of
> adding SBSA Generic Watchdog device node into t
se. Since I moved from ST, I do not have any
test board having designware PCIe controller :(, and also I do
designware work only in my hobby time, so it took time to understand
few modifications. Anyway, all modifications looks fine to me. So,
Acked-by: Pratyush Anand
PS: Does someone know about
On 15/09/2015:04:43:32 PM, Dave Young wrote:
> On 08/25/15 at 01:01am, fu@linaro.org wrote:
> > From: Fu Wei
> >
> > This can be a example of adding SBSA Generic Watchdog device node
> > into some dts files for the Soc which contains SBSA Generic Watchdog.
> >
> > Acked-by: Arnd Bergmann
>
On 10/09/2015:06:45:17 PM, Jon Masters wrote:
> On 06/03/2015 02:53 PM, Timur Tabi wrote:
> > On 06/03/2015 01:25 PM, Guenter Roeck wrote:
> >> In general the idea here would be to use a crashdump kernel, which,
> >> when loaded, would reset the watchdog before it fires. This kernel
> >> would then
*/
> + msleep(100);
IIRC, specification says to wait after link training completes. So
shouldn't it be after st_pcie_enable_ltssm. Moreover, I wonder why
others do not need it.
Reviewed-by: Pratyush Anand
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ction pcibios_align_resource(); in fact this will
>> cast "dev->sysdata" to "struct pci_sys_data*", whereas designware had passed
>> a
>> "struct pcie_port*" pointer.
>>
>> This patch solves the issue by removing "align_resourc
gt;> driver and is needed to allow the rework of designware to use
>> the new DT parsing API.
>>
>> Signed-off-by: Gabriele Paoloni
>> Signed-off-by: Zhou Wang
Looks fine to me
Acked-by: Pratyush Anand
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Hi Zhou Wang,
Thanks for unifying arm and arm64 code.
On Wed, Jun 3, 2015 at 2:05 PM, Zhou Wang wrote:
>
> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
> move related operations to dw_pc
On Monday 22 December 2014 02:00 PM, Arnd Bergmann wrote:
On Monday 22 December 2014 12:09:04 Pratyush Anand wrote:
Config space is need to be allocated using reg property. This patch
removes possibility of config space allocation through ranges property.
To: Mohit Kumar
To: Jingo Han
To
Config space is need to be allocated using reg property. This patch
removes possibility of config space allocation through ranges property.
To: Mohit Kumar
To: Jingo Han
To: Lucas Stach
To: Shawn Guo
Cc: linux-...@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Pratyush Anand
On Wednesday 17 December 2014 04:04 PM, Gabriel FERNANDEZ wrote:
sti pcie is built around a Synopsis Designware PCIe IP.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
---
drivers/pci/host/Kconfig | 5 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pci-st.c | 7
On Wednesday 17 December 2014 04:04 PM, Gabriel FERNANDEZ wrote:
sti pcie is built around a Synopsis Designware PCIe IP.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
---
Documentation/devicetree/bindings/pci/st-pcie.txt | 53 +++
1 file changed, 53 i
On Sat, Jul 5, 2014 at 11:02 PM, Bjorn Helgaas wrote:
> On Wed, Jun 25, 2014 at 11:26:44PM +0530, Kishon Vijay Abraham I wrote:
>> [1] is split into separate series in order for individual subsystem
>> Maintainers to pick up the patches. This series handles the PCIe
>> support for DRA7.
>>
>> Reba
Hi Kishon,
On Thu, Jun 26, 2014 at 02:10:02PM +0800, Kishon Vijay Abraham I wrote:
> Hi Pratyush,
>
> On Thursday 26 June 2014 11:07 AM, Pratyush Anand wrote:
> > Hi Kishon,
> >
> > Few things, if you can help me to understand:
> >
> > On Wed, Jun 25, 2
Hi Kishon,
Few things, if you can help me to understand:
On Wed, Jun 25, 2014 at 11:26 PM, Kishon Vijay Abraham I wrote:
> In DRA7, the cpu sees 32bit address, but the pcie controller can see only
> 28bit
> address. So whenever the cpu issues a read/write request, the 4 most
> significant bits
On Sat, Jun 21, 2014 at 03:05:30AM +0800, Arnd Bergmann wrote:
> On Friday 20 June 2014 13:11:37 Santosh Shilimkar wrote:
> > >
> > Arnd suggestion was to have the version 3.65 code in generic place since
> > its IP specific and just in case some other vendor using the same version
> > can levera
On Sat, Jun 21, 2014 at 05:17:07AM +0800, Murali Karicheri wrote:
>
> Sorry, my previous response was in html and not sure it has made to the
> list. I did
> get an error as well. So resending my response.
>
> On 6/18/2014 6:14 AM, Mohit KUMAR DCG wrote:
> > Hello Murali,
> >
>
[...]
> *pos =
On Sat, Jun 21, 2014 at 02:47:27AM +0800, Murali Karicheri wrote:
> On 6/18/2014 3:05 AM, Pratyush Anand wrote:
> > Hi Murali,
> >
> > On Wed, Jun 11, 2014 at 02:51:21AM +0800, Murali Karicheri wrote:
[...]
> Pratyush,
>
> Thanks for the comments.
>
>
t initialization code.
>
> Signed-off-by: Murali Karicheri
>
> CC: Santosh Shilimkar
> CC: Russell King
> CC: Grant Likely
> CC: Rob Herring
> CC: Mohit Kumar
> CC: Jingoo Han
> CC: Bjorn Helgaas
> CC: Pratyush Anand
> CC: Richard Zhu
> CC: Kishon V
-off-by: Murali Karicheri
>
> CC: Santosh Shilimkar
> CC: Russell King
> CC: Grant Likely
> CC: Rob Herring
> CC: Mohit Kumar
> CC: Jingoo Han
> CC: Bjorn Helgaas
> CC: Pratyush Anand
> CC: Richard Zhu
> CC: Kishon Vijay Abraham I
> CC: Marek Vasut
> C
dw
> > driver maintainer. So dropped these from v2.
> > - Incorporated comment to move the common/reset PCIe code to the
> > seperate driver
> > - PCIe and SATA share common PHY configuration registers, so move SATA
> > platform code to the system config driver Fourth
Hi Arnd,
Do you see any more improvement in this series.
Else we will send V5 (probably the final one) with modifications for
Kishon's comment.
Regards
Pratyush
On Thu, Feb 6, 2014 at 10:14 AM, Pratyush Anand wrote:
> First three patches are improvement and fixes for SPEAr13xx
On Thu, Feb 06, 2014 at 04:01:25PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> > On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 Fe
On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ahci driver needs some platform specific functions which are called at
> > init, exit, suspend and resume conditions. Till now
On Thu, Feb 06, 2014 at 02:23:20PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> > Hi Kishon,
> >
> > On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >&g
Hi Kishon,
On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> > skeleton support for the same.
> >
ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
skeleton support for the same.
Currently phy ops are returning -EINVAL. They can be elaborated
depending on the SOC being supported in future.
Signed-off-by: Pratyush Anand
Tested-by: Mohit Kumar
Cc: Arnd Bergmann
Cc
move all these SATA platform code to phy-miphy40lp driver.
Signed-off-by: Pratyush Anand
Tested-by: Mohit Kumar
Cc: Viresh Kumar
Cc: Tejun Heo
Cc: Arnd Bergmann
Cc: Kishon Vijay Abraham I
Cc: spear-de...@list.st.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc
maintainer
Pratyush Anand (6):
clk: SPEAr13xx: Fix pcie clock name
SPEAr13xx: Fix static mapping table
phy: st-miphy-40lp: Add skeleton driver
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
pcie: SPEAr13xx: Add
On Thu, Jan 30, 2014 at 09:21:00PM +0800, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Mohit Kumar wrote:
> >
> > diff --git a/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > b/Documentation/devicetree/bindings/phy/spear13xx-miphy.txt
> > new file mode 100644
> > index 00
Hi Arnd,
On Sat, Jan 25, 2014 at 2:23 AM, Arnd Bergmann wrote:
>
> On Friday 24 January 2014, Pratyush Anand wrote:
> > On Thu, Jan 23, 2014 at 08:22:54PM +0800, Arnd Bergmann wrote:
> > > On Thursday 23 January 2014, Mohit Kumar wrote:
> > >
> > > I assu
Hi Arnd,
Thanks for your valuable comments.
On Thu, Jan 23, 2014 at 08:22:54PM +0800, Arnd Bergmann wrote:
> On Thursday 23 January 2014, Mohit Kumar wrote:
> > diff --git a/arch/arm/boot/dts/spear13xx.dtsi
> > b/arch/arm/boot/dts/spear13xx.dtsi
> > index 3518803..2b4e58e 100644
> > --- a/arch/a
On Thu, Jan 23, 2014 at 07:36:44PM +0800, Tejun Heo wrote:
> On Thu, Jan 23, 2014 at 04:02:43PM +0530, Mohit Kumar wrote:
> > diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
> > index 73a2500..76d35e8 100644
> > --- a/include/linux/ahci_platform.h
> > +++ b/include/linux/
On Sun, Dec 15, 2013 at 04:18:23AM +0800, Bjorn Helgaas wrote:
> [+cc devicetree, linux-arm-kernel]
>
> On Sat, Dec 14, 2013 at 1:05 PM, shiv prakash Agarwal
> wrote:
> > On Sun, Dec 15, 2013 at 12:29 AM, Bjorn Helgaas wrote:
> >> On Sat, Dec 14, 2013 at 11:32 AM, shiv prakash Agarwal
> >> wrot
On Wed, Oct 09, 2013 at 06:49:15PM +0800, Jingoo Han wrote:
> On Wednesday, October 09, 2013 7:27 PM, Kishon Vijay Abraham I wrote:
> > On Wednesday 09 October 2013 03:35 PM, Jingoo Han wrote:
> > > On Wednesday, October 09, 2013 6:48 PM, Kishon Vijay Abraham I wrote:
> > >> On Wednesday 09 October
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