On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote:
Fix bypass clock source for a few DPLLs.
On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
to a mux and the output from mux is routed to the bypass clkout.
Add a mux-clock as bypass clock with CLKINP and CLKINPULOW
://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
branch: master
On:
CPU : OMAP5432 ES2.0
Board: OMAP5432 uEVM
and
CPU : DRA752 ES1.0
Board: DRA7xx
Ravikumar Kattekola (2):
ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others
ARM: OMAP5: dts: Fix the bypass clock
another mux clock as parent in bypass mode.
This design is common to most of the PLLs and the rest have only one bypass
clock. Below is a list of the DPLLs that need this fix:
DPLL_IVA,
DPLL_PER,
DPLL_USB and DPLL_CORE
Signed-off-by: Ravikumar Kattekola r...@ti.com
---
arch
in bypass mode.
This design is common to most of the PLLs and the rest have only one bypass
clock. Below is a list of the DPLLs that need this fix:
DPLL_IVA, DPLL_DDR,
DPLL_DSP, DPLL_EVE,
DPLL_GMAC, DPLL_PER,
DPLL_USB and DPLL_CORE
Signed-off-by: Ravikumar Kattekola r...@ti.com
---
arch/arm/boot
with the
latest Data Manual
Regards,
RK
Ravikumar Kattekola (2):
ARM: dts: dra7-evm: Fix typo in SMPS6 (VDD_GPU) max voltage
ARM: dts: dra7-evm: Update SMPS7 (VDD_CORE) max voltage to match DM
arch/arm/boot/dts/dra7-evm.dts |4 ++--
arch/arm/boot/dts/dra72-evm.dts |2 +-
2 files changed
)
Signed-off-by: Ravikumar Kattekola r...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 736092b..b6b9286 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm
, SPRS857M - Dec 2012, Revised Oct 2014.
DRA72 Data Manual, SPRS906G - Dec 2012, revised Oct 2014.
Signed-off-by: Ravikumar Kattekola r...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts |2 +-
arch/arm/boot/dts/dra72-evm.dts |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm
