Enable power management. This patch enables the clocks
before transfer and disables after the transfer.
Signed-off-by: Shubhrajyoti Datta
---
drivers/i2c/busses/i2c-xiic.c | 86 +---
1 files changed, 79 insertions(+), 7 deletions(-)
diff --git a/drivers
Add clock description for i2c-xiic
Signed-off-by: Shubhrajyoti Datta
---
Documentation/devicetree/bindings/i2c/i2c-xiic.txt |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-xiic.txt
b/Documentation/devicetree/bindings/i2c/i2c
> +static int alt_modular_adc_probe(struct platform_device *pdev)
> +{
> + struct altera_adc *adc;
> + struct device_node *np = pdev->dev.of_node;
> + struct iio_dev *indio_dev;
> + struct resource *mem;
> + int ret;
> +
> + if (!np)
> + return -ENO
hi ,
On Tue, Jul 21, 2015 at 6:11 PM, Vaibhav Hiremath
wrote:
> From: Yi Zhang
>
> Enable i2c module/unit before transmission and disable when it
> finishes.
>
> why?
> It's because the i2c bus may be disturbed if the slave device,
> typically a touch, powers on.
Why should that be an issue?
Is
On Wed, Jul 29, 2015 at 7:49 PM, Michal Simek wrote:
> Add i2c eeprom memories on i2c bus.
>
Thanks for the patch.
Feel free to add
Reviewed-by: Shubhrajyoti Datta
> Signed-off-by: Michal Simek
> ---
>
> Changes in v2:
> - Change eeprom max freq from 100k to 400k
>
>
Hi,
On Mon, Jul 27, 2015 at 3:18 PM, Michal Simek wrote:
> Add i2c eeprom memories on i2c bus.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep1
On Mon, Jun 15, 2015 at 8:06 PM, Punnaiah Choudary Kalluri
wrote:
> Added the basic driver for zynqmp dma engine used in Zynq
> UltraScale+ MPSoC. The initial release of this driver supports
> only memory to memory transfers.
>
> Signed-off-by: Punnaiah Choudary Kalluri
> ---
> +/**
> + * zynqm
hi,
Some minor comments.
On Fri, Jun 5, 2015 at 6:37 PM, Ranjit Waghmode
wrote:
> This patch adds support for GQSPI controller driver used by
> Zynq Ultrascale+ MPSoC
>
> Signed-off-by: Ranjit Waghmode
> ---
> Here is the v2 series.
> + */
> +static void zynqmp_qspi_chipselect(struct spi_devi
Hi Moritz,
Overall looks good some nitpicks below.
On Fri, May 22, 2015 at 5:07 AM, Moritz Fischer
wrote:
> The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
> interprocessor communication via AXI4 memory mapped / AXI4 stream
> interfaces.
>
> It is single channel per core and allow
