On 08/24, Gabriel Fernandez wrote:
> Change A9 PLL rate, as per requirement from the cpufreq framework,
> for DVFS. For rate change, the A9 clock needs to be temporarily sourced
> from PLL external to A9 and then sourced back to A9-PLL
>
> Signed-off-by: Pankaj Dev
> Signed-off-by: Gabriel Fernan
On 08/24, Gabriel Fernandez wrote:
> Add support for new PLL-type for stih418 A9-PLL.
>
> Signed-off-by: Gabriel Fernandez
> ---
I assume this will go through arm-soc?
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On 08/24, Gabriel Fernandez wrote:
> The patch adds support for enable/disable of the Clockgen PLLs.
> clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
>
> Signed-off-by: Pankaj Dev
> Signed-off-by: Gabriel Fernandez
> ---
Applied to clk-next
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Qualcomm Innovation
On 10/02, Mike Looijmans wrote:
> This patch adds the driver and devicetree documentation for the
> Silicon Labs SI514 clock generator chip. This is an I2C controlled
> oscillator capable of generating clock signals ranging from 100kHz
> to 250MHz.
>
> Signed-off-by: Mike Looijmans
> ---
Applied
On 10/02, Mike Looijmans wrote:
> On 02-10-15 01:34, Stephen Boyd wrote:
> >>+ - clock-output-names: From common clock bindings. Recommended to be
> >>"si514".
> >>+ - clock-frequency: Output frequency to generate. This defines the output
> >>+
On 09/10, Eric Anholt wrote:
> diff --git a/drivers/clk/bcm/clk-bcm2835-aux.c
> b/drivers/clk/bcm/clk-bcm2835-aux.c
> new file mode 100644
> index 000..1efa6fb
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-bcm2835-aux.c
> @@ -0,0 +1,80 @@
> +/*
> + * Copyright (C) 2015 Broadcom
> + *
> + * This
On 09/28, Eric Anholt wrote:
> Previously we've only supported a few fixed clocks based on
> assumptions about how the firmware sets up the clocks, but this
> binding will let us control the actual (audio power domain) clock
> manager.
>
> Signed-off-by: Eric Anholt
> Acked-by: Stephen Warren
>
On 09/28, Eric Anholt wrote:
> clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
> drivers are going in there so let's follow them.
>
> Signed-off-by: Eric Anholt
> Acked-by: Stephen Warren
> ---
Applied to clk-bcm2385 and merged into clk-next.
--
Qualcomm Innovation Center,
On 09/28, Eric Anholt wrote:
> +
> +static const char *bcm2835_clock_per_parents[] = {
> +static const char *bcm2835_clock_vpu_parents[] = {
> +static const char *bcm2835_clock_osc_parents[] = {
Can these parent arrays be const char * const ?
> + "gnd",
> + "xosc",
> + "testdebug0",
>
On 09/17, Mike Looijmans wrote:
> This patch adds the driver and devicetree documentation for the
> Silicon Labs SI514 clock generator chip. This is an I2C controlled
> oscilator capable of generating clock signals ranging from 100kHz
s/oscilator/oscillator/
> to 250MHz.
>
> Signed-off-by: Mike
On 09/22, Jisheng Zhang wrote:
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +The berlin4ct clock subsystem generates and supplies clock to various
> +controllers within the berlin4ct SoC. The berlin4ct contains 3 clock
On 09/22, Jisheng Zhang wrote:
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "clk.h"
> +
> +#define CLK_SOURCE_MAX 5
> +
> +static struct clk_onecell_data gateclk_data;
> +static struct clk_onecell_data clk_data;
> +
> +static DEFINE_SPIN
On 09/22, Jisheng Zhang wrote:
> +
> +static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};
> +
> +static unsigned long berlin_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 val, divider;
> + struct berlin_clk *clk = to_berlin_c
On 09/22, Jisheng Zhang wrote:
> diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
> new file mode 100644
> index 000..9aad0b6
> --- /dev/null
> +++ b/drivers/clk/berlin/pll.c
> @@ -0,0 +1,119 @@
> +
> +#define to_berlin_pll(hw) container_of(hw, struct berlin_pll, hw)
> +
>
on work by others on codeaurora.org[1].
[1]
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/regulator/cpr-regulator.c?h=msm-3.10
Cc:
Cc: David Collins
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/power/avs/qcom,cpr.txt | 125 ++
drive
On 09/12, Ivan T. Ivanov wrote:
> Make function naming consistent across this driver.
> No functional changes.
>
> Signed-off-by: Ivan T. Ivanov
> ---
Reviewed-by: Stephen Boyd
It would be nice to rename msm_irq to something like msm_uart_irq
too.
--
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On 09/12, Ivan T. Ivanov wrote:
> Stale Event Enable command should be 5 not 8, fix this.
>
> Signed-off-by: Ivan T. Ivanov
> ---
> drivers/tty/serial/msm_serial.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_s
On 09/17/2015 06:45 AM, Lee Jones wrote:
> Signed-off-by: Lee Jones
> ---
> Documentation/devicetree/bindings/rng/st,rng.txt | 15 +++
> 1 file changed, 15 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rng/st,rng.txt
>
> diff --git a/Documentation/devicetree/bi
o revise the above, I should have checked more closely
> before I sent my previous email. I now see that I have an SoC patch
> that depends on this one. So if possible I'd like to take this one
> through my tree with an Ack or two.
>
Sure.
Acked-by: Stephen Boyd
--
Qualcomm Inn
On 09/16, Gabriel Fernandez wrote:
> Use a generic name for this kind of PLL
>
> Correction in dts files are already done here:
> commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into
> st_pll3200c32_cx_x")
>
> Signed-off-by: Gabriel Fernandez
> ---
Applied to clk-fixes
--
Q
On 09/17, Maxime Coquelin wrote:
>
>
> On 09/17/2015 12:30 AM, Stephen Boyd wrote:
> >On 09/16, Gabriel Fernandez wrote:
> >>This patch set fixes a kernel crash :
> >[..]
> >>This kernel crash is due to a broken compatibility with this commit:
> &g
On 09/16, Gabriel Fernandez wrote:
> This patch set fixes a kernel crash :
[..]
>
> This kernel crash is due to a broken compatibility with this commit:
> commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into
> st_pll3200c32_cx_x")
It isn't clear who's supposed to apply this bec
On 09/09, Rob Herring wrote:
> On 09/09/2015 11:36 AM, Lee Jones wrote:
> >>> Or have I got the wrong end of the stick?
> >>>
> >>> NB: Note the suggested new property names.
> >>
> >> Yeah, all looks fine to me.
> >
> > I think these names are better:
> >
> > opp-supply-range-name => opp-micro
On 09/09, Gilad Avidov wrote:
> On Fri, 4 Sep 2015 17:50:11 -0700
> Stephen Boyd wrote:
>
> > On 09/04, Gilad Avidov wrote:
> > > On Thu, 3 Sep 2015 17:16:30 -0700
> > > Stephen Boyd wrote:
> > >
> > > > On 09/03, Gilad Avidov wrote:
>
On 08/18, Mathieu Olivari wrote:
> On recent bootloaders, the bootloader patches the DT blob with memory
> information. However, with old bootloader, this operation doesn't
> happen, which leads the board to freeze in the early init code.
>
> This patch adds the memory node to the AP148 dts explic
On 09/07, Lee Jones wrote:
> On Sun, 06 Sep 2015, Eric Anholt wrote:
>
> > clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
> > drivers are going in there so let's follow them.
> >
> > Signed-off-by: Eric Anholt
> > ---
> > drivers/clk/Makefile | 1 -
> > drivers/clk
On 09/04, Gilad Avidov wrote:
> On Thu, 3 Sep 2015 17:16:30 -0700
> Stephen Boyd wrote:
>
> > On 09/03, Gilad Avidov wrote:
> > > + supported by HW. Default (minimum
> > > supported) is 128. +
> > > +Example V1 PMIC-Arbiter:
> &g
On 09/03, Gilad Avidov wrote:
> + supported by HW. Default (minimum supported) is 128.
> +
> +Example V1 PMIC-Arbiter:
>
> spmi {
> compatible = "qcom,spmi-pmic-arb";
> @@ -62,4 +66,32 @@ Example:
>
> interrupt-controller;
> #
On 07/20, Andy Gross wrote:
> This patch creates a platform driver for the SCM so that we can adequately
> manage resources. This removes clients having to carry the necessary
> clocks to use the SCM resources.
>
> Signed-off-by: Andy Gross
> ---
It would be nice if we could use this platform d
On 08/18/2015 06:10 AM, Srinivas Kandagatla wrote:
This patch add alias node with serial0.
Signed-off-by: Srinivas Kandagatla
---
I have a whole set of patches to add all the serial aliases and
stdout-path properties [1]. Please drop this patch from your series.
[1]
http://lkml.kernel.org
On 08/18/2015 06:10 AM, Srinivas Kandagatla wrote:
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index b1f9ddb..08daafe 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -221,6 +221,1
On 08/18/2015 06:06 AM, Srinivas Kandagatla wrote:
@@ -10,6 +11,20 @@
serial1 = &gsbi6_serial;
};
+ pwrseq {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
Why do we need any of these three properties?
+
On 08/25, Varadarajan Narayanan wrote:
> On Mon, Aug 24, 2015 at 03:49:28PM -0700, Stephen Boyd wrote:
> > On 08/24, Varadarajan Narayanan wrote:
>
> > > + compatible = "qcom,ipq40xx-r3pc", "qcom,ipq40xx";
> > > +
> > > + memory {
Mathieu Olivari
> ---
Reviewed-by: Stephen Boyd
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> ---
Reviewed-by: Stephen Boyd
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On 08/18, Mathieu Olivari wrote:
> Add one new node to the ipq806x.dtsi file to declare & register the
> hardware spinlock devices. This mechanism is required to be used by
> other drivers such as SMEM.
>
> Signed-off-by: Mathieu Olivari
> ---
Reviewed-by: Stephen Boyd
-
On 08/19, Mathieu Olivari wrote:
> diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> index 6886d09..d73df24 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
> @@ -19,8 +19,9 @@
>
On 08/24, Varadarajan Narayanan wrote:
> Add initial dts files and SoC support for IPQ40XX
>
So far we haven't added any Xs in the model names for our SoC
support. Even for IPQ806X, we have it as IPQ8064 as the config
name with IPQ806x in the help text because there's IPQ8062 out
there. So I gues
On 08/13/2015 02:33 PM, Mathieu Olivari wrote:
diff --git a/drivers/mtd/qcom_smem_part.c b/drivers/mtd/qcom_smem_part.c
new file mode 100644
index 000..6cbf610
--- /dev/null
+++ b/drivers/mtd/qcom_smem_part.c
+#define SMEM_PARTS_MAX 32
+
+struct smem_partition {
+ char
On 08/13/2015 02:33 PM, Mathieu Olivari wrote:
@@ -79,6 +79,15 @@
#hwlock-cells = <1>;
};
+
+ smem {
+ compatible = "qcom,smem";
+
+ memory-region = <&smem>;
+ reg = <0x4100 0x4000>;
Doe
On 08/13/2015 02:33 PM, Mathieu Olivari wrote:
Add one new node to the ipq806x.dtsi file to declare & register the
hardware spinlock devices. This mechanism is required to be used by
other drivers such as SMEM.
Signed-off-by: Mathieu Olivari
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 12 ++
On 07/30, Linus Walleij wrote:
> These Ux500 clocks have been around for years and were never
> properly documented. Add the proper binding documentation.
>
> Cc: Ulf Hansson
> Signed-off-by: Linus Walleij
> ---
Applied to clk-next
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On 08/12/2015 07:47 AM, Sricharan R wrote:
@@ -702,6 +703,44 @@ static void print_ctx_regs(void __iomem *base, int ctx)
GET_PRRR(base, ctx), GET_NMRR(base, ctx));
}
+static void insert_iommu_master(struct device *dev,
+ struct msm_iommu_dev *iomm
On 08/04, Leo Yan wrote:
> On Hi6220, there have some clocks which can use mailbox channel to send
> messages to power controller to change frequency; this includes CPU, GPU
> and DDR clocks.
>
> For dynamic frequency scaling, firstly need write the frequency value to
> SRAM region, and then send
On 08/04, Leo Yan wrote:
> Document "hisilicon,hi6220-sramctrl" for SRAM controller.
>
> Signed-off-by: Leo Yan
> ---
Applied to clk-next
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On 08/04, Leo Yan wrote:
> Document the new compatible for stub clock driver which is used for CPU
> and DDR's dynamic frequency scaling.
>
> Signed-off-by: Leo Yan
> ---
Applied to clk-next
--
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On 08/04, Leo Yan wrote:
> This series adds support for hisilicon stub clock driver. On hi6220,
> the bootloader needs load the firmware image and set info for OPPs;
> after run into kernel, the stub clock driver is used to communicate
> w/t firmware for cpu dynamic frequency scaling.
>
> In patch
On 07/28/2015 05:54 AM, Srinivas Kandagatla wrote:
@@ -618,5 +633,77 @@
compatible = "qcom,tcsr-apq8064", "syscon";
reg = <0x1a40 0x100>;
};
+
+ hdmi: qcom,hdmi-tx@4a0 {
+ compatible = "qco
On 08/03, Leo Yan wrote:
> *of_iomap()* will check the device node pointer, and if the pointer is
> NULL it will return error code. So refine clock's init flow by checking
> the device node with this simple way; and polish a little for the print
> out message.
>
> Signed-off-by: Leo Yan
> ---
Ap
On 08/03, Leo Yan wrote:
> diff --git a/drivers/clk/hisilicon/clk-hi6220-stub.c
> b/drivers/clk/hisilicon/clk-hi6220-stub.c
> new file mode 100644
> index 000..0931666
> --- /dev/null
> +++ b/drivers/clk/hisilicon/clk-hi6220-stub.c
> @@ -0,0 +1,279 @@
> +/*
> + * Hi6220 stub clock driver
> + *
On 08/03, Archit Taneja wrote:
> @@ -93,5 +115,19 @@
> sata@2900 {
> status = "ok";
> };
> +
> + nand@1ac0 {
> + status = "ok";
> +
> + pinctrl-0 = <&nand_pins>;
> + pin
On 07/30, Rob Herring wrote:
> On Thu, Jul 30, 2015 at 3:46 AM, Lee Jones wrote:
> >
> > There is nothing stopping us from representing the data in this way.
> > On the plus side, it would mean that we wouldn't need any vendor
> > specific properties. However, far outweighing the positives are th
/88pm800.txt | 28 +++
1 file changed, 28 insertions(+)
+Cc Stephen Boyd (clocks)
We had a discussion whether clock bindings should be put in MFD
bindings documentation or into separate file in bindings/clock but
either way is fine for me:
No patch? :)
I think Rob has been
On 07/30/2015 11:04 AM, Heiko Stübner wrote:
Am Donnerstag, 30. Juli 2015, 10:36:43 schrieb Stephen Boyd:
Is it being used in DT right now and causing regressions on
v4.2-rcX? Sorry, I'm trying to understand why this patch matters
for the 4.2 release.
it's not been used in
On 07/29, James Liao wrote:
> Hi Stephen,
>
> Could you help to apply this patch into 4.2?
>
>
> Best regards,
>
> James
>
> On Wed, 2015-07-29 at 09:05 +0200, Heiko Stübner wrote:
> > Am Mittwoch, 29. Juli 2015, 14:52:25 schrieb James Liao:
> > > The dpi_ck clock can be removed because it not
On 07/29, James Liao wrote:
> From: Sascha Hauer
>
> On the MT8173 the clocks are provided by different units. To enable
> the critical clocks we must be sure that all parent clocks are already
> registered, otherwise the parents of the critical clocks end up being
> unused and get disabled later
On 07/28/2015 05:53 AM, Srinivas Kandagatla wrote:
+
+ sdcc4_pwrseq:pwrseq {
Missing space here between label and node name.
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>;
+ };
+
On 07/28/2015 05:54 AM, Srinivas Kandagatla wrote:
+
+ panel_3p3v: panel_3p3v {
+ compatible = "regulator-fixed";
+ pinctrl-0 = <&disp_en_gpios>;
+ pinctrl-names = "default";
+ regulator-min-micr
On 07/29, Lee Jones wrote:
> On Tue, 28 Jul 2015, Stephen Boyd wrote:
>
> > On 07/28, Viresh Kumar wrote:
> > > Cc'ing few people (whom I cc'd last time as well :)).
> > >
> > > On 27-07-15, 16:20, Lee Jones wrote:
> > > > +
On 07/28, Viresh Kumar wrote:
> Cc'ing few people (whom I cc'd last time as well :)).
>
> On 27-07-15, 16:20, Lee Jones wrote:
> > These OPPs are used in ST's CPUFreq implementation.
> >
> > Signed-off-by: Lee Jones
> > ---
> >
> > Changelog:
> > - None, new patch
> >
> > Documentation/devic
On 07/21/2015 03:34 AM, Archit Taneja wrote:
> +
> +nand@0x1ac0 {
s/0x//
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On 07/22/2015 01:16 AM, Vaibhav Hiremath wrote:
On Wednesday 22 July 2015 12:16 PM, Krzysztof Kozlowski wrote:
I am really busy now so I am not following closely other discussions. I
assume you are referring to clk-s2mps11.c. The of_node_put() matches
of_get_child_by_name() when parsing DT.
On 07/21/2015 12:36 PM, Vaibhav Hiremath wrote:
On Wednesday 22 July 2015 12:40 AM, Stephen Boyd wrote:
On 07/21/2015 04:07 AM, Vaibhav Hiremath wrote:
+
+pm800_clks = devm_kzalloc(&pdev->dev,
+sizeof(*pm800_clks) * PM800_CLKS_NUM,
+GFP
On 07/21/2015 04:07 AM, Vaibhav Hiremath wrote:
diff --git a/drivers/clk/clk-88pm800.c b/drivers/clk/clk-88pm800.c
new file mode 100644
index 000..cf1c162
--- /dev/null
+++ b/drivers/clk/clk-88pm800.c
@@ -0,0 +1,345 @@
+/*
+ * clk-88pm800.c - Clock driver for 88PM800 family of devices
+ *
+ *
On 07/17/2015 09:53 AM, Sricharan R wrote:
From: Mitchel Humpherys
This adds the support to turn on the regulators required
for SMMUs. It is turned on during the SMMU probe and remains
'on' till the device exists.
The device always exists. Until the driver is removed perhaps?
Signed-off-by
On 07/21/2015 02:41 AM, Srinivas Kandagatla wrote:
Thanks Stephen for review,
On 20/07/15 22:11, Stephen Boyd wrote:
On 07/20/2015 07:43 AM, Srinivas Kandagatla wrote:
diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
new file mode 100644
index 000..bde5528
--- /dev/null
+++ b
,
thermal sensors would read out this data for configuring the driver.
Signed-off-by: Srinivas Kandagatla
One comment below, otherwise
Reviewed-by: Stephen Boyd
diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
new file mode 100644
index 000..ba5e2b4
--- /dev/null
+++ b/drivers
On 07/20/2015 07:43 AM, Srinivas Kandagatla wrote:
diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
new file mode 100644
index 000..bde5528
--- /dev/null
+++ b/drivers/nvmem/core.c
@@ -0,0 +1,384 @@
+
+static int nvmem_add_cells(struct nvmem_device *nvmem,
+
On 07/10, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting by adding
> div-rate table to lookup suitable post divider setting under
On 07/10, James Liao wrote:
> Avoid u32 overflow when calculate post divider setting, and
> increase the max post divider setting from 3 (/8) to 4 (/16).
>
> Signed-off-by: James Liao
> ---
Applied to clk-next
--
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On 07/10, James Liao wrote:
> Write postdiv and pcw settings at the same time for PLLs if postdiv
> and pcw settings are on the same register.
>
> This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
>
> Signed-off-by: James Liao
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc.
ot;.
We keep parsing old name to keep compatibility with old DTSes.
Signed-off-by: Dmitry Torokhov
Acked-by: Stephen Boyd
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Add support for over current protection (OCP), pin control
selection, soft start strength, and auto-mode.
Cc:
Signed-off-by: Stephen Boyd
---
Notes:
Changes from v3:
* Split this patch out from rest of driver
* Moved auto mode into regulator-init-mode and made it equal to FAST mode
On 07/09, Gabriel Fernandez wrote:
> @@ -270,6 +285,73 @@ static int clkgen_pll_is_enabled(struct clk_hw *hw)
> return !poweroff;
> }
>
> +static int __clkgen_pll_enable(struct clk_hw *hw)
> +{
> + struct clkgen_pll *pll = to_clkgen_pll(hw);
> + unsigned long timeout;
> + int r
On 07/15/2015 12:08 PM, Tim Bird wrote:
On 07/14/2015 06:11 PM, Stephen Boyd wrote:
On 07/14/2015 04:26 PM, Tim Bird wrote:
3 files changed, 166 insertions(+)
create mode 100644 drivers/misc/qcom-coincell.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 42c3852
On 07/14/2015 04:26 PM, Tim Bird wrote:
3 files changed, 166 insertions(+)
create mode 100644 drivers/misc/qcom-coincell.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 42c3852..0909869 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -271,6 +271,17 @@ config
On 07/10, James Liao wrote:
> Hi Stephen,
>
> On Wed, 2015-07-08 at 17:44 -0700, Stephen Boyd wrote:
> > On 07/08/2015 01:37 AM, James Liao wrote:
> > > MT8173 MMPLL frequency settings are different from common PLLs.
> > > It needs different post divider sett
On 07/10, Srinivas Kandagatla wrote:
> +static int devm_nvmem_device_match(struct device *dev, void *res, void *data)
> +{
> + struct nvmem_device **nvmem = res;
> +
> + if (!nvmem || !*nvmem) {
> + WARN_ON(!nvmem || !*nvmem);
This could be
if (WARN_ON(!nvmem || !*nvme
On 07/10, Srinivas Kandagatla wrote:
> diff --git a/Documentation/nvmem/nvmem.txt b/Documentation/nvmem/nvmem.txt
> new file mode 100644
> index 000..b074b71
> --- /dev/null
> +++ b/Documentation/nvmem/nvmem.txt
> @@ -0,0 +1,152 @@
> + NVMEM SUBSYSTEM
> + Srinivas
On 07/10, Srinivas Kandagatla wrote:
> This patch adds QFPROM support driver which is used by other drivers
> like thermal sensor and cpufreq.
>
> On MSM parts there are some efuses (called qfprom) these fuses store
> things like calibration data, speed bins.. etc. Drivers like cpufreq,
> thermal
On 07/13, Yingjoe Chen wrote:
> Add 13mhz clock used by GPT timer in infracfg.
>
> Signed-off-by: Yingjoe Chen
> ---
Acked-by: Stephen Boyd
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On 07/13, Yingjoe Chen wrote:
> When cpu is in deep idle, arch timer will stop counting. Setup GPT as
> sched clock source so it can keep counting in idle.
>
> Signed-off-by: Yingjoe Chen
> ---
Acked-by: Stephen Boyd
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On 07/08/2015 01:37 AM, James Liao wrote:
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 68af518..622e7b6 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_c
On 07/08/2015 01:37 AM, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
>
> 1. Add div-rate table for PLLs.
> 2. Increa
On 06/26/2015 02:50 PM, bj...@kryo.se wrote:
> += EXAMPLE
> +The following example shows the SMEM setup for MSM8974, with a main SMEM
> region
> +at 0xfa0 and an auxiliary region at 0xfc428000:
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1
On 07/06, Stephen Boyd wrote:
> On 07/06/2015 01:11 AM, Gabriel Fernandez wrote:
> > Hi Stephen,
> >
> > Can you drop also this patch because it's concerns an old platform and
> > there no values to make more changes.
>
> Ok, so I think this series is all
On 07/02/2015 11:29 PM, Daniel Kurtz wrote:
> Hi Stephen,
>
> On Fri, Jul 3, 2015 at 7:03 AM, Stephen Boyd wrote:
>> On 06/30, James Liao wrote:
>>> From: Sascha Hauer
>>>
>>> On the MT8173 the clocks are provided by different units. To enable
>&g
On 07/05, Heiko Stuebner wrote:
> Add the devicetree binding for the cru on the rk3368 which quite similar
> structured as previous clock controllers.
>
> Signed-off-by: Heiko Stuebner
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Campbell
> Cc: Kumar Gala
> Cc: devicetree@
On 07/06/2015 01:11 AM, Gabriel Fernandez wrote:
> Hi Stephen,
>
> Can you drop also this patch because it's concerns an old platform and
> there no values to make more changes.
Ok, so I think this series is all applied then. Let me know if anything
is missing from -next.
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On 07/01/2015 09:26 PM, Daniel Kurtz wrote:
> On Thu, Jul 2, 2015 at 10:52 AM, James Liao wrote:
>> Hi Daniel,
>>
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-imgsys", "syscon"
+- #clock-cells: Must be 1
+
+The imgsys controller us
On 06/30, James Liao wrote:
> From: Sascha Hauer
>
> On the MT8173 the clocks are provided by different units. To enable
> the critical clocks we must be sure that all parent clocks are already
> registered, otherwise the parents of the critical clocks end up being
> unused and get disabled later
On 06/23, Gabriel Fernandez wrote:
> Use a generic name for this kind of PLL
>
> Signed-off-by: Gabriel Fernandez
Is this just a cleanup/nicety? I could take this patch but patch
9 needs to go through arm-soc and then we have to deal with DT
incompatibility. How about we drop these last two patc
On 06/23, Gabriel Fernandez wrote:
> From: Giuseppe Cavallaro
>
> While proving lock, the following warning happens
> and it is fixed after initializing lock in the setup
> function
>
> INFO: trying to register non-static key.
> the code is fine but needs lockdep annotation.
> turning off the lo
On 06/23, Gabriel Fernandez wrote:
> This patch fixes the mux bit-setting for ClockgenA9.
>
> Signed-off-by: Gabriel Fernandez
> ---
Applied to clk-fixes
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On 06/23, Gabriel Fernandez wrote:
> From: Pankaj Dev
>
> Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops,
> so that they reflect Hw rate after CPS wake-up when a clk_get_rate()
> is called
>
> Signed-off-by: Pankaj Dev
> Signed-off-by: Gabriel Fernandez
> ---
Applied to c
On 06/23, Gabriel Fernandez wrote:
> This patch fixes the value for disabling the FSYN channel clock.
> The 'is_enabled' returned value is also fixed.
>
> Signed-off-by: Pankaj Dev
> Signed-off-by: Gabriel Fernandez
> ---
Applied to clk-fixes
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On 06/23, Gabriel Fernandez wrote:
> Remove this duplicated code due to a bad copy / paste.
>
> Signed-off-by: Gabriel Fernandez
> ---
Applied to clk-fixes
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ked-by: Kyungmin Park
> ---
>
Looks ok.
Acked-by: Stephen Boyd
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On 06/26/2015 05:20 AM, Vitaly Andrianov wrote:
>
>
> On 06/25/2015 05:35 PM, Stephen Boyd wrote:
>>
>> There's an existing one for highbank (drivers/edac/highbank_l2_edac.c)
>> and there was a patch set for the pl310 as well[1]. I don't think we
>> w
On 06/25/2015 02:30 PM, santosh shilimkar wrote:
> On 6/25/2015 2:02 PM, Stephen Boyd wrote:
>> On 06/25/2015 08:04 AM, santosh shilimkar wrote:
>>> On 6/25/2015 7:31 AM, Vitaly Andrianov wrote:
>>>> This patch series adds support for arm L1/L2 ecc and ddr3 ec
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