On 12/05/2015 02:12 AM, Stefan Wahren wrote:
>
>> Stephen Warren <swar...@wwwdotorg.org> hat am 2. Dezember 2015 um 04:40
>> geschrieben:
>>
>>
>> On 11/19/2015 09:06 AM, Stefan Wahren wrote:
>>> Currently the pins alt3 (sdhci) are assigned to GP
On 12/05/2015 02:43 AM, Stefan Wahren wrote:
>
>> Stephen Warren <swar...@wwwdotorg.org> hat am 2. Dezember 2015 um 04:42
>> geschrieben:
>>
>>
>> On 11/19/2015 09:06 AM, Stefan Wahren wrote:
>>> The node name of the sdhci pin group d
the vf610-cosmic.dts board, is it possible to
get an ack for this too? I think you did not receive v1 of this patch
due to an old email address, sorry about that.
I thought I'd already sent an ack for this, but it looks like I forgot
somehow.
Acked-by: Stephen Warren <swar...@nvidia.
On 11/19/2015 09:06 AM, Stefan Wahren wrote:
> Only the Raspberry Pi B has a card detect pin. Specify it
> on board level because it's not free to use.
This seems fine, but it should have no effect in practice; when the SD
controller driver gpio_get()s the GPIO, the same setting will be
On 11/19/2015 09:06 AM, Stefan Wahren wrote:
> Currently the pins alt3 (sdhci) are assigned to GPIO pinctrl.
> This is bad because a user could export it to sysfs and break
> sdhci. In order to avoid that remove those pins from GPIO pintrl.
> diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
On 11/19/2015 09:06 AM, Stefan Wahren wrote:
> The node name of the sdhci pin group doesn't explain it's
> real function. So rename it.
The real function of this node is not to configure SDHCI pins, but to
set pins to alt3, as the current name states. Admittedly it's possible
that currently the
to
this combination.
CCs were acquired using (updated some email addresses):
git shortlog -sne --no-merges arch/arm/boot/dts/vf???.dtsi
Acked-by: Stephen Warren <swar...@nvidia.com>
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On 11/13/2015 09:11 AM, Thierry Reding wrote:
On Wed, Nov 04, 2015 at 01:54:15PM -0700, Stephen Warren wrote:
On 11/04/2015 10:11 AM, Thierry Reding wrote:
From: Thierry Reding <tred...@nvidia.com>
The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a
set of
On 11/13/2015 10:58 AM, Andrew Bresticker wrote:
On Fri, Nov 13, 2015 at 8:32 AM, Thierry Reding
<thierry.red...@gmail.com> wrote:
On Wed, Nov 04, 2015 at 01:59:51PM -0700, Stephen Warren wrote:
On 11/04/2015 10:11 AM, Thierry Reding wrote:
From: Thierry Reding <tred...@nvidia.com
On 11/13/2015 09:32 AM, Thierry Reding wrote:
On Wed, Nov 04, 2015 at 01:59:51PM -0700, Stephen Warren wrote:
On 11/04/2015 10:11 AM, Thierry Reding wrote:
From: Thierry Reding <tred...@nvidia.com>
Extend the binding to cover the set of feature found in Tegra210.
diff --git a/Documen
On 11/16/2015 01:30 PM, Stephen Warren wrote:
On 11/13/2015 10:58 AM, Andrew Bresticker wrote:
On Fri, Nov 13, 2015 at 8:32 AM, Thierry Reding
<thierry.red...@gmail.com> wrote:
On Wed, Nov 04, 2015 at 01:59:51PM -0700, Stephen Warren wrote:
On 11/04/2015 10:11 AM, Thierry Reding wrote:
On 11/09/2015 05:45 AM, Thierry Reding wrote:
On Mon, Oct 26, 2015 at 05:02:53PM -0600, Stephen Warren wrote:
On 10/26/2015 04:22 PM, Tom Warren wrote:
This patch adds the device tree binding doc for the Tegra
QSPI controller on Tegra210.
Acked-by: Stephen Warren <swar...@nvidia.com&g
On 11/04/2015 10:11 AM, Thierry Reding wrote:
From: Thierry Reding
The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a
set of lanes that are used for PCIe, SATA and USB.
.../bindings/phy/nvidia,tegra-xusb-padctl.txt | 359 +
On 11/04/2015 10:11 AM, Thierry Reding wrote:
From: Thierry Reding
Extend the binding to cover the set of feature found in Tegra210.
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra-xusb-padctl.txt
On 10/28/2015 02:40 PM, Alexander Aring wrote:
> This patch adds support for RPi several Power Domains and enable support
> to enable the USB Power Domain when it's not enabled before.
>
> This patch based on Eric Anholt's patch to support Power Domains. He had
> an issue about -EPROBE_DEFER
On 10/26/2015 04:22 PM, Tom Warren wrote:
This patch adds the device tree binding doc for the Tegra
QSPI controller on Tegra210.
Acked-by: Stephen Warren <swar...@nvidia.com>
(I assume if others approve the binding, Thierry will take it through
the Tegra tree)
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On 10/21/2015 10:16 AM, Stefan Wahren wrote:
Am 21.10.2015 um 04:32 schrieb Stephen Warren:
On 10/15/2015 02:47 PM, Stefan Wahren wrote:
Rebuild bcm2835_defconfig using "make bcm2835_defconfig;
make savedefconfig", and add the following features:
* Enable all bcm2835-relevant dri
On 10/11/2015 01:37 PM, Lubomir Rintel wrote:
> Essentially the same as B+.
(It'd be good practice to CC RPi patches to the ARM kernel mailing list too)
> diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
> b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
> + leds {
> + act {
> +
On 10/15/2015 02:47 PM, Stefan Wahren wrote:
> Rebuild bcm2835_defconfig using "make bcm2835_defconfig;
> make savedefconfig", and add the following features:
>
> * Enable all bcm2835-relevant drivers (MBOX, WDT, DMA,
> PWM, SND)
> * Re-enable some features to keep the current settings
>
On 10/20/2015 02:53 AM, Eric Anholt wrote:
> Stefan Wahren writes:
>
>> Since the Raspberry Pi models differ in memory amount we better
>> define it at board level. After that we are able to fix the
>> memory node of the Raspberry Pi B+ .
>> diff --git
On 10/11/2015 01:48 PM, Lubomir Rintel wrote:
> Driven via the Raspberry Pi VideoCore 4 firmware interface.
> .../bindings/thermal/raspberrypi,bcm2835-thermal.txt| 13
> +
> arch/arm/boot/dts/bcm2835-rpi.dtsi | 5 +
There should be a separate
On 10/11/2015 06:39 AM, Stefan Wahren wrote:
Am 09.10.2015 um 23:27 schrieb Eric Anholt:
This is a respin of the Raspberry Pi KMS series. Now that we've got a
real clock driver, I can actually set new video modes. Also in this
version, most of the custom DT stuff from before is gone, thanks
From: Stephen Warren <swar...@nvidia.com>
Add device-tree binding documentation for the XUSB (xHCI) controller
present on Tegra124 and later SoCs.
Signed-off-by: Andrew Bresticker <abres...@chromium.org>
[swarren, combined separate MFD, mailbox, XHCI bindings into one node
eems innocuous, but could you clarify for me how
> exactly you change the uart0 pins, and why one would do that?
I /assume/ this is so that some other DT file (that includes the
edited file) can add some pinctrl-related properties to this DT node,
using syntax such as:
{
new content;
}
From: Stephen Warren <swar...@nvidia.com>
Reword the description of the ranges property so it is correct
irrespective of how many #address-cells the PCI node's parent uses.
Be more explicit about the valid values for the compatible property, and
in particular point out that Tegra210 isn't
From: Stephen Warren <swar...@nvidia.com>
Tegra210 introduces some new options for pad muxing. Document these in
the XUSB padctl binding.
Be more explicit about the valid values for the compatible property, and
in particular point out that Tegra210 isn't fully backwards-compatible
with Te
On 09/29/2015 02:13 AM, Jon Hunter wrote:
On 28/09/15 17:36, Stephen Warren wrote:
On 09/28/2015 08:57 AM, Jon Hunter wrote:
On 25/09/15 16:47, Arnd Bergmann wrote:
On Friday 25 September 2015 16:38:55 Jon Hunter wrote:
On 25/09/15 16:17, Jon Hunter wrote:
On 25/09/15 16:03, Arnd
On 09/29/2015 06:18 AM, Jon Hunter wrote:
On 28/09/15 16:07, Arnd Bergmann wrote:
On Monday 28 September 2015 15:57:46 Jon Hunter wrote:
...
Yes that makes sense, but I think that I have confused matters here a
bit and not thought through this entirely. So while we could configure
an audio
On 09/29/2015 09:34 AM, Arnd Bergmann wrote:
On Tuesday 29 September 2015 15:18:07 Jon Hunter wrote:
On 29/09/15 13:39, Arnd Bergmann wrote:
Ok, that makes more sense then. A few questions still:
* Would the admaif in turn provide a #dma-cells and have the real slaves
hooked up to it?
I
On 09/28/2015 08:57 AM, Jon Hunter wrote:
On 25/09/15 16:47, Arnd Bergmann wrote:
On Friday 25 September 2015 16:38:55 Jon Hunter wrote:
On 25/09/15 16:17, Jon Hunter wrote:
On 25/09/15 16:03, Arnd Bergmann wrote:
On Friday 25 September 2015 15:56:40 Jon Hunter wrote:
+ case
On 09/28/2015 01:26 PM, Eric Anholt wrote:
Stephen Warren <swar...@wwwdotorg.org> writes:
On 09/10/2015 03:22 PM, Eric Anholt wrote:
These will be used for enabling UART1, SPI1, and SPI2.
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm283
On 09/25/2015 09:38 AM, Jon Hunter wrote:
On 25/09/15 16:17, Jon Hunter wrote:
On 25/09/15 16:03, Arnd Bergmann wrote:
On Friday 25 September 2015 15:56:40 Jon Hunter wrote:
+ case DMA_MEM_TO_DEV:
+ burst_size = fls(tdc->config.dst_maxburst);
+
On 09/23/2015 04:01 AM, Martin Sperl wrote:
On 22.09.2015 04:42, Stephen Warren wrote:
On 09/11/2015 05:20 AM, ker...@martin.sperl.org wrote:
From: Martin Sperl <ker...@martin.sperl.org>
Add the auxiliary uart1 device to the device tree of the bcm2835 SOC.
diff --git a/arch/arm/bo
On 09/10/2015 03:22 PM, Eric Anholt wrote:
> These will be used for enabling UART1, SPI1, and SPI2.
Patches 1, 3,
Acked-by: Stephen Warren <swar...@wwwdotorg.org>
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On 09/10/2015 03:22 PM, Eric Anholt wrote:
> There are a pair of SPI masters and a mini UART that were last minute
> additions. As a result, they didn't get integrated in the same way as
> the other gates off of the VPU clock in CPRMAN.
> diff --git a/drivers/clk/bcm/clk-bcm2835-aux.c
>
now have a correct
> clock rate if the user configures the boot-time core clock speed using
> config.txt.
Acked-by: Stephen Warren <swar...@wwwdotorg.org>
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On 09/14/2015 07:53 AM, Eric Anholt wrote:
> ker...@martin.sperl.org writes:
>
>> From: Martin Sperl
>>
>> The bcm2835 SOC contains an auxiliary uart, which is very close
>> to the ns16550 with some differences.
>>
>> The big difference is that the uart HW is not
On 09/11/2015 04:22 AM, ker...@martin.sperl.org wrote:
> From: Martin Sperl <ker...@martin.sperl.org>
>
> This defines the spi1 and spi2 devices in the device-tree.
Patches 1, 3, 4,
Acked-by: Stephen Warren <swar...@wwwdotorg.org>
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On 09/10/2015 03:22 PM, Eric Anholt wrote:
> These will be used for enabling UART1, SPI1, and SPI2.
> diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
> + aux_clocks: aux-clocks@0x7e215004 {
> + compatible = "brcm,bcm2835-aux-clock";
>
On 09/10/2015 02:58 PM, Eric Anholt wrote:
> This adds support for enabling, disabling, and setting the rate of the
> audio domain clocks. It will be necessary for setting the pixel clock
> for HDMI in the VC4 driver and let us write a cpufreq driver. It will
> also improve compatibility with
On 09/10/2015 02:58 PM, Eric Anholt wrote:
> Previously we've only supported a few fixed clocks based on
> assumptions about how the firmware sets up the clocks, but this
> binding will let us control the actual (audio power domain) clock
> manager.
Patches 1 and 2,
Acked-by: Stephen
On 09/11/2015 05:20 AM, ker...@martin.sperl.org wrote:
> From: Martin Sperl
>
> Add the auxiliary uart1 device to the device tree of the bcm2835 SOC.
> diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
> + uart1: uart@7e215040 {
>
On 09/17/2015 11:21 AM, Andrew F. Davis wrote:
>
>
> On 09/17/2015 12:20 PM, Rob Herring wrote:
>> On Thu, Sep 17, 2015 at 10:53 AM, Andrew F. Davis wrote:
>>> On 09/16/2015 08:26 PM, Rob Herring wrote:
On Wed, Sep 16, 2015 at 4:07 PM, Andrew F. Davis wrote:
On 08/28/2015 11:27 AM, Simon Glass wrote:
> Hi Rob,
>
> On 25 August 2015 at 10:22, Rob Herring wrote:
>> On Sat, Aug 15, 2015 at 8:46 AM, Simon Glass wrote:
>>> Hi Rob,
>>>
>>> On 14 August 2015 at 14:29, Rob Herring wrote:
On 09/04/2015 01:26 AM, Martin Sperl wrote:
>
>> On 26.08.2015, at 03:44, Stephen Warren <swar...@wwwdotorg.org> wrote:
>>
>> On 08/24/2015 02:40 AM, ker...@martin.sperl.org wrote:
>>
>>> +Example:
>>> +
>>> +aux_enable: aux_enable@0x7e2
On 08/24/2015 02:40 AM, ker...@martin.sperl.org wrote:
From: Martin Sperl ker...@martin.sperl.org
Patch description?
diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-aux.txt
b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-aux.txt
+Required properties:
+-
On 08/24/2015 02:40 AM, ker...@martin.sperl.org wrote:
From: Martin Sperl ker...@martin.sperl.org
Patch description?
diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt
b/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt
+Required properties:
+-
On 08/24/2015 02:40 AM, ker...@martin.sperl.org wrote:
From: Martin Sperl ker...@martin.sperl.org
The bcm2835 SOC contains 3 auxiliar devices (spi1, spi2 and uart1)
that all are enabled via a shared register.
To serialize access to this shared register this soc-driver
is created that
On 08/24/2015 02:40 AM, ker...@martin.sperl.org wrote:
From: Martin Sperl ker...@martin.sperl.org
Patch description?
arch/arm/configs/bcm2835_defconfig |1 +
drivers/spi/Kconfig| 12 +
drivers/spi/Makefile |1 +
drivers/spi/spi-bcm2835aux.c |
On 08/18/2015 03:54 PM, Eric Anholt wrote:
We need to use it for getting video modes over HDMI.
This patch,
Acked-by: Stephen Warren swar...@wwwdotorg.org
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On 08/18/2015 03:54 PM, Eric Anholt wrote:
VC4 is the GPU (display and 3D) present on the 2835.
This patch and patch 1 seem OK to me, although I'll withhold any ack
until the DT binding design discussion with Rob has been resolved. I
haven't looked at the OF graph bindings he mentioned so have
Ian Lepore wrote at Friday, August 14, 2015 11:46 AM:
On Fri, 2015-08-14 at 09:27 -0500, Rob Herring wrote:
On Thu, Aug 13, 2015 at 2:04 PM, Ian Lepore i...@freebsd.org wrote:
On Thu, 2015-08-13 at 14:13 -0400, Tom Rini wrote:
On Thu, Aug 13, 2015 at 10:02:58AM -0600, Stephen Warren
On 08/12/2015 06:56 PM, Eric Anholt wrote:
diff --git a/MAINTAINERS b/MAINTAINERS
+DRM DRIVERS FOR VC4
+M: Eric Anholt e...@anholt.net
+T: git git://github.com/anholt/linux
+S: Maintained
+F: drivers/gpu/drm/vc4/*
S: Supported
?
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On 08/12/2015 06:56 PM, Eric Anholt wrote:
Signed-off-by: Eric Anholt e...@anholt.net
This one definitely needs a patch description, since someone might not
know what a VC4 is, and git log won't show the text from the binding
doc itself. I'd suggest adding the initial paragraph of the binding
On 08/12/2015 06:56 PM, Eric Anholt wrote:
We need to use it for getting video modes over HDMI.
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
+ i2c2: i2c@7e805000 {
+ compatible = brcm,bcm2835-i2c;
+ reg =
On 08/12/2015 06:56 PM, Eric Anholt wrote:
Signed-off-by: Eric Anholt e...@anholt.net
Patch description?
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
arm-pmu {
compatible = arm,arm1176-pmu;
};
+
+
: DT node names
usually contain a device type not a device identity, so clocks not
firmware-clocks would be typical.
This patch,
Acked-by: Stephen Warren swar...@wwwdotorg.org
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On 08/12/2015 07:21 AM, Simon Glass wrote:
Hi Lucas,
On 11 August 2015 at 11:05, Lucas Stach d...@lynxeye.de wrote:
Hi Simon,
why did you send this to the Tegra ML?
Am Dienstag, den 11.08.2015, 08:25 -0600 schrieb Simon Glass:
This updates the device tree from the kernel version to
On 08/13/2015 05:05 PM, Eric Anholt wrote:
Unfortunately, the clock manager's registers are not accessible by the
ARM, so we have to request that the firmware modify our clocks for us.
This driver only registers the clocks at the point they are requested
by a client driver. This is
On 08/12/2015 06:56 PM, Eric Anholt wrote:
This is the start of a full VC4 driver. Right now this just supports
configuring the display using a pre-existing video mode (because
changing the pixel clock isn't available yet, and doesn't work when it
is). However, this is enough for fbcon and
On 08/13/2015 01:04 PM, Ian Lepore wrote:
On Thu, 2015-08-13 at 14:13 -0400, Tom Rini wrote:
On Thu, Aug 13, 2015 at 10:02:58AM -0600, Stephen Warren wrote:
On 08/13/2015 09:59 AM, Simon Glass wrote:
Hi Linus,
On 11 August 2015 at 07:00, Linus Walleij linus.wall...@linaro.org wrote:
On Fri
On 08/13/2015 09:59 AM, Simon Glass wrote:
Hi Linus,
On 11 August 2015 at 07:00, Linus Walleij linus.wall...@linaro.org wrote:
On Fri, Aug 7, 2015 at 3:42 PM, Simon Glass s...@chromium.org wrote:
This binding differs from that of Linux. Update it and change existing
users.
Signed-off-by:
On 08/11/2015 11:05 AM, Lucas Stach wrote:
Hi Simon,
why did you send this to the Tegra ML?
At my request, so that the DT changes could be reviewed by the kernel DT
reviewers and added to the copy of the DT files in the kernel source
tree if approved.
My assertion is that DT content
On 08/07/2015 07:42 AM, Simon Glass wrote:
This binding differs from that of Linux. Update it and change existing
users.
Is that meant to imply that this patch fixes the copy of the binding doc
in U-Boot so it does match the kernel's copy?
Changes in v3:
- Rename binding file to pl01x.txt
On 08/10/2015 10:11 PM, Simon Glass wrote:
HI Stephen,
On 10 August 2015 at 21:57, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/07/2015 07:42 AM, Simon Glass wrote:
This binding differs from that of Linux. Update it and change existing
users.
Is that meant to imply that this patch
On 07/28/2015 12:18 AM, Martin Sperl wrote:
Hi Stephen!
On 28.07.2015, at 04:51, Stephen Warren swar...@wwwdotorg.org wrote:
If this is not acceptable, then where should such a driver go in the
kernel tree?
It would essentially implement the following:
bcm2835aux_enable(dev, device-id
On 07/28/2015 04:48 AM, Martin Sperl wrote:
On 28.07.2015 08:18, Martin Sperl wrote:
Hi Stephen!
But the bigger question you have not answered is: “where should such an
auxiliar driver go in the kernel tree?” i.e. which directory?
One thing: could the module be a regulator?
The HW docs
On 07/24/2015 12:47 AM, Martin Sperl wrote:
On 24.07.2015, at 06:09, Stephen Warren swar...@wwwdotorg.org wrote:
I think I'd expect the shared registers to be:
bcm2835aux: misc@0x7e215000 {
compatible = brcm,bcm2835-aux;
reg = 0x7e215000 0x08;
};
There are two 4-byte registers
On 07/22/2015 10:28 AM, Martin Sperl wrote:
On 22.07.2015, at 03:55, Stephen Warren swar...@wwwdotorg.org wrote:
However, I'd like to see a semantic driver for the shared register
region rather than a syscon. IIUC, syscon simply provides a stylized
way for one driver to touch some shared
On 07/22/2015 12:17 PM, Eric Anholt wrote:
Stephen Warren swar...@wwwdotorg.org writes:
On 07/13/2015 07:35 PM, Eric Anholt wrote:
The BCM2836 (Raspberry Pi 2) uses two levels of interrupt
handling with the CPU-local interrupts being the root, so we
need to register ours as chained off
)
+{
+ pr_err(%d: unmask PMU\n, smp_processor_id());
+ writel(1 smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
+}
Are those pr_err() calls left-over debug, or is there some reason it's
an error to call those functions?
Aside from this and the other minor comment, the series,
Acked-by: Stephen
On 07/13/2015 07:35 PM, Eric Anholt wrote:
The BCM2836 (Raspberry Pi 2) uses two levels of interrupt handling
with the CPU-local interrupts being the root, so we need to register
ours as chained off of the CPU's local interrupt.
Sorry for the slow review; laziness after vacation!
diff --git
On 07/14/2015 06:39 AM, Martin Sperl wrote:
On 14.07.2015, at 14:56, Stephen Warren swar...@wwwdotorg.org wrote:
I don't care so much about the internal code details; anything there can
be trivially changed. But please do make sure the DT correctly
represents the HW by:
* Having
On 07/20/2015 02:35 PM, Andrey Danin wrote:
NVEC driver was reimplemented to use tegra i2c. Use common i2c bindings
for NVEC node.
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts
b/arch/arm/boot/dts/tegra20-paz00.dts
+ nvec: nvec@45 {
+ compatible =
On 07/20/2015 02:35 PM, Andrey Danin wrote:
Remove i2c controller related code and use tegra i2c driver in slave mode.
Update nvec documentation.
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
I would expect this
On 07/11/2015 12:01 AM, Eric Anholt wrote:
Stephen Warren swar...@wwwdotorg.org writes:
On 07/07/2015 03:13 PM, Eric Anholt wrote:
This is a new per-cpu root interrupt controller on the
Raspberry Pi 2, which will chain to the bcm2835 interrupt
controller for peripheral interrupts.
diff
On 07/11/2015 01:51 AM, Thomas Gleixner wrote:
On Fri, 10 Jul 2015, Stephen Warren wrote:
On 07/07/2015 03:13 PM, Eric Anholt wrote:
+static struct arm_local_intc intc __read_mostly;
It'd be nice to give everything (types, functions, variables) a
consistent symbol prefix
On 07/04/2015 07:14 PM, Martin Sperl wrote:
On 02.07.2015, at 06:57, Noralf Trønnes nor...@tronnes.org wrote:
Den 01.07.2015 21:39, skrev Martin Sperl:
On 30.06.2015, at 19:42, Mark Brown broo...@kernel.org wrote:
This looks relevant:
On 22.06.2015, at 16:55, Jakub Kiciński
On 07/07/2015 03:13 PM, Eric Anholt wrote:
This is a new per-cpu root interrupt controller on the Raspberry Pi 2,
which will chain to the bcm2835 interrupt controller for peripheral
interrupts.
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt
On 07/07/2015 03:13 PM, Eric Anholt wrote:
This interrupt controller is the new root interrupt controller with
the timer, PMU events, and IPIs, and the bcm2835's interrupt
controller is chained off of it to handle the peripherals.
SMP IPI support was mostly written by Andrea Merello, while I
On 06/22/2015 09:26 AM, Martin Sperl wrote:
On 22.06.2015, at 16:55, Jakub Kiciński moorr...@wp.pl wrote:
As mentioned by Noralf UART1 is quite commonly used on Compute Modules.
Proper driver - perhaps modelled as a bus - seems like a prerequisite
for this work. You are also not using IRQ mux
On 06/22/2015 07:40 AM, ker...@martin.sperl.org wrote:
From: Martin Sperl ker...@martin.sperl.org
This driver does NOT make use of native chip-selects but uses the
generic cs-gpios facilities provided by the framework allowing for
more than 3 chip-selects.
diff --git
On 06/25/2015 04:54 AM, ker...@martin.sperl.org wrote:
From: Martin Sperl ker...@martin.sperl.org
Patch description? I'd suggest deriving this from the first paragraph in
the binding doc.
diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt
On 07/10/2015 03:29 AM, Tomeu Vizoso wrote:
On 1 July 2015 at 19:36, Rob Herring robherri...@gmail.com wrote:
On Wed, Jul 1, 2015 at 7:45 AM, Tomeu Vizoso tomeu.viz...@collabora.com wrote:
When an OF node has a pin range for its GPIOs, return -EPROBE_DEFER if
the pin controller isn't
On 07/10/2015 10:21 AM, Tomeu Vizoso wrote:
On 10 July 2015 at 17:27, Stephen Warren swar...@wwwdotorg.org wrote:
On 07/10/2015 03:29 AM, Tomeu Vizoso wrote:
On 1 July 2015 at 19:36, Rob Herring robherri...@gmail.com wrote:
On Wed, Jul 1, 2015 at 7:45 AM, Tomeu Vizoso tomeu.viz
.
Isn't it in an earlier commit now (patch 2/3)? :-)
At a quick glance, I think this approach will be fine, so the series,
Acked-by: Stephen Warren swar...@nvidia.com
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On 06/23/2015 05:56 AM, Roger Quadros wrote:
+ Kukjin, Stephen,
for board specific USB question.
On Tue, 23 Jun 2015 16:35:49 +0800
Li Jun b47...@freescale.com wrote:
On Tue, Jun 23, 2015 at 10:43:28AM +0300, Roger Quadros wrote:
If the dr_mode was otg for such case and we want OTG
On 06/17/2015 06:38 AM, Ludovic Desroches wrote:
Hi Stephen,
On Mon, Jun 15, 2015 at 09:58:05AM -0600, Stephen Warren wrote:
On 06/10/2015 09:04 AM, Ludovic Desroches wrote:
When having a controller which allows per pin muxing, declaring with
which groups a function can be used is a useless
On 06/16/2015 02:42 AM, Tomeu Vizoso wrote:
On 2 June 2015 at 17:40, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/02/2015 05:28 AM, Linus Walleij wrote:
On Tue, May 26, 2015 at 9:41 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 05/25/2015 08:53 AM, Tomeu Vizoso wrote:
Specify
On 06/16/2015 03:39 AM, Noralf Trønnes wrote:
Den 16.06.2015 05:07, skrev Stephen Warren:
On 06/13/2015 05:39 AM, Noralf Trønnes wrote:
This adds a new poweroff function to the watchdog driver for the
Raspberry Pi. Currently poweroff/halt results in a reboot.
The Raspberry Pi firmware uses
On 06/10/2015 09:04 AM, Ludovic Desroches wrote:
When having a controller which allows per pin muxing, declaring with
which groups a function can be used is a useless constraint since groups
are something virtual.
This isn't true.
Irrespective of whether a particular piece of pinmux HW can
On 06/10/2015 09:04 AM, Ludovic Desroches wrote:
Using a string to describe a pin in the device tree can be not enough.
Some controllers may need extra information to fully describe a pin. It
concerns mainly controllers which have a per pin muxing approach which
don't fit well the notions of
On 06/13/2015 05:39 AM, Noralf Trønnes wrote:
The Raspberry Pi uses a new value for halt in the PM_RSTS watchdog
register. Expand the compatible string to cover this.
FWIW, the series,
Tested-by: Stephen Warren swar...@wwwdotorg.org
... but that doesn't imply my ack for the patches
On 06/15/2015 10:45 AM, Jon Hunter wrote:
Adding linux-tegra ML ...
Oh, still none of the Tegra maintainers are CC'd. scripts/get_maintainer.pl.
On 13/06/15 05:21, Kyle Huey wrote:
This patch modifies the device tree for tegra124 based devices to enable the
Cortex A15 PMU. The interrupt
On 06/13/2015 05:39 AM, Noralf Trønnes wrote:
This adds a new poweroff function to the watchdog driver for the
Raspberry Pi. Currently poweroff/halt results in a reboot.
The Raspberry Pi firmware uses the RSTS register to know which
partiton to boot from. The partiton value is spread into
On 06/10/2015 01:33 AM, Linus Walleij wrote:
On Wed, Jun 3, 2015 at 3:31 PM, Nicolas Ferre nicolas.fe...@atmel.com wrote:
Le 04/05/2015 10:56, Ludovic Desroches a écrit :
The way pins, groups and functions are tied is too constraining for some
controllers. It concerns mainly the ones we don't
On 06/05/2015 01:21 PM, Lee Jones wrote:
On Thu, 04 Jun 2015, Stephen Warren wrote:
On 06/04/2015 02:11 PM, Eric Anholt wrote:
This gives us a function for making mailbox property channel requests
of the firmware, which is most notable in that it will let us get and
set clock rates.
Acked
On 05/29/2015 03:02 PM, Eric Anholt wrote:
Stephen Warren swar...@wwwdotorg.org writes:
On 05/18/2015 01:43 PM, Eric Anholt wrote:
+static struct clk *rpi_firmware_delayed_get_clk(struct
of_phandle_args *clkspec, + void *_data)
+ rpi_clk = rpi_clocks[clkspec-args[0
On 06/04/2015 02:11 PM, Eric Anholt wrote:
This gives us a function for making mailbox property channel requests
of the firmware, which is most notable in that it will let us get and
set clock rates.
Acked-by: Stephen Warren swar...@wwwdotorg.org
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On 06/02/2015 05:28 AM, Linus Walleij wrote:
On Tue, May 26, 2015 at 9:41 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 05/25/2015 08:53 AM, Tomeu Vizoso wrote:
Specify how the GPIOs map to the pins in T124, so the dependency is
explicit.
Signed-off-by: Tomeu Vizoso tomeu.viz
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