{
status = disabled;
compatible = arm,pl022, arm,primecell;
Tested-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Acked-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
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For patch 1,4,5,6,and 7, I have tested this on AMD Seattle platform.
Tested-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Thanks,
Suravee
On 5/21/15 03:32, fu@linaro.org wrote:
From: Fu Wei fu@linaro.org
This patchset:
(1)Export arch_timer_get_rate
Sorry for delay response. I have also tested this on AMD Seattle
platform w/ PCI Generic Host Controller, and I can see that the PCI
endpoint devices are getting proper dma_map_ops as set in the host bridge.
Tested-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Thanks,
Suravee
On 02
Hi,
I am not sure if this thread is still alive. I'm trying to see what I
can do to help clean up/convert to make the PCI GHC also works for arm64
w/ zero or minimal ifdefs.
Please let me know if someone is already working on this. I noticed that
Lorenzo's patches has already been in
On 11/4/14 04:06, Thomas Gleixner wrote:
On Mon, 3 Nov 2014, Suravee Suthikulanit wrote:
On 11/3/2014 4:51 PM, Thomas Gleixner wrote:
On Mon, 3 Nov 2014, suravee.suthikulpa...@amd.com wrote:
+ irq_domain_set_hwirq_and_chip(v2m-domain, virq, hwirq,
+
On 11/4/14 07:01, Jiang Liu wrote:
Hi Suravee,
You may build a two level hierarchy irqdomains. Use the
utilities in this thread
http://www.spinics.net/lists/arm-kernel/msg374722.html to build an MSI
irqdomain to manage MSI controllers
in PCI devices. And build another irqdomain to manage
On 09/23/2014 08:41 PM, Bjorn Helgaas wrote:
On Tue, Sep 23, 2014 at 7:18 PM, Liviu Dudau li...@dudau.co.uk wrote:
On Tue, Sep 23, 2014 at 08:01:12PM +0100, Liviu Dudau wrote:
If the firmware has not assigned all the bus resources and
we are not just probing the PCIe busses, it makes sense to
.),
and will be submitted separately.
Since this patch is independent from the multi-MSI stuff. Please let me
know if you would consider taking this separately.
Thanks,
Suravee
On 09/28/2014 03:53 PM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM
Thomas,
Sorry again for the mistake on my part. Let me try to address some other
concerns you have below.
On 09/22/2014 04:08 PM, Thomas Gleixner wrote:
On Sat, 20 Sep 2014, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch
On 9/8/2014 8:54 AM, Liviu Dudau wrote:
This is my version 10 of the attempt at adding support for generic PCI host
bridge controllers that make use of device tree information to
configure themselves. This version reverses v9's attempt to create one function
to drive the whole process of
On 9/12/2014 4:30 AM, Liviu Dudau wrote:
On Fri, Sep 12, 2014 at 09:25:13AM +0100, Suravee Suthikulpanit wrote:
On 9/8/2014 8:54 AM, Liviu Dudau wrote:
This is my version 10 of the attempt at adding support for generic PCI host
bridge controllers that make use of device tree information
On 9/8/2014 8:54 AM, Liviu Dudau wrote:
If the firmware has not assigned all the bus resources and
we are not just probing the PCIe busses, it makes sense to
assign the unassigned resources in pci_scan_root_bus().
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Jason
On 08/15/2014 09:03 AM, Marc Zyngier wrote:
+
+static struct irq_chip gicv2m_chip;
+
+#ifdef CONFIG_OF
Is there any reason why this should be guarded by CONFIG_OF? Surely the
v2m capability should only be enabled if OF is.
[Suravee]
We are also planning to support ACPI in the future also,
On 08/14/2014 12:55 PM, Mark Rutland wrote:
On Wed, Aug 13, 2014 at 04:00:40PM +0100, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch
On 08/13/2014 09:56 PM, Jingoo Han wrote:
On Thursday, August 14, 2014 12:01 AM, Suravee Suthikulpanit wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support
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