rtised
by the flash in its ONFI information (either stronger or weaker). But
in this case, your commit log is confusing, because it says that the
"NAND device ... uses 4-bit BCH ECC protection". If it really does,
then the patch is not needed :-)
Best regards,
Thomas
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(). For the
vast majority of platforms, this is OK. It's only if you have 4 GB
of RAM or more that it causes problem. And then we switch to
mv_mbus_dram_info_nooverlap() as part of the -rc cycle.
(2) is probably easier. Herbert, what do you think?
Thomas
--
Thomas Petazzoni, CTO, Free
is written to AUX_CTRL), bit 28 is correctly set to 1. However, after
AUX_CTRL is written, it's restored to 0.
How does your patch handles the fact that the prefetch data and
prefetch instr are cloned between PREFETCH_CTRL and AUX_CTRL ?
Thanks,
Thomas
--
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Embedded
, and
it's now done: with ARM: l2c: write auxiliary control register first
+ Hauke's patch, it works fine for me.
Thanks!
Thomas
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Great, thanks!
Thomas
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.
Thanks,
Thomas
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, but this is weird: I just
checked the datasheet again, and it really says this pin is a gpo.
I'll try to get some more information.
Best regards,
Thomas
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,
Thomas
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.
Of course, we need at least one tested board for each SoC, however.
Best regards,
Thomas
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+= board level ranges
in .dts, we simply decided to always put:
ranges = SoC level and board level ranges
in the .dts.
It does create some duplication, but that's the best we could do with
the existing DT infrastructure.
Best regards,
Thomas
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will
disable it at the end of the boot. Check if crypto still works or not,
and you'll get your answer :-)
Thomas
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-specific hardware blocks that are definitely a lot less used than
the GIC ?
Best regards,
Thomas Petazzoni
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to slave the
upgrade of the dtb to the upgrade of the kernel. There is no 'apt-get
armv7-dtbs' that has no dependency structure on a kernel package. So we
agree, (2) was never guaranteed, and isn't probable either.
And so is (1), then :-)
Thomas
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Embedded
of the RTC are at 0xd8500, which is
also covered by this new pmu node. It does work because you're using
of_iomap(), but it isn't really ideal.
Maybe some sort of syscon/regmap thing should be used?
Best regards,
Thomas
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Embedded Linux, Kernel and Android
,
GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH,
GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH;
And ditto for all other interrupts properties?
Thanks,
Thomas
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him to merge PATCH
v3 11/20.
With this done, and PATCH v2 20/20 merged by the arm-soc maintainers, I
guess we should be all set with this patch series.
Thanks again!
Best regards,
Thomas
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Dear Linus Walleij,
On Wed, 4 Mar 2015 13:54:42 +0100, Linus Walleij wrote:
On Fri, Feb 6, 2015 at 4:57 PM, Thomas Petazzoni
thomas.petazz...@free-electrons.com wrote:
This commit adds a new pinctrl driver for the Marvell Armada 39x
family of processors, which hooks into the existing
started working all right.
Thanks,
Thomas
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The Device Tree nodes describing the MPIC nodes on Armada 370, 375,
38x and XP had a unit address that did not match the first reg
property, as suggested by the ePAPR. This commit fixes that.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370
.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts | 2 +-
arch/arm/boot/dts/armada-370-mirabox.dts | 2 +-
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 2 +-
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 2
-muxing, clocks, system controller, MBus
controller, MPIC interrupt controller, timer, CPU reset for SMP,
PMSU.
* I2C
* SPI
* SDHCI
* XOR
* NAND
* UART
* PCIe
Additional features will be supported in the future.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
This commit adds the Device Tree binding documentation to describe the
pin-muxing controller of the Marvell Armada 39x processors. Two
variants are supported for the moment: the 88F6920 (Armada 390) and
88F6928 (Armada 398).
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
differences in the available functions for
certain pins.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/pinctrl/mvebu/Kconfig | 4 +
drivers/pinctrl/mvebu/Makefile | 1 +
drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 432
- Use GIC and IRQ macros in SDHCI definition of Armada 38x
- Add missing UART alias on Armada 38x
Thanks!
Thomas
Thomas Petazzoni (20):
ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat
tables
ARM: mvebu: fix usb@ unit address on Armada 38x to match register
The Armada 38x had a label for UART0, but not UART1. This commit fixes
that.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-38x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion
As suggested by Stephen Boyd, this commit adds the __initconst
specifier to the dt_compat table declarations used by the
DT_MACHINE_START structures in mach-mvebu land.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
is 25 or 40 Mhz. Therefore, this commit extends the common
mvebu clock code to allow the SoC-specific code to say it wants to
register a reference clock, by giving a non-NULL -get_refclk_freq()
function pointer in its coreclk_soc_desc structure.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free
This commit updates the ARM CPUs Device Tree binding to document a new
enable method of Marvell Armada 39x processors.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
On Marvell Armada 38x, the USB2 controller registers are at 0x58000,
so the corresponding Device Tree node should have a unit address of
58000, and not 5. We were using 5 due to an incorrect
copy/pastebin of Armada 370/XP code.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free
some aliases to it.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-xp.dtsi | 2 --
arch/arm/boot/dts/armada-375.dtsi| 2 --
arch/arm/boot/dts/armada-38x.dtsi| 3 ---
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 -
arch/arm/boot
This commit adds 'serialX' aliases for the various serial ports on
Armada 370, 375, 38x and XP platforms. It will allow the usage of the
stdout-path property.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-xp.dtsi | 2 ++
arch/arm/boot/dts
The Marvell Armada 39x is a family of two SoCs: the Armada 390 and the
Armada 398, with a slightly different number of interfaces. This
commit introduces the Device Tree binding that documents the top-level
compatible strings for Armada 39x based platforms.
Signed-off-by: Thomas Petazzoni
clock in frequency
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/clk/mvebu/Kconfig | 4 ++
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-39x.c | 156 +
3 files changed, 161 insertions(+)
create mode
Following the introduction of the Marvell Armada 39x support, let's
enabled it by default in mvebu_v7_defconfig.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/configs/mvebu_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs
Following the introduction of the Marvell Armada 39x support, let's
enable this support by default in multi_v7_defconfig.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: a...@kernel.org
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff
This commit adds the standard uart0 and uart1 DT labels to the Device
Tree description of the Marvell Armada 375 SoC.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-375.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
as doing the same thing as the
marvell,armada-380-smp one.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/mach-mvebu/Kconfig | 14 ++
arch/arm/mach-mvebu/board-v7.c | 14 ++
arch/arm/mach-mvebu/platsmp-a9.c | 2 ++
3 files changed, 30
.
Mark forgot the ''. So does 'stdout-path = uart0:115200n8;' work?
I don't have the board at hand right now, will try this on Tuesday when
coming back to the office. Thanks for the suggestion!
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android
was explicitly suggested by Mark in his e-mail. uart0 is an alias
to the proper DT node, since stdout-path = uart0; works almost fine.
This is all on v4.0-rc1. Seems like this stdout-path feature is not
quite working in all situations yet.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Gregory,
On Mon, 23 Feb 2015 16:27:02 +0100, Gregory CLEMENT wrote:
I already submitted this fix as part of the fixes and improvements for
SDHCI series.
Ok, I will drop this patch from my series. Thanks!
Thomas
--
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Embedded Linux, Kernel and Android
, will be in v3, rebased on top of 4.0-rc1.
I also noticed another issue in the patch series: missing Armada 375
UART aliases. I'll fix that up as well when sending v3.
Thanks for the feedback!
Thomas
--
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Embedded Linux, Kernel and Android engineering
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binding file ?
Best regards,
Thomas
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tables.
Will be in v2.
Thanks!
Thomas
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that is best left at the board level.
Best regards,
Thomas
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defaults.
Fair enough :)
Thomas
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clock in frequency
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/clk/mvebu/Kconfig | 4 ++
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-39x.c | 156 +
3 files changed, 161 insertions(+)
create mode
As suggested by Stephen Boyd, this commit adds the __initconst
specifier to the dt_compat table declarations used by the
DT_MACHINE_START structures in mach-mvebu land.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/mach-mvebu/board-v7.c | 6 +++---
arch/arm
This commit adds the Device Tree binding documentation to describe the
pin-muxing controller of the Marvell Armada 39x processors. Two
variants are supported for the moment: the 88F6920 (Armada 390) and
88F6928 (Armada 398).
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
This commit updates the ARM CPUs Device Tree binding to document a new
enable method of Marvell Armada 39x processors.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
is 25 or 40 Mhz. Therefore, this commit extends the common
mvebu clock code to allow the SoC-specific code to say it wants to
register a reference clock, by giving a non-NULL -get_refclk_freq()
function pointer in its coreclk_soc_desc structure.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free
differences in the available functions for
certain pins.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/pinctrl/mvebu/Kconfig | 4 +
drivers/pinctrl/mvebu/Makefile | 1 +
drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 432
.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-38x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-38x.dtsi
b/arch/arm/boot/dts/armada-38x.dtsi
index 8c76a8d..0f0cc41 100644
--- a/arch/arm/boot/dts
The Armada 38x had an alias for UART0, but not UART1. This commit
fixes that.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-38x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-38x.dtsi
b/arch
On Marvell Armada 38x, the USB2 controller registers are at 0x58000,
so the corresponding Device Tree node should have a unit address of
58000, and not 5. We were using 5 due to an incorrect
copy/pastebin of Armada 370/XP code.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free
With the introduction of the Marvell Armada 39x SoC, the DT bindings
for Marvell EBU clocks need to be extended. This commit include the
corresponding update to the Device Tree bindings documentation.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
.../devicetree/bindings
, clocks, system controller, MBus
controller, MPIC interrupt controller, timer, CPU reset for SMP,
PMSU.
* I2C
* UART
* PCIe
Additional features will be supported in the future.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 2
This commit adds the stdout-path property in /chosen for all Armada
boards that were not yet carrying this property.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts | 1 +
arch/arm/boot/dts/armada-370-mirabox.dts
as doing the same thing as the
marvell,armada-380-smp one.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/mach-mvebu/Kconfig | 14 ++
arch/arm/mach-mvebu/board-v7.c | 14 ++
arch/arm/mach-mvebu/platsmp-a9.c | 2 ++
3 files changed, 30
The Marvell Armada 39x is a family of two SoCs: the Armada 390 and the
Armada 398, with a slightly different number of interfaces. This
commit introduces the Device Tree binding that documents the top-level
compatible strings for Armada 39x based platforms.
Signed-off-by: Thomas Petazzoni
regards,
Thomas
Thomas Petazzoni (15):
ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat
tables
ARM: mvebu: fix usb@ unit address on Armada 38x to match register
address
ARM: mvebu: add missing UART alias on Armada 38x
ARM: mvebu: use IRQ macros to define the SDHCI
Now that we support Armada 39x, let's add this family of SoC to the
Marvell documentation, and a reference to a link with more details
about those processors. Unfortunately, no datasheet is publicly
available at this time.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
is 25 or 40 Mhz. Therefore, this commit extends the common
mvebu clock code to allow the SoC-specific code to say it wants to
register a reference clock, by giving a non-NULL -get_refclk_freq()
function pointer in its coreclk_soc_desc structure.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free
. Such an early posting is done to gather early review and
feedback. I'll repost an updated series that takes into account the
initial feedback once 3.20-rc1 lands.
Thanks,
Thomas Petazzoni
Thomas Petazzoni (10):
devicetree: bindings: add DT binding for the Marvell Armada 39x SoC
family
This commit updates the ARM CPUs Device Tree binding to document a new
enable method of Marvell Armada 39x processors.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
With the introduction of the Marvell Armada 39x SoC, the DT bindings
for Marvell EBU clocks need to be extended. This commit include the
corresponding update to the Device Tree bindings documentation.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
.../devicetree/bindings
the same thing as the marvell,armada-380-smp one.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/mach-mvebu/Kconfig | 14 ++
arch/arm/mach-mvebu/board-v7.c | 14 ++
arch/arm/mach-mvebu/platsmp-a9.c | 2 ++
3 files changed, 30
, clocks, system controller, MBus
controller, MPIC interrupt controller, timer, CPU reset for SMP,
PMSU.
* I2C
* UART
* PCIe
Additional features will be supported in the future.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 2
differences in the available functions for
certain pins.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/pinctrl/mvebu/Kconfig | 4 +
drivers/pinctrl/mvebu/Makefile | 1 +
drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 432
clock in frequency
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/clk/mvebu/Kconfig | 4 ++
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-39x.c | 156 +
3 files changed, 161 insertions(+)
create mode
Now that we support Armada 39x, let's add this family of SoC to the
Marvell documentation, and a reference to a link with more details
about those processors. Unfortunately, no datasheet is publicly
available at this time.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
The Marvell Armada 39x is a family of two SoCs: the Armada 390 and the
Armada 398, with a slightly different number of interfaces. This
commit introduces the Device Tree binding that documents the top-level
compatible strings for Armada 39x based platforms.
Signed-off-by: Thomas Petazzoni
This commit adds the Device Tree binding documentation to describe the
pin-muxing controller of the Marvell Armada 39x processors. Two
variants are supported for the moment: the 88F6920 (Armada 390) and
88F6928 (Armada 398).
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
the default
+ timeout is 1000ms
I think this description lacks one information: the timeout of *what* ?
Best regards,
Thomas
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Embedded Linux, Kernel and Android engineering
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?
Thanks,
Thomas
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-rtc;
+ reg = 0xa3800 0x20, 0x184a0 0x0c;
Any reason to use 0x184A0 0xC instead of 0x184A8 0x4 ? According to
the datasheet, there is only this 184A8 register for RTC stuff.
Thanks,
Thomas
--
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Embedded Linux, Kernel and Android engineering
http://free
Dear Gregory CLEMENT,
On Thu, 8 Jan 2015 18:38:09 +0100, Gregory CLEMENT wrote:
+#include armada-385.dtsi
Is it an Armada 385 or an Armada 388 ?
Thanks,
Thomas
--
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Embedded Linux, Kernel and Android engineering
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, it remains to be confirmed, but in general most Marvell
development platforms use the superset SoC, which has all the
functionalities.
Thanks,
Thomas
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:
compatible = board, marvell,armada388, marvell,armada385,
marvell,armada380;
?
That's not what you do in the new armada-385-gp.dts. The 388 is a
superset of the 385, which itself is a superset of the 380. Should this
be reflected in this list of compatible strings?
Thanks,
Thomas
--
Thomas
regards,
Thomas
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definitely be welcome.
Thanks,
Thomas
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with an A0 revision, not a B0. But
it's indeed different from the Z1 revision we have been using until now.
At least, my Armada XP GP says:
Board: DB-88F6820-GP
SoC: MV88F6828 Rev A0
Thanks,
Thomas
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Embedded Linux, Kernel and Android engineering
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-inverted;
Why do you have a wp-inverted property, with no wp-gpios property? If I
understand the DT binding correctly, wp-inverted only makes sense when
wp-gpios is used.
Thanks,
Thomas
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Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
for indentation in Device Tree files.
Thanks!
Thomas
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Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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More
driver part has been taken, and
I forgot to resubmit the mach-mvebu part of the solution. I'll do so
today.
Best regards,
Thomas
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Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Dear Linus Walleij,
On Thu, 27 Nov 2014 14:29:47 +0100, Linus Walleij wrote:
On Fri, Nov 14, 2014 at 4:21 PM, Thomas Petazzoni
thomas.petazz...@free-electrons.com wrote:
This commit adds the implementation of -suspend() and -resume()
platform_driver hooks in order to save and restore
/viewpatch.php?id=8222/1.
Thomas
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Mike,
On Mon, 24 Nov 2014 22:07:00 -0800, Mike Turquette wrote:
Quoting Thomas Petazzoni (2014-11-21 08:00:05)
This commit adds suspend/resume support for the gatable clock driver
used on Marvell EBU platforms. When getting out of suspend, the
Marvell EBU platforms go through
rails.
Best regards,
Thomas
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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to use a different protocol, we would basically have a
suspend/resume in the kernel that would not work with any Marvell
platform that uses the default bootloader.
I hope that this clarifies how things are working.
Best regards,
Thomas
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Thomas Petazzoni, CTO, Free Electrons
Embedded Linux
Dear Mike Turquette,
On Mon, 17 Nov 2014 14:46:04 -0800, Mike Turquette wrote:
Quoting Thomas Petazzoni (2014-11-14 07:21:28)
This commit adds suspend/resume support for the gatable clock driver
used on Marvell EBU platforms. When getting out of suspend, the
Marvell EBU platforms go
to the boot CPU.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Jason Cooper ja...@lakedaemon.net
Cc: linux-ker...@vger.kernel.org
---
drivers/irqchip/irq-armada-370-xp.c | 52 +
1 file changed, 52
The suspend/resume code for Armada XP has to modify certain registers
of the SDRAM controller. Therefore, we need to define a Device Tree
binding for this hardware block.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: devicetree@vger.kernel.org
Cc: Kumar Gala ga
reword the commit log, add
stable markers.]
Cc: Russell King li...@arm.linux.org.uk
Cc: sta...@vger.kernel.org # v3.8+
Fixes: de4901933f6d (arm: mm: Add support for PJ4B cpu and init routines)
Signed-off-by: Nadav Haklai nad...@marvell.com
Signed-off-by: Thomas Petazzoni thomas.petazz...@free
be understood by the bootloader boot
info mechanism.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Reviewed-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
drivers/bus/mvebu-mbus.c | 56
include/linux/mbus.h | 1 +
2 files
strex backoff delay
Thomas Petazzoni (15):
Documentation: dt-bindings: minimal documentation for MVEBU SDRAM
controller
irqchip: irq-armada-370-xp: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
gpio: mvebu: add suspend/resume support
bus: mvebu-mbus
Tree to find out which GPIOs are used to
connect to the PIC micro-controller, and then registers its
mvebu_armada_xp_gp_pm_enter() callback to the SoC-level PM code. The
SoC PM code will call back into this registered function at the very
end of the suspend procedure.
Signed-off-by: Thomas Petazzoni
is enabled or not to find out
whether we should talk to the coherency fabric using a physical
address or a virtual address. To fix that, we simply disable the MMU
when entering this function, so that the kernel is in an expected
situation.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free
In order to support suspend/resume on Armada XP, an additional set of
registers need to be described at the MBus controller level. This
commit therefore adjusts the Device Tree of the Armada 370/XP SoC to
include those registers in the MBus controller description;
Signed-off-by: Thomas Petazzoni
the guarantee that the code starting the
secondary CPUs is going to run on the boot CPU and will not be
migrated.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mach-mvebu/platsmp.c | 31
of each DRAM
chip-select using the memblock API.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mach-mvebu/board-v7.c | 51 ++
1 file changed, 51 insertions(+)
diff
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