[PATCH] ARM: dts: socfpga: add cap-sd-highspeed for SD/MMC node

From: Dinh Nguyen Enable SD highspeed support for the SoCFPGA Arria10 devkit. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH] ARM: dts: socfpga: add the clk-phase property for sd/mmc clock

From: Dinh Nguyen The CIU clock for the SD/MMC should be the sdmmc_clk and not the sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 3 ++- 1

[PATCHv7 1/3] ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries

From: Thor Thayer Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly. http://www.spinics.net/lists/devicetree/msg51117.html

[PATCH 1/2] ARM: socfpga: dts: add clock fields for I2C, UART and USB on Arria10

From: Dinh Nguyen Add the required clock fields for all the I2C nodes. Also add missing clock fields for UART0 and USB1. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 8 1 file changed, 8

[PATCHv4] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- v4: Add a non-zero ranges property for /soc node v3: change #address-cells and #size-cells to <2> change the GIC

[PATCH 2/2] ARM: socfpga: dts: enable USB and I2C on Arria10 SoCDK

From: Dinh Nguyen On the Arria10 Devkit, the I2C bus has a serial EEPROM and an RTC hanging off it. Also, enable the USB node. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 27

[RESEND PATCHv3] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- v3: change #address-cells and #size-cells to <2> change the GIC address to 0xfffc1000 update the GIC virtual CPU

[PATCv3] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen dingu...@opensource.altera.com Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- v3: change #address-cells and #size-cells to 2 change the GIC address to 0xfffc1000 update the GIC virtual CPU reg

[PATCHv2] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen dingu...@opensource.altera.com Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- v2: use interrupt-affinity for pmu node --- arch/arm64/Kconfig | 5 +

[PATCH] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen dingu...@opensource.altera.com Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm64/Kconfig | 5 + arch/arm64/boot/dts/Makefile | 1 +

[PATCHv2 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

From: Dinh Nguyen dingu...@opensource.altera.com Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git

[PATCHv2 2/4] ARM: socfpga: dts: add altr,modrst-offset property

From: Dinh Nguyen dingu...@opensource.altera.com The altr,modrst-offset property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[PATCHv2 1/4] dt-bindings: Add reset manager offsets for Arria10

From: Dinh Nguyen dingu...@opensource.altera.com The reset manager for is pretty similar to the one for SoCFPGA cyclone5/arria5 except for a few offsets. This patch adds those offsets. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- include/dt-bindings/reset/altr,rst-mgr-a10.h |

[PATCHv2 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

From: Dinh Nguyen dingu...@opensource.altera.com In order for the Arria10 to be able to re-use the reset driver for SoCFPGA Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the device tree entry. The 'altr,modrst-offset' property is the first register into the reset manager

[PATCHv2 0/4] reset: socfpga: Add reset driver support for Arria10 platform

From: Dinh Nguyen dingu...@opensource.altera.com v2: For the reset driver, assume a modrst-offset of 0x10 in order to support legacy boards that do have the property.. v1: This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The reset manager on the Arria10 is very

[PATCH 0/4] reset: socfpga: Add reset driver support for Arria10 platform

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The reset manager on the Arria10 is very similar to the one on Cyclone5/Arria5, thus I think it's best to try to re-use the same reset driver. The biggest difference

[PATCH 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

From: Dinh Nguyen dingu...@opensource.altera.com In order for the Arria10 to be able to re-use the reset driver for SoCFPGA Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the device tree entry. The 'altr,modrst-offset' property is the first register into the reset manager

[PATCH 1/4] dt-bindings: Add reset manager offsets for Arria10

From: Dinh Nguyen dingu...@opensource.altera.com The reset manager for is pretty similar to the one for SoCFPGA cyclone5/arria5 except for a few offsets. This patch adds those offsets. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- include/dt-bindings/reset/altr,rst-mgr-a10.h |

[PATCH 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

From: Dinh Nguyen dingu...@opensource.altera.com Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git

[PATCH 2/4] ARM: socfpga: dts: add altr,modrst-offset property

From: Dinh Nguyen dingu...@opensource.altera.com The altr,modrst-offset property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[PATCH] ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk

From: Dinh Nguyen dingu...@opensource.altera.com The dbg_base_clk can also have osc1 has a parent. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi

[PATCH 1/3] ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk

From: Dinh Nguyen dingu...@opensource.altera.com The l3_sp_clk's parent should be the l3_mp_clk. This will account for the extra divider that is present for the l3_mp_clk. The dbg_clk's parent should be the dbg_at_clk. This will account for the extra divider that is present for the dbg_at_clk.

[PATCH 3/3] ARM: socfpga: dts: add missing clock gates to socfpga.dtsi

From: Matthew Gerlach mgerl...@opensource.altera.com The gates for the clocks coming out of the sdram pll were missing. The change adds the missing nodes to the device tree. Signed-off-by: Matthew Gerlach mgerl...@opensource.altera.com Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com

[PATCH 2/3] ARM: socfpga: dts: Fix gpio dts entry for the correct clock

From: Dinh Nguyen dingu...@opensource.altera.com The correct clock for the HPS gpio(s) should be the l4_mp_clk. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCHv3] ARM: dts: socfpga: Add support of Terasic DE0 Atlas board

From: Dalon Westergreen dwest...@gmail.com The Terasic DE0 Atlas board is also known as the DE0-Nano board. This patch adds the DTS board file for the DE0-Nano Sockit board, and not the DE0 Nano Development Board. Signed-off-by: Dalon Westergreen dwest...@gmail.com Signed-off-by: Dinh Nguyen

[PATCHv2] ARM: dts: socfpga: Add support of Terasic DE0 Atlas board

From: Dalon Westergreen dwest...@gmail.com The Terasic DE0 Atlas board is also known as the DE0-Nano board. This patch adds the DTS board file for the DE0-Nano Sockit board, and not the DE0 Nano Development Board. Signed-off-by: Dalon Westergreen dwest...@gmail.com Signed-off-by: Dinh Nguyen

[PATCH] ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cache

From: Dinh Nguyen dingu...@opensource.altera.com Just in case the firmware did not enable data and instruction prefetch in the L2 cache controller, we enable it in the kernel. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga.dtsi | 2 ++ 1 file changed, 2

[PATCH] ARM: dts: socfpga: use stdout-path for chosen node

From: Dinh Nguyen dingu...@opensource.altera.com Use stdout-path dts property for kernel console. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi| 5 + arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 3 ++-

[PATCH] ARM: dts: socfpga: Add support of Terasic DE0 Atlas board

From: Dalon Westergreen dwest...@gmail.com The Terasic DE0 Atlas board is also known as the DE0-Nano board. Signed-off-by: Dalon Westergreen dwest...@gmail.com Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/Makefile|1 +

[RESEND PATCHv3] Documentation: DT bindings: document the clocks for Arria10

From: Dinh Nguyen dingu...@opensource.altera.com Update the bindings document for the clocks on the SoCFPGA Arria10 platform. Also fix up a spelling error for the altr,socfpga-perip-clk. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- .../devicetree/bindings/clock/altr_socfpga.txt

[PATCH] ARM: socfpga: dts: enable ethernet for Arria10 devkit

From: Dinh Nguyen dingu...@opensource.altera.com Update the arria10 gmac nodes with all the necessary properties for ethernet to function on the Arria10 devkit. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 11 +++

[PATCHv2 3/4] ARM: socfpga: dts: add clocks to the Arria10 platform

From: Dinh Nguyen dingu...@opensource.altera.com Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- v2: Add the l4_sys_free_clk node ---

[PATCHv2 0/4] clk: socfpga: Add clock driver for Arria10

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This patch series add the clock driver for the Arria10 platform. Although the Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the differences are enough to warrant it's own driver, rather than polluting the existing

[PATCHv2 1/4] clk: socfpga: update clk.h so for Arria10 platform to use

From: Dinh Nguyen dingu...@opensource.altera.com There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[PATCH RESEND] Documentation: DT bindings: add doc for Altera's SoCFPGA platform

From: Dinh Nguyen dingu...@opensource.altera.com Document altr,socfpga-cyclone5, altr,socfpga-arria5, and altr,socfpga-arria10. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- Documentation/devicetree/bindings/arm/altera.txt | 14 ++ 1 file changed, 14 insertions(+)

[PATCHv2 0/4] Add support for Arria10 devkit

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This patchset enables and tidy up support for the Arria10 devkit. Along with this patchset and the patchset for enabling clocks on the Arria10, the devkit can boot Linux. V2: - Patch ARM: socfpga: dts: enable UART1 for the debug uart adds the

[PATCHv2 1/4] ARM: socfpga: add cpu1-start-addr for Arria 10

From: Dinh Nguyen dingu...@opensource.altera.com Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index

[PATCHv2 4/4] ARM: socfpga: rename socdk board file to socdk_sdmmc

From: Dinh Nguyen dingu...@opensource.altera.com Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base

[PATCHv2 3/4] ARM: socfpga: dts: enable UART1 for the debug uart

From: Dinh Nguyen dingu...@opensource.altera.com Arria10 devkit is using UART1 for the debug uart port. Remove unused aliases. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- v2: Add removal of unused aliases --- arch/arm/boot/dts/socfpga_arria10.dtsi | 12

[PATCHv2 2/4] ARM: socfpga: disable the sdmmc, and uart nodes in the base arria10

From: Dinh Nguyen dingu...@opensource.altera.com Add status = disabled in the base DTSI for Arria10. The SDMMC and uart nodes should be enabled in the appropriate board file. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++ 1 file

[PATCHv2] ARM: socfpga: dts: Add a clock node for sdmmc CIU

From: Dinh Nguyen dingu...@opensource.altera.com The CIU(Card Interface Unit) get its clock from the sdmmc_clk_divided clock which is used to clock the card. The sdmmc_clk_divided clock is the sdmmc_clk passed through a fixed divider of 4. This patch adds the sdmmc_clk_divided node and makes the

[PATCH] ARM: socfpga: dts: Add a ciu clock node for sdmmc

From: Dinh Nguyen dingu...@opensource.altera.com The CIU(Card Interface Unit) clock is used by the dw_mmc IP to clock an SD card. The ciu_clk is the sdmmc_clk passed through a fixed divider of 4. This patch adds the ciu_clk node and makes the sdmmc_clk it's parent. Signed-off-by: Dinh Nguyen

[PATCH 1/7] ARM: socfpga: add cpu1-start-addr for Arria 10

From: Dinh Nguyen dingu...@opensource.altera.com Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index

[PATCH 1/3] clk: socfpga: update clk.h so for Arria10 platform to use

From: Dinh Nguyen dingu...@opensource.altera.com There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[PATCH 3/3] ARM: socfpga: dts: add clocks to the Arria10 platform

From: Dinh Nguyen dingu...@opensource.altera.com Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 298

[PATCH 6/7] ARM: socfpga: remove the need to map uart_io_desc

From: Dinh Nguyen dingu...@opensource.altera.com All the necessary debug uart mapping is already being done in debug_ll_io_init, there's no need for it here. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/mach-socfpga/socfpga.c | 9 - 1 file changed, 9

[PATCH 5/7] ARM: socfpga: Add support for UART1 debug uart for earlyprintk

From: Dinh Nguyen dingu...@opensource.altera.com Add support for hardware uart1 for earlyprintk support on Arria10 devkit. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/Kconfig.debug | 25 ++--- 1 file changed, 18 insertions(+), 7 deletions(-) diff

[PATCH 2/7] ARM: socfpga: disable the sdmmc, and uart nodes in the base arria10

From: Dinh Nguyen dingu...@opensource.altera.com Add status = disabled in the base DTSI for Arria10. The SDMMC and uart nodes should be enabled in the appropriate board file. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++ 1 file

[PATCH 4/7] ARM: socfpga: rename socdk board file to socdk_sdmmc

From: Dinh Nguyen dingu...@opensource.altera.com Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base

[PATCH 7/7] Documentation: DT bindings: add doc for Altera's SoCFPGA platform

From: Dinh Nguyen dingu...@opensource.altera.com Document altr,socfpga-cyclone5, altr,socfpga-arria5, and altr,socfpga-arria10. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- Documentation/devicetree/bindings/arm/altera.txt | 14 ++ 1 file changed, 14 insertions(+)

[PATCH 0/3] clk: socfpga: Add clock driver for Arria10

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This patch series add the clock driver for the Arria10 platform. Although the Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the differences are enough to warrant it's own driver, rather than polluting the existing

[PATCH 2/3] clk: socfpga: add a clock driver for the Arria 10 platform

From: Dinh Nguyen dingu...@opensource.altera.com The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5 platform that it should just have it's own driver. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- drivers/clk/socfpga/Makefile | 1 +

[PATCH 3/7] ARM: socfpga: dts: enable UART1 for the debug uart

From: Dinh Nguyen dingu...@opensource.altera.com Arria10 devkit is using UART1 for the debug uart port. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_arria10_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 0/7] ARM: socfpga: Add support for Arria10 devkit

From: Dinh Nguyen dingu...@opensource.altera.com Hi, This patchset enables and tidy up support for the Arria10 devkit. Along with this patchset and the patch for enabling clocks on the Arria10, the devkit can boot Linux. Dinh Nguyen (7): ARM: socfpga: add cpu1-start-addr for Arria 10 ARM:

[PATCH] arm: dts: socfpga: enable watchdog for socfpga platform

From: Dinh Nguyen dingu...@opensource.altera.com Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index

[PATCH] arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC

From: Dinh Nguyen dingu...@opensource.altera.com The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers

[PATCHv4 2/3] ARM: dts: socfpga: Fix SD card detect

From: Dinh Nguyen dingu...@opensource.altera.com Without this patch, the booting the SOCFPGA platform would hang at the SDMMC driver loading. The issue, debugged by Doug Anderson, turned out to be that the GPIO bank used by the SD card-detect was not set to status=okay. Also update the cd-gpios

[PATCHv4 0/3] ARM: dts: socfpga: fix booting with SD/MMC

From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA dev kit was hanging during bootup on the SD/MMC driver loading. The first patch fixes the booting and the 2nd patch adds a regulator node for the SD/MMC driver to use. v4 diff(s): - Add a new patch to rename the GPIO IP DTS node - Use

[PATCHv4 1/3] ARM: dts: socfpga: rename gpio nodes

From: Dinh Nguyen dingu...@opensource.altera.com Since the Synopsys GPIO IP can support multiple ports of varying widths, it would make more sense to have the GPIO node DTS entry as this: gpio0: gpio@ff708000{ porta{ }; }; Also, this is documented in the snps-dwapb-gpio.txt.

[PATCHv3 1/2] ARM: dts: socfpga: Fix SD card detect

From: Dinh Nguyen dingu...@opensource.altera.com Without this patch, the booting the SOCFPGA platform would hang at the SDMMC driver loading. The issue, debugged by Doug Anderson, turned out to be that the GPIO bank used by the SD card-detect was not set to status=okay. Suggested-by: Doug

[PATCHv3 2/2] ARM: dts: socfpga: Add a 3.3V fixed regulator node

From: Dinh Nguyen dingu...@opensource.altera.com Without the 3.3V regulator node, the SDMMC driver will give these warnings: dw_mmc ff704000.dwmmc0: No vmmc regulator found dw_mmc ff704000.dwmmc0: No vqmmc regulator found This patch adds the regulator node, and points the SD/MMC to the

[PATCHv3 0/2] ARM: dts: socfpga: fix booting with SD/MMC

From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA dev kit was hanging during bootup on the SD/MMC driver loading. The first patch fixes the booting and the 2nd patch adds a regulator node for the SD/MMC driver to use. v3 diff(s): Thanks to Doug Anderson, the real issue was that the

[PATCHv2 2/2] ARM: dts: socfpga: Add a 3.3V fixed regulator node

From: Dinh Nguyen dingu...@opensource.altera.com Without the 3.3V regulator node, the SDMMC driver will give these warnings: dw_mmc ff704000.dwmmc0: No vmmc regulator found dw_mmc ff704000.dwmmc0: No vqmmc regulator found This patch adds the regulator node, and points the SD/MMC to the

[PATCHv2 0/2] ARM: dts: socfpga: fix booting with SD/MMC

From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA dev kit was hanging during bootup on the SD/MMC driver loading. The first patch fixes the booting and the 2nd patch adds a regulator node for the SD/MMC driver to use. v2 diff(s): Patch 2/2 ARM: dts: socfpga: Add a 3.3V fixed regulator

[PATCHv2 1/2] ARM: dts: socfpga: Fix SD card detect

From: Dinh Nguyen dingu...@opensource.altera.com Without this patch, the booting the SOCFPGA platform would hang at the SDMMC driver loading. There were 2 patches that caused this to happen: - Patch 9795a846e10 mmc: dw_mmc: remove dw_mci_of_cd_gpio/wp_gpio() removed looking for cd-gpios, since

[PATCH 1/2] ARM: dts: socfpga: Fix SD card detect

From: Dinh Nguyen dingu...@opensource.altera.com Without this patch, the booting the SOCFPGA platform would hang at the SDMMC driver loading. There were 2 patches that caused this to happen: - Patch 9795a846e10 mmc: dw_mmc: remove dw_mci_of_cd_gpio/wp_gpio() removed looking for cd-gpios, since

[PATCH 2/2] ARM: dts: socfpga: Add a 3.3V fixed regulator node

From: Dinh Nguyen dingu...@opensource.altera.com Without the 3.3V regulator node, the SDMMC driver will give these warnings: dw_mmc ff704000.dwmmc0: No vmmc regulator found dw_mmc ff704000.dwmmc0: No vqmmc regulator found This patch adds the regulator node, and points the SD/MMC to the

[PATCH 0/2] ARM: dts: socfpga: fix booting with SD/MMC

From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA dev kit was hanging during bootup on the SD/MMC driver loading. The first patch fixes the booting and the 2nd patch adds a regulator node for the SD/MMC driver to use. Dinh Nguyen (2): ARM: dts: socfpga: Fix SD card detect ARM:

[PATCH] reset: socfpga: use arch_initcall for early initialization

From: Dinh Nguyen dingu...@opensource.altera.com There are certain drivers that are required to get loaded very early using arch_initcall. An example of such a driver is the SOCFPGA's FPGA bridge driver. This driver has to get loaded early because it needs to enable FPGA components that are

[PATCH] arm: dts: socfpga: Add OCRAM node

From: Dinh Nguyen dingu...@opensource.altera.com At a 64KB ocram node for SOCFPGA. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi

[PATCHv3 3/3] ARM: dts: socfpga: memreserve first 4KB for future system use

From: Dinh Nguyen dingu...@opensource.altera.com This patch adds a /memreserve/ section to reserve the first 4K for future use by the system. One possible use-case is trampoline code used to bring secondary cores online. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Pavel

[PATCHv3 2/3] ARM: dts: socfpga: Add SD card detect

From: Dinh Nguyen dingu...@opensource.altera.com Revision D of the SOCFGPA devkit has a GPIO line used for SD/MMC card detect. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Pavel Machek pa...@denx.de --- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 2 +-

[PATCHv3 1/3] ARM: dts: socfpga: remove extra alias in the ArriaV devkit

From: Dinh Nguyen dingu...@opensource.altera.com commit [2755e187 dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.] added an extra ethernet alias in the ArriaV devkit board file. This patch removes it. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[PATCHv3 0/3] ARM: dts: socfpga: updates for SOCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Just a few DTS updates for the SOCFPGA platform. v3: patch 1/3 : same as v2 patch 2/3 : same as v2 patch 3/3 : Updated commit message based on Mark Rutland's comment. Dinh Nguyen (3): ARM: dts: socfpga: remove extra alias in the ArriaV devkit

[PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to bring secondary cores online. This patch adds a /memreserve/ section to reserve the first 4K for the SMP trampoline code. Signed-off-by: Dinh Nguyen

[PATCH 1/3] ARM: dts: socfpga: remove extra alias in the ArriaV devkit

From: Dinh Nguyen dingu...@opensource.altera.com commit [2755e187 dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.] added an extra ethernet alias in the ArriaV devkit board file. This patch removes it. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[PATCH 2/3] ARM: dts: socfpga: Add SD card detect

From: Dinh Nguyen dingu...@opensource.altera.com Revision D of the SOCFGPA devkit has a GPIO line used for SD/MMC card detect. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 2 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 4

[PATCH 0/3] ARM: dts: socfpga: updates for SOCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Just a few DTS updates for the SOCFPGA platform. patch 1/3 : cleanup patch 2/3 : Add a SD/MMC card detect entry patch 3/3 : Add a /memserve/ section for the platform Dinh Nguyen (3): ARM: dts: socfpga: remove extra alias in the ArriaV devkit

[PATCHv2 1/3] ARM: dts: socfpga: remove extra alias in the ArriaV devkit

From: Dinh Nguyen dingu...@opensource.altera.com commit [2755e187 dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.] added an extra ethernet alias in the ArriaV devkit board file. This patch removes it. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com ---

[PATCHv2 0/3] ARM: dts: socfpga: updates for SOCFPGA

From: Dinh Nguyen dingu...@opensource.altera.com Just a few DTS updates for the SOCFPGA platform. v2: patch 1/3 : same as v1 patch 2/3 : same as v1 patch 3/3 : Added a single line comment for /memreserve/ Dinh Nguyen (3): ARM: dts: socfpga: remove extra alias in the ArriaV devkit ARM: dts:

[PATCHv2 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to bring secondary cores online. This patch adds a /memreserve/ section to reserve the first 4K for the SMP trampoline code. Signed-off-by: Dinh Nguyen

[PATCHv2 2/3] ARM: dts: socfpga: Add SD card detect

From: Dinh Nguyen dingu...@opensource.altera.com Revision D of the SOCFGPA devkit has a GPIO line used for SD/MMC card detect. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Pavel Machek pa...@denx.de --- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 2 +-

[PATCHv2 1/2] usb: dwc2: Disable descriptor dma mode by default

From: Dinh Nguyen dingu...@altera.com Even though the IP supports Descriptor DMA mode, it does not support SPLIT transactions in this mode. So the driver, in its currently form, will not support LS/FS devices when connected to a HS Hub if Descriptor DMA mode is enabled. So we disable descriptor

[PATCHv2 2/2] Documentation: dt: add an optional dma-desc-enable property for dwc2 usb

From: Dinh Nguyen dingu...@altera.com The dma-desc-enable property can be used to enable descriptor DMA mode for the DWC2 USB IP. Signed-off-by: Dinh Nguyen dingu...@altera.com --- v2: Reword property description to enable instead of disable --- Documentation/devicetree/bindings/usb/dwc2.txt |

[PATCH 1/2] usb: dwc2: Option to disable dma descriptor mode

From: Dinh Nguyen dingu...@altera.com Even though the IP supports Descriptor DMA mode, it does not support SPLIT transactions in this mode. Since the driver can get the Descriptor DMA mode support from hardware, the driver in its currently form cannot fully support LS/FS devices connected to a HS

[PATCH 2/2] Documentation: dt: add an optional dma-desc-enable property for dwc2 usb

From: Dinh Nguyen dingu...@altera.com The dma-desc-enable property can be used to disable descriptor DMA mode for the DWC2 USB IP. Signed-off-by: Dinh Nguyen dingu...@altera.com --- Documentation/devicetree/bindings/usb/dwc2.txt |5 + 1 file changed, 5 insertions(+) diff --git

[PATCH] dts: socfpga: Add DTS entries for USB

From: Dinh Nguyen dingu...@altera.com Update all the SOCFPGA DTS files with USB entries. Signed-off-by: Dinh Nguyen dingu...@altera.com --- arch/arm/boot/dts/socfpga.dtsi| 30 + arch/arm/boot/dts/socfpga_arria5_socdk.dts|4

[PATCH] dt-bindings: add vendor-prefix for Newhaven Display

From: Dinh Nguyen dingu...@altera.com Newhaven Display provides the worldwide marketplace with cost effective high quality display devices ranging from OLED and LCD Displays to VFD Displays. Signed-off-by: Dinh Nguyen dingu...@altera.com --- .../devicetree/bindings/vendor-prefixes.txt|

[PATCH 2/3] dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.

From: Dinh Nguyen dingu...@altera.com This patch adds the dts bindings documenation for the Altera SOCFPGA glue layer for the Synopsys STMMAC ethernet driver. Signed-off-by: Dinh Nguyen dingu...@altera.com --- .../devicetree/bindings/net/socfpga-dwmac.txt | 27

[PATCH net-next 1/3] net: stmmac: Add SOCFPGA glue driver

From: Dinh Nguyen dingu...@altera.com Like the STi and sunxi series SOCs, Altera's SOCFPGA also needs a glue layer on top of the Synopsys gmac IP. This patch adds the platform driver for the glue layer which configures the IP before the generic STMMAC driver takes over. Signed-off-by: Dinh

[PATCH 3/3] dts: stmmac: Document the clocks property in the stmmac base document

From: Dinh Nguyen dingu...@altera.com Add the clocks and clock-names property to the base stmmac dts bindings document. Signed-off-by: Dinh Nguyen dingu...@altera.com --- Documentation/devicetree/bindings/net/stmmac.txt |6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCH net-next 0/3] net: stmmac: Add glue layer for socfpga platform

From: Dinh Nguyen dingu...@altera.com Hi David, I'm re-submitting the patch series to add the socfpga glue layer for the stmmac ethernet driver. My original patch did not build for kernel module, and I apologize for not testing against that. This patch is also better aligned with the other

[PATCH 1/3] net: stmmac: improve binding and fix build

From: Dinh Nguyen dingu...@altera.com The new stmmac front-end for socfpga caused build failures for modular drivers, e.g. 'make allmodconfig', which prompted me to look closer into it. I found that both the DT binding and the implementation of the driver are rather nonstandard and do things very

[PATCH 0/3] Fix stmmac-socfpga allmodconfig breakage in arm-soc

From: Dinh Nguyen dingu...@altera.com Hi, These 3 patches are based on Arnd's patch to fix the allmodconfig for the dwmac-socfpga implementation. I just broke the patch out into drivers, dts, and dts documentation. The original patch is here:

[PATCH 3/3] dts: documentation: Update documentation for the stmmac ethernet controller

From: Dinh Nguyen dingu...@altera.com * Add optional clocks and clock-names property into the base stmmac document. * Update socfpga-dwmac.txt with new compatible string and example binding. Signed-off-by: Arnd Bergmann a...@arndb.de Signed-off-by: Dinh Nguyen dingu...@altera.com ---

[PATCHv2 3/3] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform

From: Dinh Nguyen dingu...@altera.com Introduce altr,socfpga-dw-mshc to enable Altera's SOCFPGA platform specific implementation of the dwc_mmc driver. Also add the syscon binding to the altr,sys-mgr node. The clock driver can use the syscon driver to toggle the register for the SD/MMC clock

[PATCHv2 2/3] mmc: dw_mmc: Add support for SOCFPGA's platform specific implementation

From: Dinh Nguyen dingu...@altera.com Like the rockchip, Altera's SOCFPGA platform specific implementation of the dw_mmc driver requires using the HOLD register for SD commands. Signed-off-by: Dinh Nguyen dingu...@altera.com Acked-by: Steffen Trumtrar s.trumt...@pengutronix.de Tested-by: Steffen

[PATCHv3 1/3] mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc

From: Dinh Nguyen dingu...@altera.com It turns now that the only really platform specific code that is needed for SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_command function. Since the Rockchip already has this functionality, re-use the code that is already in dw_mmc-pltfm.c.

[PATCHv3 3/3] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform

From: Dinh Nguyen dingu...@altera.com Introduce altr,socfpga-dw-mshc to enable Altera's SOCFPGA platform specific implementation of the dwc_mmc driver. Also add the syscon binding to the altr,sys-mgr node. The clock driver can use the syscon driver to toggle the register for the SD/MMC clock

[PATCHv3 2/3] mmc: dw_mmc: Add support for SOCFPGA's platform specific implementation

From: Dinh Nguyen dingu...@altera.com Like the rockchip, Altera's SOCFPGA platform specific implementation of the dw_mmc driver requires using the HOLD register for SD commands. This patch renames dw_mci_rockchip_prepare_command to dw_mci_pltfm_prepare_command so that SOCFPGA and Rockchip can use

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