From: Tirumalesh Chalamarla tchalama...@cavium.com
The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
Thunder SoCs by adding an entry to DT.
Signed-off-by: Tirumalesh Chalamarla tchalama...@cavium.com
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arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 9 +
1 file
From: Tirumalesh Chalamarla tchalama...@cavium.com
The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
Thunder SoCs by adding an entry to DT.
Signed-off-by: Tirumalesh Chalamarla tchalama...@cavium.com
Acked-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/boot/dts/cavium
Hi Will,
On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon will.dea...@arm.com wrote:
Hi Tirumalesh,
On Wed, Aug 27, 2014 at 07:02:21PM +0100, c.tirumal...@gmail.com wrote:
From: Tirumalesh Chalamarla tchalama...@cavium.com
This patch modifes output_mask calculation logic for stage 1 and allow
On Mon, Sep 1, 2014 at 8:12 AM, Will Deacon will.dea...@arm.com wrote:
On Mon, Sep 01, 2014 at 02:49:58PM +0100, tirumalesh chalamarla wrote:
On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon will.dea...@arm.com wrote:
Assuming I understand the problem correctly, why not simply remove
