On 11/29/2013 06:00 AM, Thierry Reding wrote:
On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
...
@@ -110,6 +118,8 @@ reg = 0x5408 0x0004; interrupts =
GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH; clocks = tegra_car
TEGRA30_CLK_VI; + resets = tegra_car 164;
I
On Sun, Dec 01, 2013 at 12:15:07PM -0700, Stephen Warren wrote:
On 11/29/2013 06:00 AM, Thierry Reding wrote:
On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
[...]
reg = 0x70080300 0x100; nvidia,ahub-cif-ids = 4 4; clocks =
tegra_car TEGRA114_CLK_I2S0;
The clocks for
On 11/29/2013 06:00 AM, Thierry Reding wrote:
On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
[...]
@@ -135,8 +140,10 @@ reg-shift = 2; interrupts = GIC_SPI 37
IRQ_TYPE_LEVEL_HIGH; nvidia,dma-request-selector = apbdma 9;
-status = disabled; clocks = tegra_car
On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
[...]
@@ -135,8 +140,10 @@
reg-shift = 2;
interrupts = GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH;
nvidia,dma-request-selector = apbdma 9;
- status = disabled;
clocks =
From: Stephen Warren swar...@nvidia.com
An earlier patch updated the Tegra DT bindings to require resets and
reset-names properties to be filled in. This patch updates the DT files
to include those properties.
Note that any legacy clocks and clock-names entries that are replaced by
reset
