On 09/08/2015 08:09 AM, Linus Walleij wrote:
> On Fri, Aug 28, 2015 at 12:24 PM, Masahiro Yamada
> wrote:
>> 2015-08-26 22:39 GMT+09:00 Linus Walleij :
>
>>> cache-unified and cache-level are *not* optional and should be required.
>>
>> "cache-unified" is mentioned in "3.7.3 Internal (L1) Cache P
On Fri, Aug 28, 2015 at 12:24 PM, Masahiro Yamada
wrote:
> 2015-08-26 22:39 GMT+09:00 Linus Walleij :
>> cache-unified and cache-level are *not* optional and should be required.
>
> "cache-unified" is mentioned in "3.7.3 Internal (L1) Cache Properties"
> (Table 3-8),
> but it is not in "3.8 Multi
Hi Linus,
2015-08-26 22:39 GMT+09:00 Linus Walleij :
> On Mon, Aug 24, 2015 at 4:18 AM, Masahiro Yamada
> wrote:
>> This commit adds support for UniPhier outer cache controller.
>> All the UniPhier SoCs are equipped with the L2 cache, while the L3
>> cache is currently only integrated on PH1-Pro
On Wed, Aug 26, 2015 at 02:52:45PM +0200, Arnd Bergmann wrote:
> On Wednesday 26 August 2015 10:38:59 Masahiro Yamada wrote:
> > Moreover, outer-cache init seems to be unrelated to
> > IRQ init.
>
> Agreed, this is also just a historic artifact, as we don't really
> have a place to put cache contr
Hi Arnd, Russell,
2015-08-26 21:52 GMT+09:00 Arnd Bergmann :
> On Wednesday 26 August 2015 10:38:59 Masahiro Yamada wrote:
>>
>> 2015-08-25 4:59 GMT+09:00 Arnd Bergmann :
>> > On Monday 24 August 2015 11:18:10 Masahiro Yamada wrote:
>
>> Nothing.
>>
>> This outer cache is not a variant of l2x0/pl
On Mon, Aug 24, 2015 at 4:18 AM, Masahiro Yamada
wrote:
> This commit adds support for UniPhier outer cache controller.
> All the UniPhier SoCs are equipped with the L2 cache, while the L3
> cache is currently only integrated on PH1-Pro5 SoC.
>
> Signed-off-by: Masahiro Yamada
Wow it is really a
On Wednesday 26 August 2015 10:38:59 Masahiro Yamada wrote:
>
> 2015-08-25 4:59 GMT+09:00 Arnd Bergmann :
> > On Monday 24 August 2015 11:18:10 Masahiro Yamada wrote:
> Nothing.
>
> This outer cache is not a variant of l2x0/pl310.
> It was designed only for our SoCs from scratch.
Ok, I see.
>
Hi Arnd,
2015-08-25 4:59 GMT+09:00 Arnd Bergmann :
> On Monday 24 August 2015 11:18:10 Masahiro Yamada wrote:
>> diff --git
>> a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
>> b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
>> new file mode 100644
>> in
On Monday 24 August 2015 11:18:10 Masahiro Yamada wrote:
> diff --git
> a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
> b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
> new file mode 100644
> index 000..6428289
> --- /dev/null
> +++ b/Documentation/d
Hi Joe,
2015-08-24 11:29 GMT+09:00 Joe Perches :
> On Mon, 2015-08-24 at 11:18 +0900, Masahiro Yamada wrote:
>> This commit adds support for UniPhier outer cache controller.
>> All the UniPhier SoCs are equipped with the L2 cache, while the L3
>> cache is currently only integrated on PH1-Pro5 SoC
On Mon, 2015-08-24 at 11:18 +0900, Masahiro Yamada wrote:
> This commit adds support for UniPhier outer cache controller.
> All the UniPhier SoCs are equipped with the L2 cache, while the L3
> cache is currently only integrated on PH1-Pro5 SoC.
style trivia:
You might add and use
#define
This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.
Signed-off-by: Masahiro Yamada
---
.../bindings/arm/uniphier/cache-uniphier.txt | 30 ++
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