[PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

2014-08-14 Thread dinguyen
From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to bring secondary cores online. This patch adds a /memreserve/ section to reserve the first 4K for the SMP trampoline code. Signed-off-by: Dinh Nguyen

Re: [PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

2014-08-14 Thread Pavel Machek
On Thu 2014-08-14 10:51:31, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to bring secondary cores online. This patch adds a /memreserve/ section to reserve the first 4K for the

Re: [PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

2014-08-14 Thread Dinh Nguyen
On 8/14/14, 1:54 PM, Pavel Machek wrote: On Thu 2014-08-14 10:51:31, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to bring secondary cores online. This patch adds a /memreserve/

Re: [PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

2014-08-14 Thread Pavel Machek
On Thu 2014-08-14 15:56:53, Dinh Nguyen wrote: On 8/14/14, 1:54 PM, Pavel Machek wrote: On Thu 2014-08-14 10:51:31, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to bring