On Wed, Nov 06, 2013 at 01:56:18PM +0100, Laurent Pinchart wrote:
> Hi Simon,
>
> On Wednesday 06 November 2013 16:18:09 Simon Horman wrote:
> > On Tue, Oct 29, 2013 at 03:55:11PM +0100, Laurent Pinchart wrote:
> > > The R8A7790 has several clocks that are too custom to be supported in a
> > > gen
Hi Laurent
> > Thank yor for your agreement.
> > I don't want to send "rename patch",
> > please consider it in your v2 patch if possible :P
>
> We also need to take into account that the two SoCs will have a different
> number of clocks. I'm thus inclined to replace the index-based switch
> s
Hi Morimoto-san,
On Thursday 07 November 2013 16:06:29 Kuninori Morimoto wrote:
> Hi Laurent
>
> > Sure, if the hardware is very similar, it makes sense to share code. I've
> > had a quick look at the M2 documentation, and it seems to be indeed
> > mostly identical to H2. Only a couple of clocks
Hi Laurent
> Sure, if the hardware is very similar, it makes sense to share code. I've had
> a quick look at the M2 documentation, and it seems to be indeed mostly
> identical to H2. Only a couple of clocks are missing, and a new GPU clock
> register is documented. As the GPU clock is mentione
Hi Morimoto-san,
On Wednesday 06 November 2013 23:20:32 Kuninori Morimoto wrote:
> Hi Laurent again
>
> > In my SuperH experience, CPG clock divier has same pattern.
> > In H2's SDCKCR register, SDHFC and SD0FC looks different.
> > But, the real different is only enabled bit area,
> > the value i
Hi Laurent again
> In my SuperH experience, CPG clock divier has same pattern.
> In H2's SDCKCR register, SDHFC and SD0FC looks different.
> But, the real different is only enabled bit area,
> the value is same.
> You can find same pattern on FRQCRB register too,
> and, you can find same pattern
Hi Laurent
> > Now, your [1/3] patch (= for MSTP) added renesas special property
> > as "renesas,clock-indices".
> > Is it impossible to add renesas special property like
> > "renesas,clock-custom-divider" which can specify custom divider values in
> > generic cpg driver ?
> > If we can have it,
Hi Simon,
On Wednesday 06 November 2013 16:18:09 Simon Horman wrote:
> On Tue, Oct 29, 2013 at 03:55:11PM +0100, Laurent Pinchart wrote:
> > The R8A7790 has several clocks that are too custom to be supported in a
> > generic driver. Those clocks can be divided in two categories:
> >
> > - Fixed r
Hi Magnus,
(CC'ing Grant Likely)
On Wednesday 06 November 2013 17:19:48 Magnus Damm wrote:
> On Wed, Nov 6, 2013 at 8:47 AM, Laurent Pinchart wrote:
> > On Tuesday 05 November 2013 16:56:40 Magnus Damm wrote:
> >> On Tue, Oct 29, 2013 at 11:55 PM, Laurent Pinchart wrote:
> >> > The R8A7790 has se
Hi Morimoto-san,
On Tuesday 05 November 2013 18:31:31 Kuninori Morimoto wrote:
> Hi Laurent
>
> > > Please correct me if my understanding was wrong.
> > > Does your "of_clk_get_parent_name()" means "case R8A7790_CLK_MAIN"'s one
> > > ?
> > > If Yes, it is needed on "parent" clock side, not here ?
Hi Laurent,
On Wed, Nov 6, 2013 at 8:47 AM, Laurent Pinchart
wrote:
> Hi Magnus,
>
> (And a question for Mike below)
>
> On Tuesday 05 November 2013 16:56:40 Magnus Damm wrote:
>> On Tue, Oct 29, 2013 at 11:55 PM, Laurent Pinchart wrote:
>> > The R8A7790 has several clocks that are too custom to
On Tue, Oct 29, 2013 at 03:55:11PM +0100, Laurent Pinchart wrote:
> The R8A7790 has several clocks that are too custom to be supported in a
> generic driver. Those clocks can be divided in two categories:
>
> - Fixed rate clocks with multiplier and divisor set according to boot
> mode configurat
Hi Laurent
> > Please correct me if my understanding was wrong.
> > Does your "of_clk_get_parent_name()" means "case R8A7790_CLK_MAIN"'s one ?
> > If Yes, it is needed on "parent" clock side, not here ?
> > If No, who need/call of_clk_get_parent_name() for this ?
> > does "qspi", "sdh", "sd0", "
Hi Morimoto-san,
On Tuesday 05 November 2013 16:54:31 Kuninori Morimoto wrote:
> Hi Laurent
>
> > > > + for (i = 0; i < CPG_NUM_CLOCKS; ++i) {
> > > > + const struct clk_div_table *table = NULL;
> > > > + const char *parent_name = "main";
> > > > +
Hi Laurent
> > > + for (i = 0; i < CPG_NUM_CLOCKS; ++i) {
> > > + const struct clk_div_table *table = NULL;
> > > + const char *parent_name = "main";
> > > + const char *name;
> > > + unsigned int shift;
> > > + unsigned int mult = 1;
> > > + unsign
Hi Morimoto-san,
On Tuesday 05 November 2013 00:52:29 Kuninori Morimoto wrote:
> Hi Laurent
>
> > +Required Properties:
> > +
> > + - compatible: Must be "renesas,r8a7790-cpg-clocks"
> > + - reg: Base address and length of the memory resource used by the CPG
> > + - clocks: Reference to the pa
Hi Magnus,
(And a question for Mike below)
On Tuesday 05 November 2013 16:56:40 Magnus Damm wrote:
> On Tue, Oct 29, 2013 at 11:55 PM, Laurent Pinchart wrote:
> > The R8A7790 has several clocks that are too custom to be supported in a
> > generic driver. Those clocks can be divided in two categor
Hi Laurent
> +Required Properties:
> +
> + - compatible: Must be "renesas,r8a7790-cpg-clocks"
> + - reg: Base address and length of the memory resource used by the CPG
> + - clocks: Reference to the parent clock
> + - #clock-cells: Must be 1
> + - clock-output-names: The name of the clocks,
On Tue, Oct 29, 2013 at 11:55 PM, Laurent Pinchart
wrote:
> The R8A7790 has several clocks that are too custom to be supported in a
> generic driver. Those clocks can be divided in two categories:
>
> - Fixed rate clocks with multiplier and divisor set according to boot
> mode configuration
>
>
On Oct 29, 2013, at 9:55 AM, Laurent Pinchart wrote:
> The R8A7790 has several clocks that are too custom to be supported in a
> generic driver. Those clocks can be divided in two categories:
>
> - Fixed rate clocks with multiplier and divisor set according to boot
> mode configuration
>
> - C
The R8A7790 has several clocks that are too custom to be supported in a
generic driver. Those clocks can be divided in two categories:
- Fixed rate clocks with multiplier and divisor set according to boot
mode configuration
- Custom divider clocks with SoC-specific divider values
This driver s
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