On Thu, Sep 25, 2014 at 04:03:40PM -0700, Mike Turquette wrote:
Quoting Maxime Ripard (2014-09-13 03:26:03)
On Fri, Sep 12, 2014 at 11:16:26AM +0800, Chen-Yu Tsai wrote:
Hi,
On Fri, Sep 12, 2014 at 5:02 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On
Quoting Maxime Ripard (2014-09-13 03:26:03)
On Fri, Sep 12, 2014 at 11:16:26AM +0800, Chen-Yu Tsai wrote:
Hi,
On Fri, Sep 12, 2014 at 5:02 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Sat, Sep 06, 2014 at 06:47:24PM +0800, Chen-Yu Tsai wrote:
This patch
On Fri, Sep 12, 2014 at 11:16:26AM +0800, Chen-Yu Tsai wrote:
Hi,
On Fri, Sep 12, 2014 at 5:02 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Sat, Sep 06, 2014 at 06:47:24PM +0800, Chen-Yu Tsai wrote:
This patch unifies the sun6i AHB1 clock, originally supported
Hi,
On Sat, Sep 06, 2014 at 06:47:24PM +0800, Chen-Yu Tsai wrote:
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate
Hi,
On Fri, Sep 12, 2014 at 5:02 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Sat, Sep 06, 2014 at 06:47:24PM +0800, Chen-Yu Tsai wrote:
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.
Signed-off-by: Chen-Yu Tsai w...@csie.org
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