* Balaji T K [131018 08:59]:
> On Friday 18 October 2013 09:05 PM, Tony Lindgren wrote:
> >* Balaji T K [131018 00:41]:
> >>
> >>Any conclusion on using regmap for omap control module non-mux registers ?
> >
> >I don't think anybody has even started looking into a SCM driver
> >yet considering th
On Friday 18 October 2013 09:05 PM, Tony Lindgren wrote:
* Balaji T K [131018 00:41]:
Any conclusion on using regmap for omap control module non-mux registers ?
I don't think anybody has even started looking into a SCM driver
yet considering there are tons of other issues to sort out.
If yo
* Balaji T K [131018 00:41]:
>
> Any conclusion on using regmap for omap control module non-mux registers ?
I don't think anybody has even started looking into a SCM driver
yet considering there are tons of other issues to sort out.
If you're thinking about implementing the MMC PBIAS driver, I
On Friday 11 October 2013 09:31 PM, Tony Lindgren wrote:
* Linus Walleij [131011 09:05]:
On Fri, Oct 11, 2013 at 5:43 PM, Tony Lindgren wrote:
* Linus Walleij [131011 03:40]:
On Fri, Oct 11, 2013 at 10:56 AM, Roger Quadros wrote:
The register handling is fine. But how do we deal with res
* Linus Walleij [131011 09:05]:
> On Fri, Oct 11, 2013 at 5:43 PM, Tony Lindgren wrote:
> > * Linus Walleij [131011 03:40]:
> >> On Fri, Oct 11, 2013 at 10:56 AM, Roger Quadros wrote:
> >>
> >> > The register handling is fine. But how do we deal with resource handling?
> >> > e.g. the block tha
On Fri, Oct 11, 2013 at 5:43 PM, Tony Lindgren wrote:
> * Linus Walleij [131011 03:40]:
>> On Fri, Oct 11, 2013 at 10:56 AM, Roger Quadros wrote:
>>
>> > The register handling is fine. But how do we deal with resource handling?
>> > e.g. the block that has the deep-core registers might need to b
* Balaji T K [131011 08:51]:
> On Friday 11 October 2013 09:06 PM, Tony Lindgren wrote:
> >>>What the pin control driver should do is control the pins. Whether the
> >>>registers
> >>>are spread out in the entire IO-memory does not matter. We did have one
> >>>system
> >>>which placed the IO-mux
On Friday 11 October 2013 09:06 PM, Tony Lindgren wrote:
What the pin control driver should do is control the pins. Whether the registers
are spread out in the entire IO-memory does not matter. We did have one system
which placed the IO-muxing together with each peripheral (!) and I did
still wan
* Linus Walleij [131011 03:40]:
> On Fri, Oct 11, 2013 at 10:56 AM, Roger Quadros wrote:
>
> > The register handling is fine. But how do we deal with resource handling?
> > e.g. the block that has the deep-core registers might need to be clocked or
> > powered
> > before the registers can be ac
* Roger Quadros [131011 02:04]:
> On 10/11/2013 11:00 AM, Linus Walleij wrote:
> > On Thu, Oct 10, 2013 at 6:20 PM, Tony Lindgren wrote:
> >> * Linus Walleij [131010 09:19]:
> >>> On Thu, Oct 10, 2013 at 6:00 PM, Tony Lindgren wrote:
> * Roger Quadros [131010 06:32]:
> >
> > I tri
* Roger Quadros [131011 07:07]:
> On 10/11/2013 11:49 AM, Roger Quadros wrote:
> > On 10/10/2013 07:00 PM, Tony Lindgren wrote:
> >>
> >> Well the irq_set_wake() should only be needed for suspend and resume. For
> >> runtime PM
> >> the wake-events should be always enabled by default as pointed o
On 10/11/2013 11:49 AM, Roger Quadros wrote:
> On 10/10/2013 07:00 PM, Tony Lindgren wrote:
>> * Roger Quadros [131010 06:32]:
>>>
>>> I tried testing this with the USB EHCI driver, but I'm not getting wake up
>>> interrupts
>>> while the system is still running and only the EHCI controller is ru
On Fri, Oct 11, 2013 at 10:56 AM, Roger Quadros wrote:
> The register handling is fine. But how do we deal with resource handling?
> e.g. the block that has the deep-core registers might need to be clocked or
> powered
> before the registers can be accessed.
Yeah I saw this in the code there.
On 10/11/2013 11:00 AM, Linus Walleij wrote:
> On Thu, Oct 10, 2013 at 6:20 PM, Tony Lindgren wrote:
>> * Linus Walleij [131010 09:19]:
>>> On Thu, Oct 10, 2013 at 6:00 PM, Tony Lindgren wrote:
* Roger Quadros [131010 06:32]:
>
> I tried testing this with the USB EHCI driver, but I
On 10/10/2013 07:00 PM, Tony Lindgren wrote:
> * Roger Quadros [131010 06:32]:
>>
>> I tried testing this with the USB EHCI driver, but I'm not getting wake up
>> interrupts
>> while the system is still running and only the EHCI controller is runtime
>> suspended.
>>
>> It seems we need to someh
On 10/10/2013 07:23 PM, Tony Lindgren wrote:
> * Tony Lindgren [131010 09:09]:
>> * Roger Quadros [131010 06:32]:
>>>
>>> I tried testing this with the USB EHCI driver, but I'm not getting wake up
>>> interrupts
>>> while the system is still running and only the EHCI controller is runtime
>>> s
On Thu, Oct 10, 2013 at 6:20 PM, Tony Lindgren wrote:
> * Linus Walleij [131010 09:19]:
>> On Thu, Oct 10, 2013 at 6:00 PM, Tony Lindgren wrote:
>> > * Roger Quadros [131010 06:32]:
>> >>
>> >> I tried testing this with the USB EHCI driver, but I'm not getting wake
>> >> up interrupts
>> >> wh
* Linus Walleij [131010 08:40]:
> On Thu, Oct 10, 2013 at 4:35 PM, Roger Quadros wrote:
> > On 10/10/2013 05:04 PM, Linus Walleij wrote:
>
> >> As an innocent bystander who has no clue what the _reconfigure_io_chain()
> >> is about can you tell me what this is all about?
> >
> > The OMAP SoC has
* Tony Lindgren [131010 09:09]:
> * Roger Quadros [131010 06:32]:
> >
> > I tried testing this with the USB EHCI driver, but I'm not getting wake up
> > interrupts
> > while the system is still running and only the EHCI controller is runtime
> > suspended.
> >
> > It seems we need to somehow
* Linus Walleij [131010 09:19]:
> On Thu, Oct 10, 2013 at 6:00 PM, Tony Lindgren wrote:
> > * Roger Quadros [131010 06:32]:
> >>
> >> I tried testing this with the USB EHCI driver, but I'm not getting wake up
> >> interrupts
> >> while the system is still running and only the EHCI controller is
On Thu, Oct 10, 2013 at 6:00 PM, Tony Lindgren wrote:
> * Roger Quadros [131010 06:32]:
>>
>> I tried testing this with the USB EHCI driver, but I'm not getting wake up
>> interrupts
>> while the system is still running and only the EHCI controller is runtime
>> suspended.
>>
>> It seems we nee
* Roger Quadros [131010 06:32]:
>
> I tried testing this with the USB EHCI driver, but I'm not getting wake up
> interrupts
> while the system is still running and only the EHCI controller is runtime
> suspended.
>
> It seems we need to somehow call _reconfigure_io_chain() to update the daisy
On Thu, Oct 10, 2013 at 4:35 PM, Roger Quadros wrote:
> On 10/10/2013 05:04 PM, Linus Walleij wrote:
>> As an innocent bystander who has no clue what the _reconfigure_io_chain()
>> is about can you tell me what this is all about?
>
> The OMAP SoC has a mechanism to monitor and wakeup from a low p
On 10/10/2013 05:04 PM, Linus Walleij wrote:
> On Thu, Oct 10, 2013 at 3:24 PM, Roger Quadros wrote:
>
>> I think pcs_irq_set_wake() is where need to control system wakeup behaviour
>> for the irq.
>> This is where we should be able to change WAKEUP_EN bit of the pad
>> to enable/disable system
On Thu, Oct 10, 2013 at 3:24 PM, Roger Quadros wrote:
> I think pcs_irq_set_wake() is where need to control system wakeup behaviour
> for the irq.
> This is where we should be able to change WAKEUP_EN bit of the pad
> to enable/disable system wakeup for that pad and also call
> _reconfigure_io_
Hi Tony,
On 10/03/2013 08:42 AM, Tony Lindgren wrote:
> The pin control registers can have interrupts for example
> for device wake-up. These interrupts can be treated as a
> chained interrupt controller as suggested earlier by
> Linus Walleij .
>
> This patch adds support for interrupts in a way
* Linus Walleij [131008 05:18]:
> On Thu, Oct 3, 2013 at 7:42 AM, Tony Lindgren wrote:
>
> > This patch adds support for interrupts in a way that
> > should be pretty generic, and works for the omaps that
> > support wake-up interrupts. On omaps, there's an
> > interrupt enable and interrupt sta
On Thu, Oct 3, 2013 at 7:42 AM, Tony Lindgren wrote:
> This patch adds support for interrupts in a way that
> should be pretty generic, and works for the omaps that
> support wake-up interrupts. On omaps, there's an
> interrupt enable and interrupt status bit for each pin.
So to be clear: is thi
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