Hi,
Yes, we don't really care about this corner case.
Thanks for your reviewing.
BR
Gabriel
On 17 December 2014 at 15:01, One Thousand Gnomes
wrote:
> On Wed, 17 Dec 2014 11:34:46 +0100
> Gabriel FERNANDEZ wrote:
>
>> sti SoCs PCIe IPs are built around DesignWare IP Core.
>> But in these SoCs
On Wed, 17 Dec 2014 11:34:46 +0100
Gabriel FERNANDEZ wrote:
> sti SoCs PCIe IPs are built around DesignWare IP Core.
> But in these SoCs, PCIe IP doesn't support IO.
> By default, when no IO space is provided, a default one is assigned.
>
> Add an empty IO resource to the bus, and disable IO by
sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs, PCIe IP doesn't support IO.
By default, when no IO space is provided, a default one is assigned.
Add an empty IO resource to the bus, and disable IO by default.
Signed-off-by: Fabrice Gasnier
---
drivers/pci/host/pci-st.c