On Tue, Feb 18, 2014 at 02:58:14PM +, Arnd Bergmann wrote:
On Tuesday 18 February 2014, Mark Rutland wrote:
- These are Spear SoC specific miscellaneous registers. Here these are
used for
to configure sata/pcie aux clock.
+- phy-id: Instance id of the phy.
+-
Abraham I;
spear-devel; devicetree@vger.kernel.org
Subject: Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information
On Tue, Feb 11, 2014 at 09:29:59AM +, Mohit Kumar wrote:
From: Pratyush Anand pratyush.an...@st.com
ST miphy40lp can be used with PCIe, SATA and Super Speed USB
On Tuesday 18 February 2014, Mark Rutland wrote:
- These are Spear SoC specific miscellaneous registers. Here these are used
for
to configure sata/pcie aux clock.
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - 1st cell:
On Tue, Feb 11, 2014 at 09:29:59AM +, Mohit Kumar wrote:
From: Pratyush Anand pratyush.an...@st.com
ST miphy40lp can be used with PCIe, SATA and Super Speed USB
controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.
Signed-off-by: Pratyush Anand pratyush.an...@st.com
Cc: Mohit
From: Pratyush Anand pratyush.an...@st.com
ST miphy40lp can be used with PCIe, SATA and Super Speed USB
controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.
Signed-off-by: Pratyush Anand pratyush.an...@st.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Viresh
