On Wed, Oct 29, 2014 at 10:16 PM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 29 October 2014 22:09:00 Y Vo wrote:
Hi Arnd,
Per Linus, shall we hold this driver until the GIC submission complete
? Or we will send the version without access GIC to read status in
case the GPIO is
On Tuesday 16 December 2014 16:43:02 Y Vo wrote:
+static int xgene_gpio_sb_get(struct gpio_chip *gc, u32 gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct xgene_gpio_sb *chip = to_xgene_gpio_sb(mm_gc);
+ u32 data;
+
+ data =
On Fri, Oct 24, 2014 at 3:46 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 24 October 2014 14:14:43 Linus Walleij wrote:
On Wed, Oct 8, 2014 at 4:52 PM, Y Vo y...@apm.com wrote:
+ apm_gc-irq = devm_kzalloc(pdev-dev, sizeof(u32) *
XGENE_MAX_GPIO_DS,
+
On Wednesday 29 October 2014 10:52:47 Linus Walleij wrote:
On Fri, Oct 24, 2014 at 3:46 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 24 October 2014 14:14:43 Linus Walleij wrote:
See the discussion I had on this. Yes, each line is connected to a
GIC SPI interrupt by itself. I've
Hi Arnd,
Per Linus, shall we hold this driver until the GIC submission complete
? Or we will send the version without access GIC to read status in
case the GPIO is configured IRQ ?
+static int xgene_gpio_sb_get(struct gpio_chip *gc, u32 gpio)
+{
+ struct of_mm_gpio_chip *mm_gc =
On Wednesday 29 October 2014 22:09:00 Y Vo wrote:
Hi Arnd,
Per Linus, shall we hold this driver until the GIC submission complete
? Or we will send the version without access GIC to read status in
case the GPIO is configured IRQ ?
I'm fine with it either way.
+static int
On Wed, Oct 8, 2014 at 4:52 PM, Y Vo y...@apm.com wrote:
Add APM X-Gene standby GPIO controller driver.
Signed-off-by: Y Vo y...@apm.com
That's a very terse commit message. Please tell us a bit about the
hardware and what platforms it is used on, etc.
For example that is uses ACPI, as seems
On Friday 24 October 2014 14:14:43 Linus Walleij wrote:
On Wed, Oct 8, 2014 at 4:52 PM, Y Vo y...@apm.com wrote:
Add APM X-Gene standby GPIO controller driver.
Signed-off-by: Y Vo y...@apm.com
That's a very terse commit message. Please tell us a bit about the
hardware and what
On Friday 10 October 2014 10:22:34 Y Vo wrote:
APM: There are 6 GPIOs which can support IRQ, they are fixed to use
external IRQ from XGIC. (The XGIC is based on the ARM Generic
Interrupt Controller Architecture Specification, Architecture version
2.0, The XGIC provides the mechanism to
On Thursday 09 October 2014 16:31:18 Y Vo wrote:
Dear Arnd,
Thanks a lot for your review. Pls see my answer on blue text below.
Please do not send html-encoded email, it will get dropped by all mailing
lists.
On Wed, Oct 8, 2014 at 10:13 PM, Arnd Bergmann a...@arndb.de wrote:
On
Dear Arnd,
Pls see my answer below:
On Thu, Oct 9, 2014 at 7:13 PM, Arnd Bergmann a...@arndb.de wrote:
On Thursday 09 October 2014 16:31:18 Y Vo wrote:
Dear Arnd,
Thanks a lot for your review. Pls see my answer on blue text below.
Please do not send html-encoded email, it will get dropped
Add APM X-Gene standby GPIO controller driver.
Signed-off-by: Y Vo y...@apm.com
---
drivers/gpio/Kconfig |7 ++
drivers/gpio/Makefile|1 +
drivers/gpio/gpio-xgene-sb.c | 232 ++
3 files changed, 240 insertions(+)
create mode
On Wednesday 08 October 2014 21:52:26 Y Vo wrote:
+
+#define GICD_SPI_BASE0x7801
You can't hardcode register locations. Please use the proper interfaces
to do whatever you want.
It's probably not ok to map any GIC registers into the GPIO driver,
it should operate as
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