Re: [PATCH v2 1/2] i2c: davinci: Optimize clock generation on Keystone SoC

2015-09-04 Thread Grygorii Strashko
On 08/21/2015 12:46 PM, Alexander Sverdlin wrote: According to "KeyStone Architecture Inter-IC Control Bus User Guide", fixed additive part of frequency divisors (referred as "d" in the code and datasheet) always equals to 6, independent of module clock prescaler.

[PATCH v2 1/2] i2c: davinci: Optimize clock generation on Keystone SoC

2015-08-21 Thread Alexander Sverdlin
According to KeyStone Architecture Inter-IC Control Bus User Guide, fixed additive part of frequency divisors (referred as d in the code and datasheet) always equals to 6, independent of module clock prescaler. module clock frequency master clock frequency =