Hi Viresh,
Thanks for reviewing. Please see my reply below:
On 4 March 2015 at 18:15, Viresh Kumar viresh.ku...@linaro.org wrote:
On 4 March 2015 at 14:19, pi-cheng.chen pi-cheng.c...@linaro.org wrote:
In this patch, CPU clock/power domain information is added into the
platform_data of
On 5 March 2015 at 09:02, Pi-Cheng Chen pi-cheng.c...@linaro.org wrote:
In the case of Mediatek SoC, the intermediate frequency might not be one entry
of OPP table. To elaborate, the source clock node of the CPUs/Cluster on
Mediatek SoC is a mux. The mux has several PLLs as parents. When we are
On 5 March 2015 at 11:58, Viresh Kumar viresh.ku...@linaro.org wrote:
On 5 March 2015 at 09:02, Pi-Cheng Chen pi-cheng.c...@linaro.org wrote:
In the case of Mediatek SoC, the intermediate frequency might not be one
entry
of OPP table. To elaborate, the source clock node of the CPUs/Cluster on
On 4 March 2015 at 14:19, pi-cheng.chen pi-cheng.c...@linaro.org wrote:
In this patch, CPU clock/power domain information is added into the
platform_data of cpufreq-dt so that cpufreq-dt driver could check with CPUs
share clock/power. Also, intermediate frequency support is added in this
You
On 4 March 2015 at 15:45, Viresh Kumar viresh.ku...@linaro.org wrote:
+struct cpufreq_cpu_domain {
+ struct list_head node;
+ cpumask_t cpus;
+ unsigned long intermediate_freq;
This should come from DT instead of platform data.
Well, we are getting fixed this in OPP
In this patch, CPU clock/power domain information is added into the
platform_data of cpufreq-dt so that cpufreq-dt driver could check with CPUs
share clock/power. Also, intermediate frequency support is added in this
version. Since the program flows of .target_index and .target_intermediate
are
