Hi Arnd,
Ok i will try the same way that pci-versatile.c
Thanks.
Gabriel
On 16 March 2015 at 21:00, Arnd Bergmann a...@arndb.de wrote:
On Monday 16 March 2015 13:00:51 Kumar Gala wrote:
On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ gabriel.fernan...@st.com
wrote:
ST sti SoCs PCIe IPs
Hi Srinivas,
Yes, you are right.
Nevertheless i'll try the Kumar and Arnd 's request to not use DT to do that.
BR
Gabriel
On 16 March 2015 at 18:53, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
On 16/03/15 14:20, Gabriel FERNANDEZ wrote:
- bus-range: PCI bus numbers
ST sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs PCIe IP doesn't support IO.
This patch adds the possibility to disable it through
a DT property, by creating an empty IO window and by
removing PCI_COMMAND_IO from the setup register.
Signed-off-by: Fabrice Gasnier
On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ gabriel.fernan...@st.com wrote:
ST sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs PCIe IP doesn't support IO.
This patch adds the possibility to disable it through
a DT property, by creating an empty IO window and by
On 16/03/15 14:20, Gabriel FERNANDEZ wrote:
- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
specify this property, to keep backwards compatibility a range of 0x00-0xff
is assumed if not present)
+- disable_io_support: set this property for PCIe host
On Monday 16 March 2015 13:00:51 Kumar Gala wrote:
On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ gabriel.fernan...@st.com
wrote:
ST sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs PCIe IP doesn't support IO.
This patch adds the possibility to disable it
