On Oct 31, 2013, at 12:30 PM, Stephen Boyd wrote:
> On 10/30, Kumar Gala wrote:
>>
>> On Oct 30, 2013, at 4:58 PM, Stephen Boyd wrote:
>>
>>> On 10/30/13 14:56, Kumar Gala wrote:
On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:
> On 10/30/13 14:45, Kumar Gala wrote:
>> On Oct
On 10/30, Kumar Gala wrote:
>
> On Oct 30, 2013, at 4:58 PM, Stephen Boyd wrote:
>
> > On 10/30/13 14:56, Kumar Gala wrote:
> >> On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:
> >>
> >>> On 10/30/13 14:45, Kumar Gala wrote:
> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
> > +l2-ca
On Oct 30, 2013, at 4:58 PM, Stephen Boyd wrote:
> On 10/30/13 14:56, Kumar Gala wrote:
>> On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:
>>
>>> On 10/30/13 14:45, Kumar Gala wrote:
On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
> +l2-cache node containing the following properties:
On 10/30/13 14:56, Kumar Gala wrote:
> On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:
>
>> On 10/30/13 14:45, Kumar Gala wrote:
>>> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
+l2-cache node containing the following properties:
>>> Is the L1 interrupt not per core L1 cache (even if they
On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote:
> On 10/30/13 14:45, Kumar Gala wrote:
>> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
>>
>>> @@ -75,3 +77,50 @@ Example:
>>> reg = <0x101>;
>>> };
>>> };
>>> +
>>> +If the compatible string contains "qcom,k
On 10/30/13 14:45, Kumar Gala wrote:
> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
>
>> @@ -75,3 +77,50 @@ Example:
>> reg = <0x101>;
>> };
>> };
>> +
>> +If the compatible string contains "qcom,krait" there shall be an interrupts
>> +property containing
On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote:
> The Krait L1/L2 error reporting device is made up of two
> interrupts, one per-CPU interrupt for the L1 caches and one
> interrupt for the L2 cache.
>
> Cc: Mark Rutland
> Cc: Kumar Gala
> Cc:
> Signed-off-by: Stephen Boyd
> ---
> Documentat
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Mark Rutland
Cc: Kumar Gala
Cc:
Signed-off-by: Stephen Boyd
---
Documentation/devicetree/bindings/arm/cpus.txt | 49 ++