Re: [PATCH v2 4/7] clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

2014-10-06 Thread Chen-Yu Tsai
On Tue, Sep 30, 2014 at 11:54 PM, Maxime Ripard maxime.rip...@free-electrons.com wrote: On Sat, Sep 27, 2014 at 04:49:52PM +0800, Chen-Yu Tsai wrote: This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on

Re: [PATCH v2 4/7] clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

2014-10-06 Thread Chen-Yu Tsai
On Mon, Oct 6, 2014 at 8:58 PM, Chen-Yu Tsai w...@csie.org wrote: On Tue, Sep 30, 2014 at 11:54 PM, Maxime Ripard maxime.rip...@free-electrons.com wrote: On Sat, Sep 27, 2014 at 04:49:52PM +0800, Chen-Yu Tsai wrote: This patch unifies the sun6i AHB1 clock, originally supported with separate

Re: [PATCH v2 4/7] clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

2014-09-30 Thread Maxime Ripard
On Sat, Sep 27, 2014 at 04:49:52PM +0800, Chen-Yu Tsai wrote: This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate

[PATCH v2 4/7] clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

2014-09-27 Thread Chen-Yu Tsai
This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation. Signed-off-by: Chen-Yu Tsai w...@csie.org ---