Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-15 Thread Geert Uytterhoeven
Hi Mark, On Mon, Dec 7, 2015 at 9:18 PM, Geert Uytterhoeven wrote: > On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland wrote: >> On Mon, Dec 07, 2015 at 06:49:43PM +, Sudeep Holla wrote: >>> On 07/12/15 18:24, Geert Uytterhoeven wrote: >>> >+

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-09 Thread Dirk Behme
On 08.12.2015 20:16, Mark Rutland wrote: On Tue, Dec 08, 2015 at 07:50:38PM +0100, Dirk Behme wrote: On 07.12.2015 20:03, Mark Rutland wrote: On Mon, Dec 07, 2015 at 06:49:43PM +, Sudeep Holla wrote: On 07/12/15 18:24, Geert Uytterhoeven wrote: + L2_CA57: cache-controller@0 { +

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-09 Thread Mark Rutland
On Wed, Dec 09, 2015 at 05:58:38PM +0100, Dirk Behme wrote: > >>For what is the arm64 dts entry > >> > >>cpu@0 { > >>... > >>next-level-cache = <_0>; > >>}; > >> > >>L2_0: l2-cache0 { > >>compatible = "cache"; > >>}; > >> > >>good for at all, then? > > > >With the other properties from

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-09 Thread Sudeep Holla
On 09/12/15 16:58, Dirk Behme wrote: On 08.12.2015 20:16, Mark Rutland wrote: [...] With the other properties from ePAPR you can acquire information on the geometry of the cache, which cannot be acquired from architected registers. Just for my understanding: Yes, if other properties

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-09 Thread Sudeep Holla
On 09/12/15 17:21, Mark Rutland wrote: On Wed, Dec 09, 2015 at 05:58:38PM +0100, Dirk Behme wrote: For what is the arm64 dts entry cpu@0 { ... next-level-cache = <_0>; }; L2_0: l2-cache0 { compatible = "cache"; }; good for at all, then? With the other properties

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-08 Thread Sudeep Holla
On 08/12/15 18:50, Dirk Behme wrote: On 07.12.2015 20:03, Mark Rutland wrote: On Mon, Dec 07, 2015 at 06:49:43PM +, Sudeep Holla wrote: On 07/12/15 18:24, Geert Uytterhoeven wrote: +L2_CA57: cache-controller@0 { +compatible = "cache"; +arm,data-latency = <4 4 1>; +

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-08 Thread Mark Rutland
On Tue, Dec 08, 2015 at 07:50:38PM +0100, Dirk Behme wrote: > On 07.12.2015 20:03, Mark Rutland wrote: > >On Mon, Dec 07, 2015 at 06:49:43PM +, Sudeep Holla wrote: > >> > >>On 07/12/15 18:24, Geert Uytterhoeven wrote: > >>>+ L2_CA57: cache-controller@0 { > >>>+ compatible = "cache";

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-08 Thread Dirk Behme
On 07.12.2015 20:03, Mark Rutland wrote: On Mon, Dec 07, 2015 at 06:49:43PM +, Sudeep Holla wrote: On 07/12/15 18:24, Geert Uytterhoeven wrote: + L2_CA57: cache-controller@0 { + compatible = "cache"; + arm,data-latency = <4 4 1>; +

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-07 Thread Geert Uytterhoeven
Hi Mark, On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland wrote: > On Mon, Dec 07, 2015 at 06:49:43PM +, Sudeep Holla wrote: >> On 07/12/15 18:24, Geert Uytterhoeven wrote: >> >+L2_CA57: cache-controller@0 { >> >+compatible = "cache"; >> >+

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-07 Thread Geert Uytterhoeven
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node. The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways), and requires the following settings: - Tag RAM latency: 3 cycles, - Data RAM latency: 4 cycles, - Data RAM setup: 1

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-07 Thread Sudeep Holla
On 07/12/15 18:24, Geert Uytterhoeven wrote: Add device nodes for the L2 caches, and link the CPU node to its L2 cache node. The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways), and requires the following settings: - Tag RAM latency: 3 cycles, -

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

2015-12-07 Thread Mark Rutland
On Mon, Dec 07, 2015 at 06:49:43PM +, Sudeep Holla wrote: > > On 07/12/15 18:24, Geert Uytterhoeven wrote: > >+L2_CA57: cache-controller@0 { > >+compatible = "cache"; > >+arm,data-latency = <4 4 1>; > >+arm,tag-latency = <3 3 3>; > > Interesting, only