Re: [PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings

On 07/10, James Liao wrote: > Avoid u32 overflow when calculate post divider setting, and > increase the max post divider setting from 3 (/8) to 4 (/16). > > Signed-off-by: James Liao > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Founda

[PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings

Avoid u32 overflow when calculate post divider setting, and increase the max post divider setting from 3 (/8) to 4 (/16). Signed-off-by: James Liao --- drivers/clk/mediatek/clk-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/